DC Charging Capabilities of Battery-Integrated Modular Multilevel Converters Based on Maximum Tractive Power

: The increase in the average global temperature is a consequence of high greenhouse gas emissions. Therefore, using alternative energy carriers that can replace fossil fuels, especially for automotive applications, is of high importance. Introducing more electronics into an automotive battery pack provides more precise control and increases the available energy from the pack. Battery-integrated modular multilevel converters (BI-MMCs) have high efﬁciency, improved controllability, and better fault isolation capability. However, integrating the battery and inverter inﬂuences the maximum DC charging power. Therefore, the DC charging capabilities of 5 3-phase BI-MMCs for a 40-ton commercial vehicle designed for a maximum tractive power of 400kW was investigated. Two continuous DC charging scenarios are considered for two cases: the ﬁrst considers the total number of submodules during traction, and the second increases the total number of submodules to ensure a maximum DC charging voltage of 1250V. The investigation shows that both DC charging scenarios have similar maximum power between 1 and 3MW. Altering the number of submodules increases the maximum DC charging power at the cost of increased losses.


Introduction
Over the last several decades, the average global temperature has risen considerably due to greenhouse gas emissions, and the automotive industry contributes about 15% of the emissions [1,2]. It is essential to increase the utilization of alternative energy carriers to replace fossil fuels. Automotive battery packs are typically made up of modules containing several parallel and/or series-connected cells [3]. However, the energy and power are determined not only by the cell type and size but, to a large extent, also by the configuration and battery management system (BMS) [4,5]. By restructuring the cell interconnections and introducing more electronics in the pack, more precise control and, thus, better utilization of the energy in the individual modules can increase the energy and provide more benefits such as improved battery life and increased usable capacity of the battery pack [6,7].
Currently, EV powertrains typically utilize a large battery pack with a conventional two-level voltage source inverter [8]. The battery pack typically contains low-voltage battery cells (e.g., 2-4 V) connected in parallel to achieve the required power rating. These cells are then connected in series, providing high-voltage (e.g., 300-1000 V) [9]. Because of differences in leakage currents and cells in homogeneity, individual cell voltage and state-of-charge (SOC) distribution among the cells are non-homogeneous. As a result, some cells discharge faster than other cells, thus limiting the total energy the pack can deliver. Cell balancers are employed as part of the battery management systems (BMS) to mitigate this problem [4]. However, individual cell control is desirable to maximize the energy delivered by the battery pack. This is achieved by integrating power electronics into the battery pack, thereby changing the battery interconnection pattern in response to the battery behavior and user demands. This provides enhanced fault tolerance, charge and temperature balancing, extended energy delivery, and easy integration of batteries of different ages and chemistry types [10].
Modular multilevel converters (MMCs) have gained popularity in the power distribution sector, especially in HV and MV applications where it has been proven to give several advantages, such as low THD, high modularity, and scalability [11,12]. Furthermore, over the last few years, battery-integrated MMCs (BI-MMCs) have gained popularity in battery energy storage systems (BESS) [13][14][15]. References [16,17] indicate a significant benefit in increasing the controllability of cells in terms of battery lifetime and battery utilization. A slight increase in the battery lifetime and utilization typically results in tremendous benefits [18]. BI-MMCs are, thus, particularly interesting for EV powertrains because of their high efficiency, greater cell-level control, and provide better battery fault isolation [19][20][21][22][23][24][25]. Low power (7.4 to 43 kW) AC and higher power (63 to 350 kW) DC charging capabilities for cascaded H-bridge topologies are presented in [26,27]. These articles report several advantages with BI-MMCs while charging, such as active balancing during charging, flexible DC charging voltage, and the potential elimination of a dedicated onboard charger for AC charging. Although the shown interesting effort in the literature, the mega-watt (MW) DC charging capabilities of BI-MMCs were not investigated.
The charging time for electric vehicles is significantly longer than the refueling time for conventional vehicles. To achieve a short charging time, efficient DC fast chargers capable of delivering high power are required. As a result, different standards for DC fastcharging systems are developed [28]. The combined charging system (CCS) is a standard for charging electric vehicles and can provide power up to 350 kW [29][30][31]. A key challenge in electrifying heavy-duty vehicles (HDVs) such as 40-ton commercial vehicles, is the need for high-energy storage capacity [32]. The anticipated size of the battery packs for HDVs is about 250 to 750 kWh [31]. To meet the changing needs of medium-and heavy-duty commercial vehicles' large energy storage system's short charging time intervals of 30 to 40 min, megawatt charging systems (MCS) are under development [33]. MCS chargers have an estimated charging power of 1 MW or greater with a maximum charging voltage and current of 1250 V and 3000 A, respectively [34].
The battery pack is connected directly to the fast charger in a conventional powertrain. However, the battery and the inverter are integrated into a BI-MMC, potentially increasing the DC fast charging capabilities because higher voltages are achieved during charging than during traction.

Contributions and Outline
The first contribution involves the derivation of the maximum DC charging power of five three-phase BI-MMCs, considering the same submodule semiconductor losses for a maximum tractive power of 400 kW for a 40-ton commercial vehicle. The second contribution is a comparative assessment of five three-phase BI-MMCs with 1, 6, and 12 cascaded cells per submodule, considering two different design criteria either based on the maximum motor voltage or maximum MCS DC charger voltage. The assessment includes the maximum DC charging power, voltage, and current, the total number of submodules, submodule losses, total semiconductor losses, and submodule temperature at maximum charging power.
The article outline follows: Section 2 presents an overview of the five BI-MMC topologies. Section 3 presents the two different design criteria to determine the total number of submodules either based on the maximum motor voltage or maximum MCS DC charger voltage. Section 4 describes the power loss calculations for the two different design criteria. The maximum DC charging current and power calculations are described in Section 5. Section 6 presents the calculations of the submodule case temperature at maximum charging power. Section 7 presents the comparative assessment of 5 3-phase BI-MMCs with 1-, 6-, and 12-cascaded cells per submodule. Finally, discussions and conclusions are presented in Sections 8 and 9, respectively. Figure 1 presents the schematic of BI-MMC topologies. They consist of either one or two arms per phase (N arms ), and each arm is made up of several cascaded stages of power converters and is commonly referred to as submodules (SM) (N sm,arm SMs per arm). In the figure, the terminals 'P' and 'N' are used as the positive and negative terminals for DC charging, and the circuit breaker, CB n , in the open position ensures that the electric machine (EM) is disconnected from the BI-MMC during DC charging. Figure 1a,b present the double-star half-bridge (DSHB) and double-star full-bridge (DSFB) topologies, respectively, and Figure 1c,d gives the single-star half-bridge and single-star full-bridge topologies, respectively. In single-star topologies, in addition to CB n open, it is also necessary to ensure that CB n is open for DC charging. In double-star BI-MMCs, arm inductors are used to reduce the amplitude of circulating currents. Still, in single-star topologies, there is no path for the circulating current during traction. Therefore, arm inductors are not required for such a design. Figure 1e illustrates the single-delta topology. In this topology, in addition to CB n open, CB p and CB n should be in position 'Y' for DC charging. A detailed description of all the topologies is presented in [35]. The SMs are bidirectional by design due to the anti-parallel diode, and as a result, the AC side current can be controlled in both directions.  Figure 2a shows the schematic of a typical megawatt (MW) DC charger. A medium voltage (MV) three-phase electrical grid is connected to an active rectifier (AC/DC) and followed by a stage of DC-to-DC converter (typically, a dual-active bridge) [37][38][39]. The output of the DC-to-DC converter stage is connected to the 'P' and 'N' terminals of the BI-MMC through the MCS connector for DC charging [40]. Figure 2b shows the constant current (CC) and constant current constant voltage (CC-CV) charging process. A detailed description of the charging process is described in [4]. The DC charger controls the current through the BI-MMC during DC charging. The figure clearly shows that the charging power varies throughout the entire charging cycle. However, the maximum DC charging power (P c max ), such that the semiconductor losses per submodule during the traction and charging are equal, is presented in Section 5.  Figure 3a,b present the half-bridge (HB) and full-bridge (FB) submodules (SM), respectively. The figure shows that the DC side of an SM contains a battery pack, configured with N s(cells) series and N p(cells) parallel cells, and DC-link capacitors modeled as an RLC circuit with an equivalent series resistance (ESR), equivalent capacitance, (C) and parasitic inductance between the capacitors and the high-side switches (ESL). N s(cells) defines the desired SM DC voltage (U s ), and the required battery capacity per submodule defines N p(cells) . An SM consists of 2 or 4 switches (for HB-and FB-SMs, respectively), and each switch is made of N p(mos) parallel MOSFETs. The HB-SM, shown in Figure 3a, has two complementary switches S 1 and S 2 . When S 1 is 'off' (S 2 is 'on'), u sm is equal to 0 V, referred to as the bypass state. Alternatively, when S 1 is 'on' (S 2 is 'off'), the SM output voltage u sm is equal to the DC side voltage U s ; this is referred to as the insertion state. The FB-SM, shown in Figure 3b, has four switches, S 1 , S 2 , and S 3 , S 4 , where S 1 , S 2 , and S 3 , S 4 are complementary switches. When either S 1 , S 3 , or S 2 , S 4 is 'on', u sm is 0 V (bypass states). When S 1 and S 4 are 'on' (S 2 and S 3 are 'off'), then u sm is equal to U s (insertion state). Similarly, when S 2 and S 3 are 'on' (S 1 and S 4 are 'off'), then u sm is equal to −U s (insertion state). The RMS output voltage of the HB-SM (U sm(hb) ) and FB-SM (U sm(fb) ) are:

Topology Review
where M max is the maximum modulation index.

Total Number of Submodules
This section presents the two different methods of determining the total number of submodules for continuous DC charging: CDC-T gives the total number of submodules determined by the traction voltage, and CDC-C presents the total number of submodules by the maximum DC charger voltage.

CDC-T: Total Number of Submodules Determined by the Traction Voltage
During traction, the SMs are operated as DC-AC inverters and the total number of submodules (N t sm ) required to achieve an output RMS phase-to-neutral voltage of U ph is calculated using the following relation: where N ph is the number of phases.

CDC-C: Total Number of Submodules Determined by Maximum DC Charger Voltage
During DC charging, the SMs are used as DC-DC buck converters and the BI-MMC DC-terminal voltage (U pn ) is given as follows: One way to maximize the DC charging power is to ensure that U pn is equal to the maximum voltage of the DC charger (U max dc(c) ) and the total number of submodules required to ensure U pn = U max dc(c) (N c sm ) is calculated as follows: If a BI-MMC topology has N c sm SMs, resulting in a phase-to-neutral RMS AC output voltage of U ph , and N c sm < N t sm , then U ph < U ph . As a result, the BI-MMC cannot reach the maximum traction voltage, reducing traction power. Therefore, the total number of submodules (N c sm ) required to ensure U pn > U max dc(c) while also ensuring a maximum AC output voltage of U ph is determined as follows: It is important to mention that when the total number of submodules (N sm ) is altered, the total number of parallel cells per SM will also change. This is because the total energy stored in the batteries is the same. As a result, during charging, the change in the total number of SM batteries in series compensates for the change in the number of parallel cells per SM. Therefore, the battery losses in both CDC-T and CDC-C are identical.

Power Loss Calculations
This section presents the power loss calculations during traction and DC charging.

Power Loss during Traction
The maximum arm current during traction (I t arm ) is calculated as follows: where cos(φ) is the traction motor power factor and P t max is the maximum tractive power. The conduction and switching losses of a switch (P l(t) c,sw and P l(t) s,sw , respectively) are determined as follows: where R ds(on) is the MOSFET on-state resistance, N p(mos) is the number of parallel MOSFETs per switch, t sw(tran) is the combined switching transient time, corresponding to the sum of current rise and voltage fall time at turn-on and the voltage rise and current fall time at a turn-off, i.e., t sw(tran) = t ri + t fi + t rv + t fv , and f t sw is the MOSFET switching frequency. N p(mos) is calculated, considered a maximum case temperature, t sw(tran) is determined considering a maximum drain-to-source voltage ripple, and f t sw is selected such that the DC-current harmonic components are bypassed by the DC-link capacitors [36].
The total losses in a submodule during traction (P l(t) sm ) are given as follows: where N sw represents the number of switches per SM. It is important to mention that the SM circuit board contains the switches and the DC-link capacitors. As a result, the total losses per submodule include both P l(t) sm and the capacitor losses per SM. However, due to the design choice of the DC-link capacitors, the capacitor losses per SM are far lower than P l(t) sm [36]. Therefore, the total losses per submodule are equal to P l(t) sm . The total semiconductor losses during traction (P l(t) sc ) is given as follows: where N sm(tot) represents the total number of submodules presented in either CDC-A or -B.

Power Loss during DC Charging
As mentioned previously, during DC charging, the SMs of the BI-MMCs are operated as DC-DC buck converters, and the SM duty cycles (D c ) are equal to 1, i.e., SMs are always inserted. However, for the topologies where U pn > U max dc(c) , then D c = U pn /U max dc(c) . It is worth mentioning that D c among SMs can be different and is determined by a BMS active balancing algorithm to ensure an even SOC distribution among the SM cells. Furthermore, the DC charging current magnitude is determined by the charger, and it is assumed that there exists communication between the vehicle and the DC charger to control the charging current.
The distribution of losses within the SM depends on D c , i.e., during the insertion period; S 1 in HB-SM, and S 1 and S 3 in the FB-SM, bare the conduction losses; and during the bypass period, the other switches bare the conduction losses. The DC charging conduction losses per switch during the insertion-and bypass-states (P l(c) c,sw(ins) and P l(c) c,sw(byp) , respectively) are given as follows: where I c arm is the DC arm current during charging and R ds(on) is the MOSFET on-state resistance. In the continuous DC charging (CDC) case, the MOSFET switching frequency is equivalent to the rate of active balancing determined by the BMS, and the switching losses are neglected. The total losses in a submodule during DC charging, P c sm , is, thus, given as follows: The total semiconductor losses during DC charging (P l(c) sc ) is given as follows:

Maximum DC Charging Power Calculations
In a conventional powertrain, during DC charging, the positive and negative terminals of the battery pack are connected to the DC charger, and the losses incurred are only in the battery. However, in a BI-MMC-based powertrain, the battery and the inverter are integrated, and as a result, the losses during DC charging are increased. Therefore, to restrict the losses and cooling requirements per submodule, the submodule losses per charging and traction are considered to be equal, i.e., The maximum DC charging arm current to ensure that the total semiconductor charging and traction losses are equal (I c,max arm ) can, thus, be calculated as follows: where P l(t)max sm is the SM losses at P t max and R max ds(on) is the MOSFET on-state resistance at maximum junction temperature.
The maximum DC charging power is calculated using the following:

Submodule Case Temperature
The SM case temperature (T c ) is calculated using the following relation: where R θca is the case of ambient thermal resistance (presented in Appendix A), P l sm is the submodule losses, and T a is the ambient temperature.

Comparative Assessment
The BI-MMC design parameters are presented in Table 1. The converter design considers a maximum tractive power of 400 kW and a 20-pole traction motor with a nominal speed of 1000 rpm. A maximum modulation index (M max ) of 0.85 was considered, allowing for 15% redundant submodules; 24 Ah Samsung NMC Li-ion cells were considered with nominal and minimum cell voltages of 3.7 V and 3.45 V, respectively. The minimum cell voltage selected from the open circuit voltage vs. state-of-charge curve corresponds to 65% depth-of-discharge. The total energy stored in the batteries of a 40-ton commercial vehicle is assumed to be one MWh. Appendix A shows the number of parallel MOSFETs per switch, the maximum drain-to-source resistances, the MOSFET switching frequencies, and the case of ambient thermal resistance, determined using the procedure shown in [36]. The two different DC charging scenarios for the comparative assessment are as follows: CDC-T Continuous DC charging with the total number of submodules determined by the traction voltage.
CDC-C Continuous DC charging with the total number of submodules determined by the maximum DC charger voltage. Figure 4 shows the total number of submodules determined by the traction voltage (N t sm ) and maximum DC charger voltage (N c sm ) for all BI-MMC topologies with 1, 6, and 12 N s(cells) .

N s(cells) Comparison
The figure clearly shows that the total number of submodules (both N t sm and N c sm ) decreases with an increase in N s(cells) for a given topology. This is because as N s(cells) increase, the DC-side SM voltage (U s ) increases, thus increasing the SM output RMS voltage (U sm ), and this, in turn, reduces the total number of submodules required to have U ph (U ph is the same for all topologies and N s(cells) ).

Topology Comparison
From the figure, it is clear that DSHB has a 50% lower N t sm than DSFB. This is because U sm for DSFB is two times more than that of DSHB because of the bi-polar nature of FB-SMs. For the same reason, SSFB has 50% lower N t sm than SSHB, and N t sm for DSFB and SSHB are identical for a given N s(cells) . SDFB has √ 3 times higher N t sm than that of SSFB because, in the SDFB, U v and U ph are equal. N c sm for all topologies is identical by the definition of CDC-C. However, in the DSHB topology, N t sm is greater than N c sm since U pn is greater than U max dc(c) . Consequently, the maximum AC traction phase-to-neutral voltage for DSHB with N c sm submodules is lower than U ph , thus resulting in lower tractive power. Therefore, in CDC-C, DSHB N c sm and N t sm are the same, and during DC charging, the D c of DSHB is equal to U max dc(c) /U pn . N c sm for all other topologies is the same as N c sm . Figure 5 presents the submodule semiconductor losses (P l sm ) for the two different DC charging cases, namely, CDC-T and CDC-C at a maximum charging power of P c max for all BI-MMC topologies with 1, 6, and 12 N s(cells) . P l sm for both the DC charging scenarios is identical, and this is, by definition, i.e., ensuring that the submodule losses during charging and traction are identical.

N s(cells) Comparison
It is clear that P l sm increases with an increase in N s(cells) for a given topology. This is because of the increase in the conduction losses due to the high R ds(on) of the higher voltage class MOSFETs employed at higher N s(cells) .

Topology Comparison
The DSFB has about two times more P l sm than the DSHB because the DSFB has two times more N sw than the DSHB for a given N s(cells) . For the same reason, P l sm for SSFB is two times more than in SSHB. P l sm for SSHB is almost four times as in DSHB because SSHB has two times more I arm than DSHB. For the same reason, SSFB has three times more P l sm than DSFB. For 12 N s(cells) , P l sm of SSHB is a factor of 3 higher than DSHB because SSHB has slightly higher N p(mos) than DSHB, and a detailed calculation for N p(mos) is described in [36]. For the same reason, SSFB has three times more P l sm than DSFB at 12 N s(cells) . P l sm for SSFB is about three times higher than in SDFB because I arm for SSFB is √ 3 times greater than in SDFB.
The SSFB has the highest P l sm compared with the other topologies, but the thermal resistance of the SSFB submodule is relatively low (as shown in Table A1). As a result, the case temperature is kept under a maximum allowable case temperature (T max c ) of 80 • C. (as shown in Section 7.6). Since P l sm for FB-SM is two times that of the HB-SM, the cost of the cooling system for the FB-SMs is higher than HB-SMs. This is reflected in the case-to-ambient thermal resistance in Table A1.

N s(cells) Comparison
For a given topology, the total semiconductor losses, P l sc (both P l(t) sc and P l(c) sc ), are the lowest at 6 N s(cells) . This is because as N s(cells) increases, the MOSFET R ds(on) increases but not in proportion to the total number of submodules (both N t sm and N c sm ) decreases. sc for SSHB is about two times more than DSHB. This is because the arm current during traction (I t arm ) for SSHB is two times more than DSHB, and N t sm for DSHB is half as much as DSHB. For the same reason, P l(t) sc for SSFB is two times more than DSFB. The SSFB has about √ 3 times higher P l(t) sc than SDFB. This is because the I t arm is √ 3 times higher and N t sm is about a factor √ 3 lower in SSFB than SDFB. P l(t) sc for DSHB and DSFB are almost identical. This is because the N t sm for DSFB is half of DSHB, but DSFB has twice the number of switches as DSHB. For the same reason, P l(t) sc for SSFB and SSHB are similar. SSFB has about four times higher P l(c) sc than DSFB. This is because the arm's current during charging (I c arm ) is twice as much for SSFB than DSFB, and both topologies have identical N c sm . SSFB has about two times the P l(c) sc as SSHB because P l sm for SSFB is around twice as much as SSHB, and both topologies have identical N c sm . P l(c) sc for DSFB is about 30% more than DSHB because DSFB has twice the P l sm as DSHB, but N c sm for DSHB is higher than in DSFB.

Topology Comparison
Although the SSFB CDC-C has about three times higher P l(c) sc than the SSFB CDC-T, the SSFB CDC-C SM case temperature is lower than 80 • C. However, the high P l(c) sc of SSFB CDC-C significantly increases the cost of cooling systems. Figure 7 shows the maximum BI-MMC DC link voltage and maximum DC charging current considering the two different scenarios, CDC-T and CDC-C, for all topologies with 1, 6, and 12 N s(cells) . Figure 7a gives the maximum BI-MMC DC link voltage (U pn ) and maximum MCS DC charger voltage (U max dc(c) ). The figure shows that U max dc(c) is independent of N s(cells) for a given topology. This is because in CDC-T, the N t sm is designed such that all topologies have the same U ph , irrespective of N s(cells) , and in CDC-C, N c sm is determined such that U pn is equal to U max dc(c) , irrespective of N s(cells) . U pn for DSHB in CDC-T and CDC-C are identical because both N c sm and N t sm for DSHB are equal. In CDC-T, the distribution of U pn among topologies follows N t sm for a given N s(cells) . However, in CDC-C, by definition, U pn and U max dc(c) are equal for all topologies except DSHB. U pn for DSHB is higher than U max dc (c) because N c sm is greater than N c sm .  Figure 7b shows the maximum DC charging current (I c max ), and it is clear that as N s(cells) increases, I c max increases marginally for a given topology. This is because f t sw increases with the increase in N s(cells) . I c max for CDC-T and CDC-C are similar for a given topology and N s(cells) , because P l sm for CDC-T and CDC-C are similar (by definition). I c max for DSHB and DSFB are similar even though P l sm for DSFB is two times more than DSHB. This is because FB-SMs have twice the N sw as HB-SMs, for a given N s(cells) . For the same reason, I c max for SSHB and SSFB are similar for 1 N s(cells) . At 6 and 12 N s(cells) , however, I c max SSFB is slightly lower than SSHB because these topologies have different N p(mos) . I c max for SSFB is about two times more than in DSFB for a given N s(cells) . This is because P l sm for SSFB is about four times more than in DSFB. For the same reason, I c max for SSHB is about twice as DSFB. DSFB and SDFB have similar I c max because these topologies have similar P l sm .

N s(cells) Comparison
The figure shows that for a given topology, as N s(cells) increases, P c max increases marginally. This is because I c max increases marginally with an increase in N s(cells) .

Topology Comparison
The figure shows that P c max for CDC-C is higher than in CDC-T for all topologies except DSHB. This is because U pn in CDC-C is much greater than in CDC-T for all topologies except DSHB for a given N s(cells) . In CDC-C, P c max for all topologies follows I c max for a given N s(cells) because U pn for all the topologies is the same.
In CDC-T, P c max for SSFB and DSFB are similar for a given N s(cells) . This is because U pn for SSFB is half of that in DSFB, but I c max for SSFB is two times more than in DSFB. For the same reason, P c max for SSHB is similar to that in DSHB. DSFB and SDFB have similar P c max because these topologies have similar U pn and I c max , irrespective of the DC charging scenario (CDC-T or CDC-C).
P c max for DSHB in CDC-T and CDC-C are identical because N t sm and N c sm are equal for a given N s(cells) . P c max for SSFB in CDC-C is about three times greater than in CDC-T because N c sm is about three times higher than N t sm . For the same reason, DSFB, SSHB, and SDFB also have higher P c max in CDC-C than in CDC-T and is proportional to the difference between N c sm and N t sm . All the BI-MMC topologies have a maximum DC charging power between 800 kW to 3.3 MW. This corresponds to a maximum charging C-rate between 1 C to 3 C assuming a 1 MWh battery system. 7.6. Submodule Temperature N p(mos) is selected such that T c for all topologies is below 80 • C considering an ambient temperature of 40 • C, and is presented in Table A1. A minimum limit for N p(mos) of 4 is chosen to reduce the total losses. Figure 9 shows the T c for all topologies with 1, 6, and 12 N s(cells) at a maximum charging power of P c max .

N s(cells) Comparison
As N s(cells) increases, T c also increases. This is because the MOSFET on-state resistance also increases with an increase in N s(cells) (Table A1), thereby increasing P l sm . Figure 9. The submodule temperature for all topologies with 1, 6, and 12 N s(cells) at a maximum charging power of P c max .

Topologies Comparison
The double-star topologies have a lower T c than for a given N s(cells) . This is because, in the double-star topologies, the RMS output current is split equally between the two arms resulting in lower losses. The SDFB is slightly more than in DSFB because P l sm for SDFB is slightly more than in DSFB are similar. The T c for DSFB and DSHB are similar. This is because P l sm for DSFB is twice as in DSHB, but DSFB has 50% lower R θca than DSHB (see Table A1) since DSFB has twice as many switches as DSHB.

Discussion
The DC charging power can be increased for both CDC-T and CDC-C scenarios by increasing the maximum SM temperature above 80 • C during charging. However, this increases the total semiconductor losses.
The total submodule losses include all the switches in the SM. Therefore, during DC charging, the distribution of power losses among the switches within the SM is not even and is dependent on the duty cycle of the submodule.
The underlying assumption for the analysis is that the total semiconductor losses during charging and traction are identical. However, the vehicle is stationary during charging, which affects the cooling. Therefore, to ensure that total semiconductor losses during charging and traction are the same, possibly additional cooling requirements are required. If all the topologies had the same number of parallel MOSFETs, then submodule conduction losses during traction for the SSFB and SSHB topology would increase. This also increases the submodule conduction losses during DC charging. As a result, the total DC charging power will also increase, and so will the case temperature.
Extending the battery losses during traction from [36] to DC charging with a power of 1 MW and a DC-link voltage of 800 V, the battery losses are 4.5 kW. Furthermore, assuming that the total energy stored in the battery pack of the two-level inverter-based powertrain and the batteries in BI-MMCs is identical, the battery losses during charging for both powertrains are equal. However, the total losses during charging in a BI-MMC include the semiconductor losses much greater than the two-level inverter. Therefore, the total losses during charging in BI-MMCs are much higher than in a two-level inverter-based powertrain.

Conclusions
Two different DC charging scenarios for five different three-phase BI-MMC topologies with 1, 6, and 12 cascaded cells per submodule designed for a maximum tractive power of 400 kW for a 40-ton commercial vehicle were investigated. The two DC charging scenarios are continuous DC charging with the total number of submodules determined by the traction voltage (CDC-T) and continuous DC charging with the total number of submodules determined by the maximum DC charger voltage (CDC-C). A topology's maximum charging power (P c max ) is defined as the power at which the total semiconductor losses during traction and DC charging are equal.
Most BI-MMCs with the total number of submodules determined by the maximum DC charger voltage (CDC-C) have higher P c max than BI-MMCs with the total number of submodules determined by the traction voltage (CDC-T). In particular, SSFB P c max is about three times as high in CDC-C than in CDC-T. However, the total semiconductor losses (P l sc ) are significantly higher in CDC-C than in CDC-T. As a result, the total power converter efficiency reduces, potentially reducing the advantages of BI-MMCs, especially during traction. For the DSHB, P c max in both CDC-C and CDC-T are identical. Therefore, P c max can be further increased at the cost of increased submodule losses.
About 20% of BI-MMC topologies with 6 and 12 N s(cells) have about 2.5 to 3.3 MW of P c max , about 30% of all the topologies with 1, 6, and 12 N s(cells) have P c max of about 1.5 to 2.5 MW and all the other topologies have P c max of about 800 kW to 1.5 MW. All the BI-MMC topologies can achieve 1 h or shorter charging time, corresponding to 1 C or higher charging current. Data Availability Statement: Data supporting reported results can be found at https://gitlab.liu.se/ BI-MMC_public/dc-charging-of-bi-mmcs/continuous-dc-charging (accessed on 23 January 2023).

Conflicts of Interest:
The authors declare no conflict of interest. Table A1 presents the number of parallel MOSFETs per switch (N p(mos) ) for all topologies at different N s(cells) , such that the case temperature does not exceed 80 • C calculated using the relation in [36]. Most topologies have four N p(mos) because the minimum number of parallel MOSFETs is limited to 4. The table also presents the maximum on-state resistance (R max ds(on) ) for all topologies at different N s(cells) , and for a given N s(cells) , all topologies employ the same MOSFET. Furthermore, the table presents the MOSFET switching frequency during traction (f t sw ) for all topologies at different N s(cells) using the optimization principle presented in [36]. Finally, the table shows the SM case of ambient thermal resistance.