Temperature Dependence of Germanium Arsenide Field-Effect Transistors Electrical Properties

: In this work, we report the fabrication of germanium arsenide ( 𝐺𝑒𝐴𝑠 ) field-effect transistors with ultrathin channel and their electrical characterizations in a wide temperature range, from 20 to 280 K . We show that at lower temperatures, the electrical conduction of the 𝐺𝑒𝐴𝑠 channel is dominated by the 3D variable range hopping but becomes band-type at higher temperatures, after the formation of a highly conducting two-dimensional (2D) channel. The presence of this 2D channel, limited to a few interfacial 𝐺𝑒𝐴𝑠 layers, is confirmed by the observation of an unexpected peak in the temperature dependence of the carrier density per area at ∼ 75 K . Such a feature is explained considering a model based on a temperature-dependent channel thickness, corroborated by numerical simulations, that show excellent agreement with the experimental data.


Introduction
Recent interest in research on two-dimensional (2D) materials has led to the exploration of new classes of layered materials beyond graphene and transition metal dichalcogenides. Among these, the binary compounds of groups IV and V are assuming considerable importance since theoretical studies have proved their crystalline layered structures with orthorhombic ( 2 for and for and ) or monoclinic ( 2/ for , , and ) symmetries [1][2][3][4]. Particularly, has been considered for possible optoelectronic applications and for its high in-plane anisotropy [5,6]. Figure 1a shows the crystal layered structure, in which each atom is bonded to one atom and three atoms forming distorted @ octahedra [7]. Similar to TMDs, the bandgap changes according to the number of layers. Numerical calculations and optical bandgap measurements, indicate that germanium arsenide indirect bandgap ranges from ~0.57 − 0.65 eV for the bulk [8,9] to 1.6 − 2.1 eV for the monolayer [10,11].
In this work, we report the fabrication of 12 nm thick back-gate field effect transistors through mechanical exfoliation and their electrical characterization in a fourprobe configuration and in a range of temperatures from 20 to 280 K. We find that at low temperature, the conduction is dominated by 3D variable range hopping but becomes band-type at higher temperatures. This change in the conduction mechanism is due to the formation of a highly conducting 2D channel close to the gate, confirmed by the observation of an unexpected peak in the temperature dependence of the carrier density per area

Results and Discussion
Figure 1b shows an optical image of a 12 nm thick flakes covered with eight 5 nm Ni/40 nm Au electrodes. Ultrathin flakes were exfoliated from bulk single crystals using a standard mechanical exfoliation method by adhesive tape. The flakes were transferred onto degenerately doped p-type silicon substrates, covered by 300 nm-thick SiO . Electron-beam lithography were performed on selected flakes to obtain a Hall bar structure. Finally, electron-beam evaporation was used to deposit the metal electrodes [12].
Contacts 1 to 4 were used to perform a standard four probe electrical characterization in which the current ( ) is measured between the outers contact (1 and 4) and the voltage drop ( ) is measured between the inner contacts (2 and 3). Figure 1c shows the output characteristic, i.e., the drain-source current as a function of the voltage drop between two inner contacts with the gate-source voltage ( ) as control parameter. It shows a linear behaviour that is not influenced by the gate potential which only changes the total conductance of the device. Moreover, it testifies the formation of ohmic contacts due to the alignment between the Ni Fermi level (work function 5.15 eV) below the valence band of . Figure 1d reports the transfer characteristic, i.e., the − curve ( = / is the channel conductance) measured over a loop of the gate voltage. It shows a typical p-type behaviour mainly due to the presence of intrinsic defects such as vacancies, the interaction with the SiO gate dielectric and the oxidation of the topmost layers of the flake that would act as p-type dopants in the material and provide intragap states [1,2].  Figure 2b reports the transfer characteristic of the device in which we defined the FET channel conductance as: where is the field-effect mobility; = • = 1.15 • 10 F/cm is the capacitance per unit area of the gate dielectric, where = 8.85 • 10 F/cm , = 3.9, and = 300 nm are the vacuum permittivity, the SiO relative permittivity, and thickness, respectively; is the threshold voltage; and 1 is a dimensionless parameter, which accounts for a possible -dependence of the mobility [13]. in which we can consider = 1. From the fit, we can extrapolate the mobility at each temperature as shown in the inset of Figure 2b. We find a quadratic dependence, ~ , pointing towards a mobility dominated by Coulomb scattering due to ionized impurities [14]. A deeper analysis of the versus graph, shown in the inset of Figure 2a reveals that the electrical conduction follows two different mechanisms at low and high temperature, respectively. Indeed, we notice that the best fitting of the experimental data at low temperature is obtained using the variable range hopping conduction (VRH). According to VRH theory, the relation between and can be expressed as [15]: where depends on the square root of , is a constant, and n indicates the dimensionality of the system [16].  The linearity demonstrates that the conduction is bulk type (3D) for < 80 K, i.e., it occurs through the entire flake constituted of ∼ 20 atomic layers. Figure 2d shows the trend for > 180 K. We observe an exponential increase with the inverse of temperature that indicates that the thermal excitation of carriers (holes) to the valence band leads to a band conduction regime, ∝ ( / ), as expected after the formation of a highly conductive 2D channel in the transitor. In order to try to explain this strange passage from a bulk to a 2D conduction, we calculate the carrier density per unit area (in cm ) as a function of the temperature. Indeed, having computed ( ) and ( ) at each of the considered temperatures, can be obtained from the relation: where is the electron charge. Figure 3a shows that ( ) exhibits an unexpected and pronounced peak at ~75 K, followed by a smoother increase for > 150 K. In a doped three-dimensional semiconductor, the carrier density would show a different temperature behavior [14]. Specifically, an initial rapid increase due to the ionization of dopant atoms by thermal energy (freeze-out region, up to ~150 K for medium-doped ) would be followed by a plateau over a wide temperature range when complete ionization is reached (extrinsic region, ~150 − 500 K for medium-doped ), and would finally evolve in an exponential increase at higher temperatures due to intrinsic generation of electron-hole pairs (intrinsic region). To explain both the reported anomalous behavior and the modification from a bulk to a 2D conduction due to increasing temperature, we propose a model that considers a temperature-dependent thickness of the channel in which most of the conduction occurs. Indeed, we notice that the 2D carrier density per unit area can be expressed as ( ) = ( ) ( ) where is the carrier density per unit volume in cm and is the thickness of the conducting channel. The current in the flake is due to carriers injected from the Ni contacts that overcome a potential barrier, , between the contacts and the channel region. Therefore, ( ) in the region between the inner contacts can be expressed as [17]: where is the Boltzmann constant and is a proportionality constant that can be considered as a fitting parameter of the model. At low temperature (< 80 K), there is a limited amount of carriers as well as high intralayer resistance that suppresses the vertical transport with respect to the in-plane one [18,19]. In this regime, conduction occurs mainly through the layers in closer contact with the metal leads (especially the topmost ones) and the gate electric field controls the entire flake thickness. With raising temperature, defect ionization, and injection from the contacts increase. The new available carriers, pushed by the applied gate voltage and the favorable vertical band bending toward the interface with the gate dielectric, form a 2D channel, which becomes more and more conductive with the rising temperature. This channel now screens the gate field, and any variation of the gate voltage affects mainly the bottommost layers of the flake. In this regime, the conduction is dominated by a few atomic layers closer to the gate, i.e., the effective conducting thickness ( ) controlled by the gate is reduced.
To test the model, with an appropriate choice of ( ) and ( ), we computed ( ) obtaining an excellent agreement with the experimental data, as shown in Figure 3a, where we display ( ) at = −20 V. The carrier density per volume ( ), given by Equation (4), is shown by the red line of Figure 3b, with obtained as fitting parameter. For ( ), we used a step-like function, ( ) = /(1 ( * ) ) , represented by the black curve shown in Figure 3b, in which is the initial thickness of the whole flake, i.e., ~ 12 nm, is the thickness of a single layer (0.6 nm), and is a fitting parameter used to simulate a smooth transition in the 70 − 150 K range. Finally, the model is further corroborated by the estimation of the Debye screening length = , that gives the length over which the electric field strength drops by a factor 1/ (here = 8 is the dielectric constant at room temperature of the material [20]). From our data, we estimate ~ 0.4 nm at room temperature, confirming that the gate electric field is substantially screened in the layer closer to the gate.

Conclusions
We fabricated back-gate field effect transistors with ultrathin films and investigated their electrical properties over a wide temperature range, from 20 to 280 K. We found a p-type behaviour with temperature increasing conductivity. We find that the con-duction is dominated by the 3D variable range hopping at lower temperatures but becomes band-type at higher temperatures, when a highly conducting 2D channel is formed. We observed that the carrier density in flakes depends on temperature with a pronounced and broad peak around 75 K. We proposed a model based on a temperaturedependent channel thickness to explain such an anomaly that shows an excellent agreement with the experimental data.