Comparative Analysis of Design Parameters for Modern Radio Frequency Complementary Metal Oxide Semiconductor Ultra-Low Power Ampliﬁer Architecture Trends

: This research presents a comparative analysis of design parameters in modern power ampliﬁer (PA) architecture trends in various CMOS nano-meter technologies. The design parameters include the signal gain, linearity, output power, and output power back-off. The resultant parameters are compared using a table, and various parameters of various designs are visually shown for comparison. These comparative ﬁndings will provide any designer with practical information to choose the best CMOS PA design for a speciﬁc application. The most important RF CMOS PA integrated implementations are addressed in the conclusion section


Introduction
Currently, a faster, more effective, linear, and power-efficient communication system with a higher frequency is pursued due to the enormous demand for and rapid development of wireless transmission, as well as the needs for advanced short-range low-power Wireless Personal Area Network (WPAN) and long-range low-power Wireless Local Area Network (WLAN) systems [1].Therefore, it is crucial to improve the PA's design in communication systems.In order to increase efficiency, modern power amplifiers should be built with a large output back-off (OBO) and enhanced efficiency.Because of the small chip size, CMOS technology enables operation at an ultra-low power supply, which reduces power dissipation and lowers manufacturing costs [2]. Figure 1 Represents the IEEE standards for ULP architectures.

Introduction
Currently, a faster, more effective, linear, and power-efficient communication system with a higher frequency is pursued due to the enormous demand for and rapid development of wireless transmission, as well as the needs for advanced short-range low-power Wireless Personal Area Network (WPAN) and long-range low-power Wireless Local Area Network (WLAN) systems [1].Therefore, it is crucial to improve the PA's design in communication systems.In order to increase efficiency, modern power amplifiers should be built with a large output back-off (OBO) and enhanced efficiency.Because of the small chip size, CMOS technology enables operation at an ultra-low power supply, which reduces power dissipation and lowers manufacturing costs [2]. Figure 1 Represents the IEEE standards for ULP architectures.

Comparative Analysis of Modern RF CMOS PA Design Parameters
To assess the overall performance, a figure-of-merit (FoM) is used, which takes into account the most significant performances and characteristics in a methodology as follows: where P dBm is the saturated output power in dBm, S21 is the power gain in dB, S11 is the insertion loss in dB, PAE is the power-added efficiency in percentage, f GHz shows the channel frequency in GHz, and P dc is the dc power consumption in mW. Figure 2 illustrates the PAE, output power, and FoM for recent PA architecture.

Comparative Analysis of Modern RF CMOS PA Design Parameters
To assess the overall performance, a figure-of-merit (FoM) is used, which takes into account the most significant performances and characteristics in a methodology as follows: where PdBm is the saturated output power in dBm, S21 is the power gain in dB, S11 is the insertion loss in dB, PAE is the power-added efficiency in percentage, fGHz shows the channel frequency in GHz, and Pdc is the dc power consumption in mW. Figure 2 illustrates the PAE, output power, and FoM for recent PA architecture.Table 1 shows the performance metrics for various state-of-the-art modern CMOS RF PAs at a glance.The depicted results were simulated to observe the discrete comparison of the PAE with the input power (dBm) and modern RF CMOS design architectures.

Power-Added Efficiency
The post-layout simulation results show that cascodes class-E [3] and class-D [7] have the highest PAEs for short-range WPAN and long-range WLAN networks, respectively.The analysis was performed with reference to the input power (in dBm).Concerning BLE RF PAs, Integrated Analogue Pre-Distorters (APDs) [4] and class-F designs with reconfigurable off-chip inter-stage matching networks [10] have a low PAE compared to class-E [3] and class-D [6] design architectures.

Saturated Power in dBm
Taking into account the WPAN BLE standards, Integrated Analogue Pre-Distorters (APDs) [4] and class-F designs with reconfigurable off-chip inter-stage matching network architectures [5] produce more output power because of the BLE class-1 ISM band.The least output power is produced by the CMOS power amplifier based on transformer coupling and synthetic dielectric differential transmission.Due to class-2 BLE ISM band designs, the remaining devices offer acceptable output powers between 1 and 4 dBm.Due to the sub-1 GHz band, the IEEE 802.11 ah WiFi HaLow offers a long range of up to 1 km, as observed in [7][8][9][10] PA design architectures.

ULP Consumption
The DPA with fixed inter-stage capacitances [6] and class-F designs with feedback using ET supply bias [10] are ultra-low power (ULP) designs compared to the rest of the proposed architectures.The MOS architectures in both designs are biased in the subthreshold region.The MOS biasing operation in moderate and weak inversion regions is a noticeable justification for ULP.

Figure 1 .
Figure 1.IEEE standards for low-power communications.

Figure 1 .
Figure 1.IEEE standards for low-power communications.

Figure 2 .
Figure 2. (a) PAE of individual design.(b) Discrete and statistical comparison of the PAE with the input power (dBm) and modern RF CMOS design architectures.(c) Comparison of saturated output power and (d) the analyzed figure-of-merit.

Figure 2 .
Figure 2. (a) PAE of individual design.(b) Discrete and statistical comparison of the PAE with the input power (dBm) and modern RF CMOS design architectures.(c) Comparison of saturated output power and (d) the analyzed figure-of-merit.

Table 1 .
Comparison of state-of-the-art CMOS RF PA ULP architecture in recent years.