Design of an LDMOS Transistor Based on the 1 m CMOS Process for High/Low Power Applications "2279

In this paper we investigate the performance of an integrated n-type laterally-diffused metal oxide semiconductor (nLDMOS) transistor, using 2D TCAD simulations. This work is based on the 1 μm CMOS technology node at CDTAs clean room. The nLDMOS process uses the necessary steps extracted from logic-integrated circuits fabrication flow, which yields to local oxidation of silicon (LOCOS), single reduced surface field (RESURF)-based nLDMOS, without needing any additional masks or steps. The resulting device has a 22 V breakdown voltage (BV) and 272 mm2 mΩ specific on-state resistance (RON). The analysis determined that the proposed device could be implemented in RF power amplifiers for wireless communications or automotive circuits as primary domains, provided experimental calibrations.


Introduction
In many power, RF, and microwave electronic circuits, the laterally-diffused metal oxide semiconductor (LDMOS) transistor is widely adopted, which is due to its low cost and excellent performance [1,2]. LDMOS transistor design is also a mature, well-optimized practice [3]. The influence of each process step, region, and operating regime is well understood, especially when it is fabricated in complementary MOS (CMOS) technology [4]. Additionally, the basic LDMOS structure allows easy integration with the logic, low power circuits, opening more application possibilities, even with old technology nodes [5]. A good LDMOS for power/analog applications should have a relatively high breakdown voltage (BV), low on-state resistance (R ON ), and a large safe operating area (SOA). It also needs to take into account the characteristics of various parasitic BJTs and their influence on self-heating, the capacitors' impact on the linearity and resistors' temperature dependence, and how it affects the frequency response [6,7].
Based on the available equipment at CDTAs clean room, which uses the 1 µm CMOS technology node [8,9], we propose an nLDMOS transistor by TCAD simulations. The latter is designed to be integrated with the rest of the logic circuits, as it follows the extracted CMOS flow adopted at the facility. The proposed device uses a single-RESURF and adopts the LOCOS separation method as field oxide. The DC and RF behavior is consistent with what is reported in the literature [10]. The characteristics described in the following paragraphs, more precisely the breakdown voltage of 22 V, show that the proposed device is a good candidate as a power device, RF power amplifiers (PA) for wireless applications, automotive circuits, or similar domains [11,12].

Results and Discussion
The proposed LDMOS structure was generated using the Sprocess tool in Sentaurus simulator [13]. The process flow was extracted from a standard CMOS flow adopted at CDTA [8,9]. CDTA's process uses 14 masks for both the FEOL and BEOL. However, for our study of the FEOL of the LDMOS, the process used seven masks and six implants. Figure 1 shows the general steps.

Results and Discussion
The proposed LDMOS structure was generated using the Sprocess tool in Sentaurus simulator [13]. The process flow was extracted from a standard CMOS flow adopted at CDTA [8,9]. CDTA's process uses 14 masks for both the FEOL and BEOL. However, for our study of the FEOL of the LDMOS, the process used seven masks and six implants. Figure 1 shows the general steps. The substrate was boron-doped with a final resistivity of 10 Ω that corresponds to Nsub = 5 × 10 14 cm −3 , <100> orientation, and 10 µm thickness. The transistor used an epitaxial layer, grown by diffusion at 1000 °C for 6 min, which gave a thickness of 12 µm; the same doping concentration as the substrate was chosen, thus the same resistivity. Next, the 2D mesh engine was triggered and we prepared the n-well, starting with a dry O2 diffusion at 950 °C for 40 min, then photoresist deposition with a thickness of 1.2 µm. The implant used a phosphorus dose of 1.3 × 10 13 cm −2 , at 150 KeV, tilting the substrate at 7°, using the Pearson distribution function.
After, we stripped the oxide. The same procedure was done to prepare the p-well implant, which used a boron dose of 3.7 × 10 13 cm −2 at 160 KeV while adding a rotation of 22°. Before proceeding to other layers, we performed a well drive-in by diffusion in an N2 environment at 1150 °C for 120 min.
The next step was to prepare the LOCOS separation, starting with stripping the previous oxide, diffusing dry O2 at 950 °C for 20 min, then depositing a nitride isotropic layer of 150 nm thickness. We etched the nitride using the LOCOS mask anisotropically. Finally, a wet H2O diffusion was performed at 960 °C for 240 min. The post-LOCOS steps included stripping the nitride and an isotropic oxide etch of 0.2 µm. For the threshold adjustment, we used a Boron implant with a dose of 2 × 10 12 cm −2 at 25 KeV and a tilt of 7°.
The gate oxide used diffusion of dry O2 at 900 °C for 40 min, followed by the polysilicon layer, which used an isotropic deposition doped with phosphorus, with a concentration of 5 × 10 19 cm −3 and a thickness of 0.5 µm. We etched 0.58 µm of poly-silicon using the gate mask anisotropically.
For the lightly doped drain step (LDD), the single implant found in the original process did not yield a good threshold voltage. Vth was too high and it would be an issue for a full integration, thus it had to be changed. We used four consecutive implants of Boron with a dose of 1 × 10 12 cm −2 , a tilt of 30°, and rotation by 90° for each implant. Then, we followed The substrate was boron-doped with a final resistivity of 10 Ω that corresponds to N sub = 5 × 10 14 cm −3 , <100> orientation, and 10 µm thickness. The transistor used an epitaxial layer, grown by diffusion at 1000 • C for 6 min, which gave a thickness of 12 µm; the same doping concentration as the substrate was chosen, thus the same resistivity. Next, the 2D mesh engine was triggered and we prepared the n-well, starting with a dry O 2 diffusion at 950 • C for 40 min, then photoresist deposition with a thickness of 1.2 µm. The implant used a phosphorus dose of 1.3 × 10 13 cm −2 , at 150 KeV, tilting the substrate at 7 • , using the Pearson distribution function.
After, we stripped the oxide. The same procedure was done to prepare the p-well implant, which used a boron dose of 3.7 × 10 13 cm −2 at 160 KeV while adding a rotation of 22 • . Before proceeding to other layers, we performed a well drive-in by diffusion in an N 2 environment at 1150 • C for 120 min.
The next step was to prepare the LOCOS separation, starting with stripping the previous oxide, diffusing dry O 2 at 950 • C for 20 min, then depositing a nitride isotropic layer of 150 nm thickness. We etched the nitride using the LOCOS mask anisotropically. Finally, a wet H 2 O diffusion was performed at 960 • C for 240 min. The post-LOCOS steps included stripping the nitride and an isotropic oxide etch of 0.2 µm. For the threshold adjustment, we used a Boron implant with a dose of 2 × 10 12 cm −2 at 25 KeV and a tilt of 7 • .
The gate oxide used diffusion of dry O 2 at 900 • C for 40 min, followed by the polysilicon layer, which used an isotropic deposition doped with phosphorus, with a concentration of 5 × 10 19 cm −3 and a thickness of 0.5 µm. We etched 0.58 µm of poly-silicon using the gate mask anisotropically.
For the lightly doped drain step (LDD), the single implant found in the original process did not yield a good threshold voltage. V TH was too high and it would be an issue for a full integration, thus it had to be changed. We used four consecutive implants of Boron with a dose of 1 × 10 12 cm −2 , a tilt of 30 • , and rotation by 90 • for each implant. Then, we followed immediately with an arsenic implant for the n-type extension, at a dosage of 1 × 10 15 cm −2 , and 0 • tilt and no rotation. The annealing peaks were at 960 • C under N 2 and O 2 .
Next, the spacers were grown at rate of 150 nm/s at 750 • C, which was etched back as well as 20 nm of silicon. After, we prepared for the source and drain implant by diffusing dry O 2 at 925 • C for 20 min, then deposited a 1.2 µm photoresist layer. The implant used an arsenic dose of 5 × 10 15 cm −2 at 60 KeV, also using the Pearson distribution function.
After, we prepared for the source and drain implant by diffusing dry O 2 at 925 • C for 20 min then deposited a 1.2 µm photoresist layer. The implant used an arsenic dose of 5 × 10 15 cm −2 at 60 KeV, also using the Pearson distribution function.
During the process, we noticed the necessity of two additional annealing steps, one for the source and drain implant and another for the body implant. Without these annealing steps, the low energy implant was not enough for the species to make them penetrate the device at the desired depth. These particular steps used an adequate temperature elevation using N 2 environment, and a mixture of N 2 and O 2 gas flow, for a total duration of 1.67 min in the temperature range 700-1050 • C. We can make sure the annealing did not affect the previous layers destructively by simply observing the before and after structure.
Finally, for the body implant, after a 1.2 µm photoresist deposition, we used a BF 2 dose of 3 × 10 15 cm −2 at 80 KeV with 7 • tilt. Then we stripped the photoresist and performed annealing for 1.57 min. This particular step is the source and drain implant of the PMOS transistors.
Although it is feasible to simulate the deposition and etching of aluminum and titanium, it is not possible to solve the transport equations coupled with temperature for metals in our simulator version. Solving for temperature is critical to accurately evaluate the self-heating effect and the breakdown voltage. Therefore, the metal layers were omitted in the final structure. Figure 2 shows the resulting device. The gate oxide and LOCOS thicknesses are 15 and 787.4 nm respectively. 20 min then deposited a 1.2 µm photoresist layer. The implant used an arsenic dose of 5 × 10 15 cm −2 at 60 KeV, also using the Pearson distribution function.
During the process, we noticed the necessity of two additional annealing steps, one for the source and drain implant and another for the body implant. Without these annealing steps, the low energy implant was not enough for the species to make them penetrate the device at the desired depth. These particular steps used an adequate temperature elevation using N2 environment, and a mixture of N2 and O2 gas flow, for a total duration of 1.67 min in the temperature range 700-1050 °C. We can make sure the annealing did not affect the previous layers destructively by simply observing the before and after structure.
Finally, for the body implant, after a 1.2 µm photoresist deposition, we used a BF2 dose of 3 × 10 15 cm −2 at 80 KeV with 7° tilt. Then we stripped the photoresist and performed annealing for 1.57 min. This particular step is the source and drain implant of the PMOS transistors.
Although it is feasible to simulate the deposition and etching of aluminum and titanium, it is not possible to solve the transport equations coupled with temperature for metals in our simulator version. Solving for temperature is critical to accurately evaluate the selfheating effect and the breakdown voltage. Therefore, the metal layers were omitted in the final structure Figure 2 shows the resulting device. The gate oxide and LOCOS thicknesses are 15 and 787.4 nm respectively.
The device simulation, conducted using the SDevice tool [14], will reflect the front-end of line (FEOL) behavior only. We used the area-factor function to simulate a device width of 100 µm without using an actual 3D mesh. We chose the hydrodynamic transport model with Fermi statistics and density quantization model for electrons, and mobility degradation using the "Inversion-Accumulation layer mobility model" coupled with the Hänsch model for high field saturation. Doping and temperature-dependent Shockley-Read-Hall (SRH), Auger, and avalanche (UniBo) were used to model recombination and impact ionization. Finally, the "OldSlotboom" model was used for bandgap narrowing.  The device simulation, conducted using the SDevice tool [14], will reflect the front-end of line (FEOL) behavior only. We used the area-factor function to simulate a device width of 100 µm without using an actual 3D mesh. We chose the hydrodynamic transport model with Fermi statistics and density quantization model for electrons, and mobility degradation using the "Inversion-Accumulation layer mobility model" coupled with the Hänsch model for high field saturation. Doping and temperature-dependent Shockley-Read-Hall (SRH), Auger, and avalanche (UniBo) were used to model recombination and impact ionization. Finally, the "OldSlotboom" model was used for bandgap narrowing.
The transfer characteristic is plotted in Figure 3a, where the sweep is done for various V DS , from 3 to 30 V with a 3 V step. The highest leakage current (I off ) is 1.3 × 10 −11 A under V DS = 30 V. The curves were then differentiated to show the transconductance (g m ), plotted in Figure 3b. g m keeps increasing with increasing V GS when V DS is high, which is good for RF behavior, as the cut-off and maximum frequencies are directly proportional to g m . useful for current referencing, a common practice in RF design [16]. The ZTC point occurs in our case at ~1.6 V. We also noticed a rise in Ioff, where it reached 1.9 × 10 −8 A at 400 K, which is a good value considering that we did not include any form of thermal dissipation of the backend of the process and the packaging.
As for the breakdown voltage (BV), it was extracted using the continuation method, while maintaining the gate voltage, VGS at 0. BV occurs at VDS = 22 V and approximately 10 −11 A, the result is plotted in Figure 4. If we leave a 30% safe operating area, which is a standard value in LDMOS designs, the limit will be 15.4 V for an off-state drain bias. Figure 5 shows the 2D scalar distribution of the absolute value of the electric field and with its extracted maximum path. The bird's beak and near areas have the highest values, and we reported that it triggers noticeable degradation under hot carrier injection [17,18].   Figure 3c shows the output characteristic plotted for various V GS values. According to this electrothermal simulation, temperature rises, during this DC sweep, did not create the self-heating effect. Self-heating manifests as a dip in I DS after saturation and causes a compression effect in the output characteristic due to the Kirk effect [15], which is practically absent in our device. Instead, this device suffers from a prolonged quasi-saturation regime at low V GS as well as an early on-state breakdown.
We also plotted the transfer characteristic for various temperatures, as shown in Figure 3d, to extract the zero-temperature coefficient point (ZTC). The ZTC point is where the threshold voltage and mobility temperature dependencies are canceled. This point is useful for current referencing, a common practice in RF design [16]. The ZTC point occurs in our case at~1.6 V. We also noticed a rise in I off , where it reached 1.9 × 10 −8 A at 400 K, which is a good value considering that we did not include any form of thermal dissipation of the backend of the process and the packaging.
As for the breakdown voltage (BV), it was extracted using the continuation method, while maintaining the gate voltage, V GS at 0. BV occurs at V DS = 22 V and approximately 10 −11 A, the result is plotted in Figure 4. If we leave a 30% safe operating area, which is a standard value in LDMOS designs, the limit will be 15.4 V for an off-state drain bias.   As mentioned earlier, the LDMOS operates in RF modes, thus it is important to determine its frequency response. The AC sweep simulation saves all possible combinations of capacitances and admittances between the electrodes. The saved data were used in the Svisual tool, which relies on a two-port network configuration to extract the RF parameters. The resistances 150 and 1 kΩ were used for stability at the source and substrate, respectively, as well as using a 100 kΩ resistance for the gate to drain feedback to reduce low-frequency gains. This setup was intended as a first approximation for the LDMOS response, not a final configuration, as further impedance matching will be in SPICE circuit level simulations.
First, we extracted the maximum oscillation frequency (fmax) and the cut-off frequency (fT), using the admittance and hybrid parameters, respectively, with the unit-gain-point method. The results are plotted in Figure 6a,b. Next, we examined the transistor gain as a function of frequency for multiple gate voltages, using Mason's unilateral gain (MUG)  Figure 5 shows the 2D scalar distribution of the absolute value of the electric field and with its extracted maximum path. The bird's beak and near areas have the highest values, and we reported that it triggers noticeable degradation under hot carrier injection [17,18].  As mentioned earlier, the LDMOS operates in RF modes, thus it is important to determine its frequency response. The AC sweep simulation saves all possible combinations of capacitances and admittances between the electrodes. The saved data were used in the Svisual tool, which relies on a two-port network configuration to extract the RF parameters. The resistances 150 and 1 kΩ were used for stability at the source and substrate, respectively, as well as using a 100 kΩ resistance for the gate to drain feedback to reduce low-frequency gains. This setup was intended as a first approximation for the LDMOS response, not a final configuration, as further impedance matching will be in SPICE circuit level simulations.
First, we extracted the maximum oscillation frequency (fmax) and the cut-off frequency (fT), using the admittance and hybrid parameters, respectively, with the unit-gain-point method. The results are plotted in Figure 6a,b. Next, we examined the transistor gain as a As mentioned earlier, the LDMOS operates in RF modes, thus it is important to determine its frequency response. The AC sweep simulation saves all possible combinations of capacitances and admittances between the electrodes. The saved data were used in the Svisual tool, which relies on a two-port network configuration to extract the RF parameters. The resistances 150 and 1 kΩ were used for stability at the source and substrate, respectively, as well as using a 100 kΩ resistance for the gate to drain feedback to reduce low-frequency gains. This setup was intended as a first approximation for the LDMOS response, not a final configuration, as further impedance matching will be in SPICE circuit level simulations. First, we extracted the maximum oscillation frequency (f max ) and the cut-off frequency (f T ), using the admittance and hybrid parameters, respectively, with the unit-gain-point method. The results are plotted in Figure 6a,b. Next, we examined the transistor gain as a function of frequency for multiple gate voltages, using Mason's unilateral gain (MUG) approach. MUG simulation results are plotted in Figure 6c. Stable gains occur if V G ≤ 6 V and under 10 9 Hz frequencies, thus strong inversion regimes must be avoided; it also causes hot carrier injection degradations. and under 10 9 Hz frequencies, thus strong inversion regimes must be avoided; it also causes hot carrier injection degradations. A recapitulation of the DC and RF parameters is presented in Table 1. This simulation showed that integrating RF and/or power modules is possible using the 1 µm CMOS process flow at CDTA, and the results show overall acceptable electrothermal behavior under DC and RF regimes, provided further studies. However, to take full advantage of the RE-SURF principle, which can enhance BV up to 120 V, a slight change in the process flow (like implant energies) and using a double-gate design are more fitting to our targeted applications.

Conclusions
The DC and RF performances of an integrated LDMOS were investigated in this paper. The 2D process simulation was based on the 1 µm CMOS technology node, available at CDTA. The extracted process flow yielded a 22 V BV and 272 mm 2 mΩ RON. The temperature effect and the stability in various bias conditions and frequencies are presented. A recapitulation of the DC and RF parameters is presented in Table 1. This simulation showed that integrating RF and/or power modules is possible using the 1 µm CMOS process flow at CDTA, and the results show overall acceptable electrothermal behavior under DC and RF regimes, provided further studies. However, to take full advantage of the RESURF principle, which can enhance BV up to 120 V, a slight change in the process flow (like implant energies) and using a double-gate design are more fitting to our targeted applications.

Conclusions
The DC and RF performances of an integrated LDMOS were investigated in this paper. The 2D process simulation was based on the 1 µm CMOS technology node, available at CDTA. The extracted process flow yielded a 22 V BV and 272 mm 2 mΩ R ON . The temperature effect and the stability in various bias conditions and frequencies are presented. According to the extracted data, the proposed nLDMOS could be used for power amplifiers in wireless communications, automotive, and similar domains.