Hardware Implementation and Performance Study of Analog PI λ D µ Controllers on DC Motor

: In this paper, the performance of an analog PI λ D µ controller is done for speed regulation of a DC motor. The circuits for the fractional integrator and differentiator of PI λ D µ controller are designed by optimal pole-zero interlacing algorithm. The performance of the controller is compared with another PI λ D µ controller—in which the fractional integrator circuit employs a solid-state fractional capacitor. It can be veriﬁed from the results that using PI λ D µ controllers, the speed response of the DC motor has improved with reduction in settling time ( T s ), steady state error (SS error) and % overshoot (% M p ).


Introduction
PI λ D µ controllers exhibit promising features like minimizing the steady state error, robustness to plant gain variations, disturbance rejection and faster response over PID controllers [1,2]. Some of the works of PI λ D µ controllers are reported in [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. Similarly, the works on a DC motor can be seen in [19][20][21][22][23][24][25][26][27][28][29]. Recent works of analog PI λ D µ controller on a DC motor includes implementation by Operational Transconductance Amplifiers (OTA) [30] or using CMOS op-amp [31]. Even though the above methods can provide electronic tunability, it has disadvantages such as: restriction on the maximum input signal that the circuits can handle (which is less than 1 V), requirement of more active components, resistors and capacitors for its implementation and only simulation studies are published. On the counterpart, a discrete version of the controller on a DC motor can be seen in [32,33] where special care must be taken for choosing the following: sampling rate, A/D and D/A converters, type of discretization rule used, skills in coding, computational and memory requirements. All the above methods utilize frequency domain approach for designing the controller and for that, the model of the plant is essential, and in [34], simulation studies on a model free technique for the design of a data driven fractional PID controller is demonstrated. The algorithm uses iterative computation and hence, it requires a computer.
From the above, it can be seen that the majority of the works done on a DC motor uses discrete type fractional controllers and for analog implementation of PI λ D µ controller, one needs op-amp/other active elements and fractional order elements. The fractional order elements can be implemented either by a multicomponent method (e.g., ladder circuits [35]) or single component fractional capacitors (like the fractional capacitor reported in [36]). The major issue is that the single component fractional capacitors (which reduces the circuit complexity) are not yet commercialized. So in this paper, we will show the performance comparison of two types of analog PI λ D µ controllers on a DC motor emulator in real time. One PI λ D µ controller is employing the commercially available op-amp, resistors and capacitors for its realization and it is compared with the controller implemented using a single component fractional capacitor.
This paper is an extension of the work reported in [37]. In that paper, we have studied the performance of a solid-state fractional capacitor based PI λ D µ controller where the analog fractional integrator has the stated fractional capacitor in the feedback path of the circuit. In this research work, we will develop optimal pole-zero interlacing algorithm based analog I λ and D µ circuits; and the PI λ D µ controller based on this (termed as Type A controller) is implemented on hardware. The performance of Type A PI λ D µ controller is compared with the previously reported PI λ D µ controller (named as Type B: where fractional integrator employs solid-state fractional capacitor). The study is done on the speed regulation of the DC motor emulator. Thus, the paper focuses on the comparison of the performance of these two types of analog PI λ D µ controllers (one by the multicomponent approach and the other by a single component fractional capacitor) and present its advantages.
The paper is divided into six sections. Section 1 deals with the introduction. Section 2 describes Type A and Type B PI λ D µ controllers. The details of the hardware implementation and the tuning algorithm for the fractional PID controller are given in Sections 3 and 4, respectively. Then, the results are elaborated in Section 5 and the conclusion in Section 6.

DC Motor Emulator
The transfer function of the DC motor [37] under study is given as: where V ω (s) is the voltage corresponding to speed and V a (s) is the armature input voltage to the DC motor. Equation (1) is implemented using resistors, capacitors and op-amps to emulate the DC motor which has a gain stage followed by two integration stages (as illustrated in Figure 1), and on this emulated circuit, the comparison studies of Type A and Type B fractional PID controllers have been carried out.

Type A and Type B PI λ D µ Controllers
The block diagram of the controlled DC motor emulator is shown in Figure 2. As mentioned before, the analog implementation of the fractional order PI λ D µ controller is done by two methods: (1) Type A controller, which employs the optimal pole-zero interlacing algorithm [26] for the design of both fractional integrator and differentiator circuits; and (2) Type B controller-here, the fractional integrator block in Type A controller is replaced by a solid-state fractional capacitor [37] circuit. In the case of Type A controller, for I λ implementation, there are separate circuits for K i and s −λ . However, for the I λ circuit of Type B controller, the gain is adjusted by the input potentiometer (R1), as shown in Figure 3.  In general, the control signal from PI λ D µ controller is given as where U(s) is the control signal, E(s) is the error signal, K p , K i and K d are the proportional, integral and differential gains and λ, µ are the fractional exponents of integrator and differentiator, respectively. The description of Type A controller is provided in Section 2.3, which is followed by Type B controller in Section 2.4.

Optimal Pole-Zero Interlacing Algorithm Based Fractional I λ Controller
The optimal pole-zero interlacing algorithm [26] tries to find the rational approximation of the fractional operator in s-domain. It is one of the techniques available in the literature that can be used for the realization of the fractional integral operator. The optimization function used is the rms error of phase angle in the desired band of frequencies and the algorithm tries to find the poles and zeros such that the phase error is less than 1 • . If one uses ladder fractor, then the phase deviation that is obtained will be greater than 1 • for 12 resistor and 12 capacitor combination [35]. Now comparing with the other approximation methods like Charef [38], Oustaloup [39] and Xue [19], these methods require a higher order of the polynomial and the phase error obtained is also greater than 1 • . Considering the analog realization in [40], it requires three resistors, two capacitors and one op-amp for one pole-zero implementation. For that case, the phase error >1 • and the realization have issues in low frequency operation.
Hence, from the above discussion, it can be specified that the order of the optimal pole-zero interlacing algorithm is less when correlated with the other algorithms. Also, in optimal pole-zero analog implementation, it requires three resistors, one op-amp and one capacitor for one pole-zero combination. Thus, it requires fewer components in comparison to the implementation published in [40]. Because of the above advantages, we will use the same for analog implementation of the fractional PID controller.
Next, the approximated transfer function from the optimal pole-zero interlacing algorithm for a fractional integrator with λ = 0.4 which replicates the solid-state fractional capacitor (fabricated by the authors and reported in [41]) is given as: The values of R's and C's for analog implementation of fractional integrator given by Equation (3) is calculated based on the algorithm. It has five stages of pole-zero combination. The analog implementation of the fractional integrator (K i s −0.4 ) requires 8 op-amps, 17 resistors and 6 capacitors, as shown in Figure 3.

Fractional Differentiator (D µ ) Using Optimal Pole-Zero Interlacing Algorithm
The transfer function of fractional differentiator (with µ = 0.4) by the optimal pole-zero interlacing algorithm is: The circuit diagram of the fractional differentiator by optimal pole-zero interlacing algorithm is similar to the fractional integrator circuit but the feedback impedance and input impedance of each stage needs to be interchanged.

Fractional PI λ D µ Controller Using Solid-State Fractional Capacitor (Type B Controller)
The details of the Type B controller using a solid-state fractional capacitor are provided in [37]. The solid-state fractional capacitor (used in the fractional integrator circuit) has Constant Phase (CP) = −31.55 • ± 6.75 • (taken as λ = 0.4) in the frequency range 15 Hz-1 kHz. The fractional differentiator (implemented using optimal pole-zero interlacing algorithm) for this controller will have the same transfer function as in Equation (4) but the K d will be different.

Details of Hardware Implementation
The details of components and instruments employed for the hardware realization are listed below.

1.
Type of DC motor emulator: Armature controlled DC motor 2.
Op-amp IC used for DC motor emulator and analog PI λ D µ controller: TL084 3.

Tuning PI λ D µ Controllers
The tuning algorithm mentioned in [37] has been utilized here and is summarized as 1.
The Simulink model (in MATLAB 2016b) of the controller DC motor system is generated with an input of 1 V.

2.
We define the step response requirements in "Check Response Characteristics" block of MATLAB with rise time <1.98 ms, settling time <13 ms and overshoot ≤12%. Once the model is created, the pattern search optimization method [42] is run to obtain the tuned parameters K p , K i and K d for Type A and Type B controllers.
The parameters of Type A controller are obtained by the above algorithm. The tuning technique provides the optimal values of the parameters satisfying the time domain specifications: rise time <1.98 ms, settling time <13 ms and overshoot ≤12%.

Results and Discussion
The fractional integrator circuit obtained by optimal pole-zero interlacing algorithm has a constant phase angle of −34.5 ± 1.40 • in the frequency range of 10 Hz to 1 kHz. Whereas, for the fractional differentiator, the constant phase angle is 31.48 ± 2.31 • in the frequency range from 10 Hz to 900 Hz (from the hardware implemented D µ circuit). The tuning algorithm mentioned in Section 4 is run to get the values of controller parameters.
There is a difference in the K i and K d values (in Equations (5) and (6)) as the solid-state fractional capacitor is matching only the phase characteristics of the fractional integrator circuit by the optimal pole-zero interlacing algorithm and there is a difference in their impedance characteristics, which have caused the change in the controller gain values.
With the above-designed controllers, a square wave reference signal (V re f = 1 V p , 25 Hz) is given to a cascaded fractional PI λ D µ controlled DC motor emulator and the simulated as well as the real time response graphs are plotted. The simulation (using Multisim) and experimental results for Type A and Type B controlled DC motor emulator are shown in Figure 4, and the corresponding performance metrics are tabulated in Table 1.   The simulation results are showing that Type B controller is better in terms of % overshoot, settling time and steady state error (SS error). Whereas, from the experimental results, it is apparent that the performance measures of Type A controller and Type B controllers are comparable. The difference between the simulation and the hardware results are due to the tolerance of the components used in the hardware.

Fractional Integration of Type A Controller
The fractional integral action on the error signal for Type A controller is graphically shown in Figure 5 (the zoomed version of the error signal is at the right bottom of the figure). The details of the fractional integral action considering error voltage in each section (0-A, A-B, B-C) as sine waves are tabulated in Table 2.  From point C to t = 0.02 s, the output of the fractional integrator is illustrated by Figure 5 as in that range, the error is not sinusoidal. The algorithm mentioned in Section 4 tries to find the gain K i so that the output from the fractional integrator has a value of around 1 V (as we are giving V re f = 1 V) at half the time period of the input signal.
The calculated gain (Table 2) is the ideal case and is not dependent on input amplitude with its value equal to K i × (2 × 3.14 × f ) −λ . However, actual gain is influenced by the input amplitude and saturation limit of the op-amp. For instance, if the gain is 5.63, for an input of 2 V p , the output amplitude should be 11.26 V p and cannot be obtained in this case as the output is bounded to ±10.44 V p (the op-amp used to implement the circuit saturates at ±10.44 V p ). So, for each case, the actual gain will not be equal to the ideal gain of the fractional integrator. It has been observed that with increase in frequency, the calculated gain as well as the actual gain decreases.

Fractional Differentiation of Type A Controller
The fractional derivative action on the error signal is shown in Figure 6; and the details of the fractional differentiation considering error voltage in each section (0-A, A-B, B-C) as sine waves are given in Table 2. From point C to t = 0.02 s, the output of the fractional differentiator is graphically shown in Figure 6. For the fractional differentiator also, the computed gain and the experimental gain are listed in Table 2. The calculation of gain from a fractional differentiator is given by K d × (2 × 3.14 × f ) µ and it is unrelated with input amplitude and saturation limit. However, experimental gain has an influence from input amplitude as mentioned above. Due to which, the calculated gain and actual gain will not be the same. The value of gain increases with increase in frequency for both the calculated gain and the actual gain, that is, it follows the frequency characteristics of the differentiator.
The final controller output, which is the summation of controller efforts from the proportional, fractional integrator and fractional differentiator, will be given to the DC motor emulator. It is mentioned in Section 2 that the DC motor emulator has one gain stage and two integrators (see Figure 1). From Figure 7, we can see that the output from the gain stage of the DC motor (V G ) is the square wave of small intervals, which makes the integrator-1 output (V I1 ) to charge to a lower voltage and the output of integrator-2 (V ωA ) has a minor overshoot; hence making the output value close to 1 V. The short interval square wave is produced from the fractional controller. Also, the saturation element in the fractional controller and the DC motor emulator has an effect on reducing the % overshoot of the DC motor. Whereas, the fractional integrator tries to reduce the steady state error in the speed response. The comparison results show that the performance measures are almost the same for Type A and Type B controller but the number of components can be greatly reduced if one uses a Type B controller (which employs the solid-state fractional capacitors). As mentioned before, the number of components required for implementing fractional integrator (including K i gain block) in Type A controller are: 8 op-amps, 17 resistors and 6 capacitors and the fractional integrator in Type B controller requires: one op-amp, one resistor and the solid-state fractional capacitor. From Table 1, it can be seen that the performance of the DC motor has improved (decrease in T s , % overshoot and steady state (SS) error) when employing fractional PI λ D µ controllers.

Conclusions
In this paper, performance comparison of two types of analog PI λ D µ controllers implemented in hardware and tested on a DC motor emulator is presented. Type B controller uses a solid-state fractional capacitor in the fractional integrator circuit and this controller has an advantage over Type A controller by reducing the number of components in the hardware implementation; but both the controllers' performance measures are comparable. Hence, this study shows that if one does not have a single component fractional capacitor, then also the same performance can be attained using the optimal pole-zero interlacing technique. Apart from the above, it also validates the applicability of the tuning algorithm for Type A controller, which was developed for the Type B controller by the authors in their earlier work. As a future work, the fractional PI λ D µ controllers can be implemented on other systems employing the tuning algorithm proposed and also comparison studies with a digital controller. In addition, analog implementation of PI λ D µ controllers with other components, which reduces the circuit complexity, needs to be explored.