A New Off-Board Electrical Vehicle Battery Charger: Topology, Analysis and Design

The extensive use of electric vehicles (EVs) can reduce concerns about climate change and fossil fuel shortages. One of the main obstacles to accepting EVs is the limitation of charging stations, which consists of high-charge batteries and high-energy charging infrastructure. A new transformer-less topology for boost dc-dc converters with higher power density and lower switch stress is proposed in this paper, which may be a suitable candidate for high-power fast-charging battery chargers of EVs. Throughout this paper, two operating modes of the proposed converter, continuous current mode (CCM) and discontinuous current mode (DCM), are analyzed in detail. Additionally, critical inductances and design considerations for the proposed converter are calculated. Finally, real-time verifications based on hardware-in-loop (HiL) simulation are carried out to assess the correctness of the proposed theoretical concepts.


Introduction
Environmental considerations, the problem of air pollution, the reduction of fossil energy levels, and their cost are the most critical concerns facing governments [1,2].The use of EVs can solve some of these problems.In some cases, these vehicles can inject electricity into the grid (vehicle-to-grid (V2G) technology) and thus play an essential role in decommissioning [3].Battery chargers, the cable between vehicle and charger, feeder, material type and cost, connector, transformer, condition of the ground surface, and peak voltage control are among the challenges facing EVs [4,5].Electric car battery charging systems can be divided into two groups: on-board and off-board [6].On-board systems, which are themselves subdivided into subcategories of AC level 1 and AC level 2, are installed on electric cars.The ability to connect to the distribution power system directly, no need to build a charging station, and its cost are the advantages of this category.However, the need to install a battery charging system in each car, increasing the cost of the car production, low power, and duration time of battery charging are the disadvantages of this type of charging system.Charging of EVs in off-board systems is carried out by charging stations [7].In other words, the equipment related to the charging section of EVs, except for the battery, is only at the charging station.Therefore, the cost of producing electric cars is reduced compared to on-board ones.On the other hand, the power density and efficiency are improved compared to on-board systems, and the charging time is significantly reduced.This type of electric vehicle charging system, also known as DC fast charger (level 3), is classified into two types: ac-connected and dc-connected [8].In acconnected systems, power is supplied from the grid by a transformer, and other equipment Designs 2021, 5, 51 2 of 15 is transferred to ac-bus by an ac/dc converter and a dc/dc converter for each output port.Ac-connected systems are categorized into two categories: extreme fast charging stations and grid-facing ac/dc converters.Dc-connected systems provide the required energy of dc-bus by a transformer and an ac/dc converter.In these systems, dc/dc converters offer the possibility of connecting EVs.In both systems, energy storage systems and renewable energy sources may be used in some applications.In general, dc-connected systems have high efficiency, simple control, and fewer conversion steps compared to ac-connected ones while ac-connected systems have more straightforward protection and more standard measuring equipment.Dc-connected systems are installed in two types: isolated and non-isolated.If the isolation of the charging system is provided by the transformers before the ac/dc converter, it can use non-isolated converters.Although the bidirectional nonisolated boost converters have higher efficiency and easier control systems than most unidirectional non-isolated converters, the simple structure in unidirectional converters has driven research.For EV charging applications, depending on the battery voltage, a unidirectional boost converter can be a suitable and straightforward choice.The power of this type of converter is limited via the current passing through the switches and the inductor size for low current ripple.Various techniques have been introduced to increase the capability of this type of converter.
One of the essential techniques for this type of converter is the switched-capacitor (SC) technique [9,10].In the SC technique, adequate voltage gains, high density, and higher efficiency are provided for this technique.However, the stresses among the semiconductors have limited its use.The interleaving technique is also one of the other techniques introduced.In this technique, several converters can be located in series-parallel to each other to provide more suitable conditions on the output side [11,12].In [11], an interleaved boost dc-dc converter with three-phase legs is introduced.Simple structure, convenient performance, and high power density are its advantages.In [13], the proposed converter in [11] was extended to six phase legs.In [14], a three-phase interleaved boost converter under discontinuous current mode (DCM) has been designed while its small inductor size causes the ability to change the direction of the inductor current and provides zero-voltage switching conditions.In [15], an interleaved boost converter in DCM utilized partial power concepts, and low voltage rates for switches and reduced losses are introduced.The drawback of this structure is the need for a lot of hardware equipment and inner dc-bus balancing.The voltage-lift technique is another popular method for non-isolated boost converters [16,17].In this technique, the voltage is increased step by step, using the energy storage feature in the inductor and capacitor.Losses of semiconductor elements are the most critical drawback of this technique.
In this paper, a new topology for a non-isolated boost dc-dc converter is proposed for the EV charger.First, the topology of the proposed converter is analyzed in detail.Next, the critical inductances are calculated to determine its operating condition, especially for designing for DCM operating as in [15].Then, the designing considerations are carried out for choosing better switches, and a comparison between some literature is presented.Real-time examinations are presented to verify the theoretical concepts.Finally, some concluding remarks are given.

The Proposed Converter Topology Analysis
The proposed converter topology is shown in Figure 1.As observed from this figure, the proposed structure consists of two power electronic switches, two inductors, three capacitors, and three diodes.The switching of the proposed topology is carried out by the PWM technique, where their turning on/off switches are complementary.High voltage gain and high-frequency transformer-less are the proposed topology's advantages, whereas its hard switching condition are the main drawback.The proposed converter voltage gain is carried out using the energy storage (inductors and capacitors) element feature.To simplify the analysis, it is assumed that: (a) the converter is in steady state, so the output voltage V o is constant, (b) the capacitors are large enough and therefore their voltage in each switching period remains unchanged, (c) all switches and diodes are ideal, (d) equivalent series resistance(ESR) ESR is neglected, and (e) the isolation of the system is carried out before the converter.In the following, equations of the current and voltage of each element in CCM and DCM are discussed.the output voltage o V is constant, (b) the capacitors are large enough and therefore their voltage in each switching period remains unchanged, (c) all switches and diodes are ideal, (d) equivalent series resistance(ESR) ESR is neglected, and (e) the isolation of the system is carried out before the converter.In the following, equations of the current and voltage of each element in CCM and DCM are discussed.

Analysis of The Proposed Converter in CCM
In the time interval of on T , the switch of 1 S is turned on and the switch of 2 S is turned off.Then, the inductor 1 L is connected to the input voltage source () i V and its through pass current is increased to its maximum value  L is connected to i V ; therefore, its stored energy is increased.Additionally, the stored energy of the capacitor o C is increased, then it is charged.The equivalent circuit of the proposed topology is shown in Figure 2b.Some key waveforms of the proposed topology in CCM are illustrated in Figure 3a.

Analysis of the Proposed Converter in CCM
In the time interval of T on , the switch of S 1 is turned on and the switch of S 2 is turned off.Then, the inductor L 1 is connected to the input voltage source (V i ) and its through pass current is increased to its maximum value (I LP1 ) from its minimum value (I LV1 ).During this time interval, the diode of D 2 is reversely biased and the diodes D 1 and D o are forward biased.In this time interval, the stored energy of the inductor L 2 is decreased to its minimum value (I LV2 ) from its maximum value (I LP2 ).The equivalent circuit of the proposed topology is shown in Figure 2a.
voltage in each switching period remains unchanged, (c) all switches and diodes are ideal, (d) equivalent series resistance(ESR) ESR is neglected, and (e) the isolation of the system is carried out before the converter.In the following, equations of the current and voltage of each element in CCM and DCM are discussed.

Analysis of The Proposed Converter in CCM
In the time interval of on T , the switch of 1 S is turned on and the switch of 2 S is turned off.Then, the inductor 1 L is connected to the input voltage source () i V and its through pass current is increased to its maximum value  This time interval of T o f f begins when the switch of S 1 is turned off and the switch of S 2 is turned on.In this situation, the diodes of D 2 and D o are turned on and the diode of D 1 is turned off.So, the inductor L 2 is connected to V i ; therefore, its stored energy is increased.Additionally, the stored energy of the capacitor C o is increased, then it is charged.The equivalent circuit of the proposed topology is shown in Figure 2b.Some key waveforms of the proposed topology in CCM are illustrated in Figure 3a.Here, some critical relations of the proposed converter are illustrated.The first index shows the component number and second part is used for time intervals, whereas 1 and 2 show on T and off T in CCM, respectively, and 1, 2, 3, and 4 show 01 ( , ) tt, ) tt at DCM, respectively.By applying the Kirchhoff voltage law (KVL) to the circuit of Figure 2a, the following equation is obtained: Additionally, the equation below can be determined by Figure 2b: The equation below is also written for the inductor By considering , the voltage gain of the proposed converter in CCM can be extracted by substitution ( 1) and ( 2) into voltage balance law for on inductor as follows: Finally, D is obtained from (5) as follows: The voltage and current relation of semiconductors and current ripples of inductors in CCM are shown in Table 1.Here, some critical relations of the proposed converter are illustrated.The first index shows the component number and second part is used for time intervals, whereas 1 and 2 show T on and T o f f in CCM, respectively, and 1, 2, 3, and 4 show (t 0 , t 1 ), (t 1 , t 2 ), (t 2 , t 3 ), and (t 3 , t 4 ) at DCM, respectively.
By applying the Kirchhoff voltage law (KVL) to the circuit of Figure 2a, the following equation is obtained: Additionally, the equation below can be determined by Figure 2b: The equation below is also written for the inductor L 2 : By considering T = T on + T o f f and D = T on /T, the voltage gain of the proposed converter in CCM can be extracted by substitution (1) and ( 2) into voltage balance law for on inductor as follows: Finally, D is obtained from (5) as follows: The voltage and current relation of semiconductors and current ripples of inductors in CCM are shown in Table 1.

Analysis of the Proposed Converter in DCM
At (t 0 , t 1 ), the switch S 1 is turned on and the switch S 2 is turned off.Additionally, the diodes D 1 and D o are on and the diode D 2 is off.Then, the inductor L 1 is connected to V i and its stored energy is increased.Another side, the inductor L 2 is the load path, and its stored energy is decreased.Therefore, the inductor current is reached to the minimum value.The equivalent circuit of the proposed topology is shown in Figure 4a.By applying KVL on Figure 4a,b, we have: Additionally, the following equation can be written for the inductor The equivalent circuit of the proposed topology in DCM; (a) at (t 0 , t 1 ), (b) at (t 1 , t 2 ), (c) at (t 2 , t 3 ), (d) at (t 3 , t 4 ).
The time interval of (t 1 , t 2 ) begins when the diode D o is turned off, whereas the switch S 1 is turned on and the switch S 2 is turned off.In this condition, the diode D 2 is on.So, Designs 2021, 5, 51 6 of 15 the discharge current of the capacitor C o provides the load current and its stored energy is decreased.The equivalent circuit of the proposed topology is shown in Figure 4b.
At (t 2 , t 3 ), the switch S 1 is turned off and the switch S 2 is turned on.Additionally, the diodes D 2 and D o are on and the diode D 1 is off.Then, the inductor L 2 is connected to V i and its stored energy is increased.The store energy of the inductor L 1 is decreased due to its location at the load path.Therefore, the current thorough pass L 1 is reached to its minimum value.The equivalent circuit of the proposed topology is shown in Figure 4c.
At (t 3 , t 4 ), the switch S 1 is still turned off and the switch S 2 is turned on.Meanwhile, the diode D 2 is on, whereas the diode of D o is turned off and the diode D 1 is turned on.During this time interval, the inductor L 2 is connected to V i and is charged.Additionally, the load current is provided by the capacitor C o .The equivalent circuit of the proposed topology is shown in Figure 4d. Figure 3b shows some key waveforms of the proposed topology in DCM.
By applying KVL on Figure 4a,b, we have: Additionally, the following equation can be written for the inductor L 1 : From Figure 4, the equation below also results for the inductor L 2 : V L2,2 = 0, (11) By applying the voltage balance law for the inductor L 2 and replacing (7) to (9) into it, and considering D = (t 0 , t 2 )/T as the duty cycle in DCM, the voltage gain of the proposed converter in DCM is calculated as follows: Therefore, one obtains that: Table 1 shows the voltage and current of the semiconductors and the ripple current of the inductors in this operating mode briefly.

Critical Inductance Calculation
In a dc-dc converter, the CCM and DCM are determined based on the values of the inductors, and the critical inductance determines the boundary between the CCM and DCM.If the inductance value of the inductors is greater than the critical inductance value, the converter will operate in CCM, and if the inductance value of the inductors is less than the critical inductance value, the converter will operate in DCM.
By replacing critical conditions into (7), the following equation is obtained: The equation below can be written for the capacitor: The current of the capacitor C o is equal to: Assuming a new time-off set for T o f f , the current of the inductor L 1 is equal to the following: By replacing ( 18) and ( 17) into ( 16) and considering (19), the equation below is resulted: The above equation can be written as: Substitution of the above relation into (15) yields to: The critical inductance of L 1 can be extracted form (22) as follows: Assuming L 1 = L 2 , we have:

Design Considerations
The peak current flow switch (PCFS) plays a vital role in designing and selecting the type of switch, and finally, the converter price, and it can be minimized by proper selection of the inductor values.Next, the peak current of switches are extracted in CCM and DCM.

Switches Current in CCM
According to Figure 2a,b, the peak current passing through the switches are equal to: By considering (21) and assuming L 1 = L 2 , it has resulted: By considering L 1 = L C1 and L 2 = L C2 into (27), the maximum peak current of the switches are determined as follows: From the above equation, it can be concluded that the peak current passing through the switches depends on the values of D, L and R. Additionally, the maximum peak current of switches can be selected for L 1 = L C1 and L 2 = L C2 .

Switches Current in DCM
According to Figure 5, PCFSs are obtained as follows: Designs 2021, 5, x FOR PEER REVIEW 9 of 1

Switches Voltage Stress
From Figures 2 and 4, the voltage stress of switched-off can be calculated as follows

Efficiency Analysis
Neglecting of the inductors current ripple and the capacitors voltage ripple, the root mean-square (RMS) current relations of inductors is given as follows: Thus, the inductors losses are obtained as follows: The diodes RMS current relations are calculated as follows: 2) By replacing (22) into the above relation, PCFSs are rewritten as follows: From the above relation, it can be seen that the minimum PCFSs in DCM also have an inverse relation with D, R and inductors values and they are obtained by considering L 1 = L C1 and L 2 = L C2 .The maximum PCFSs are obtained for L 1 < L C1 and L 2 < L C2 .Figure 5 shows the relative between the peak current of switches and inductors values.It is obvious that the peak current of switches in DCM is higher than CCM ones.

Switches Voltage Stress
From Figures 2 and 4, the voltage stress of switched-off can be calculated as follows: Designs 2021, 5, 51 9 of 15

Efficiency Analysis
Neglecting of the inductors current ripple and the capacitors voltage ripple, the root-mean-square (RMS) current relations of inductors is given as follows: Thus, the inductors losses are obtained as follows: The diodes RMS current relations are calculated as follows: After neglecting turn off state losses in the diodes and defining Q rr as reverse recovery energy of diode, the diode losses are as follows: The RMS current values of C 1 and C 2 are obtained as follows: the RMS value of capacitor C o current is as follows: The capacitors losses are obtained as follows: Designs 2021, 5, 51 10 of 15 The switches RMS current and their losses are equal to: Thus, the total loss and efficiency are equal to:

Comparison
The comparison results of different converters avilable in the literature and the proposed converter are presented in Table 2.As shown in Table 2, the comparison is made in terms of the number of active and passive elements and the voltage gain in CCM.In terms of the number of active elements, the proposed converter topology has more switches than the ones proposed in [16] and [17].Moreover, the proposed converter has fewer diodes than the topology in [18][19][20], and has the same number of diodes as the ones in [9,10,16,17].Although the number of inductors of the proposed converter is less than [9,17], its number is equal to [10,16,[18][19][20].As a result, the size of the proposed converter may be smaller than the others.In terms of the number of capacitors, the proposed converter has the same number of capacitors compared to [9,16], and has less than [17,19], and more than [10,18].
Figure 6a,b show the changes in the maximum normalized voltage stress of the switch and the maximum normalized voltage stress of the diode, respectively.Except for [10], which has a fixed graph in both analyzes, the values of the maximum normalized voltage stress of the switch and the maximum normalized voltage stress of the diode change varied for different amounts of voltage gain (M).From Figure 6a, the maximum normalized voltage stress of the switch in the proposed converter is almost equal to [9], while compared to [10,16,[18][19][20], the value of the maximum normalized voltage stress of the switch is lower.It is worth noting that the maximum normalized voltage stress of the switch in the proposed converter is more than [17].The maximum normalized voltage stress of the diode at lower yields is better than the converters studied (see Figure 6b).The maximum normalized voltage stress of the diode in the proposed converter is better than [16,[18][19][20], while the value of this parameter is higher compared to [9,10,17].
than the others.In terms of the number of capacitors, the proposed converter has the same number of capacitors compared to [9,16], and has less than [19,17], and more than [10,18].
Figure 6a,b show the changes in the maximum normalized voltage stress of the switch and the maximum normalized voltage stress of the diode, respectively.Except for [10], which has a fixed graph in both analyzes, the values of the maximum normalized voltage stress of the switch and the maximum normalized voltage stress of the diode change varied for different amounts of voltage gain (M).From Figure 6a, the maximum normalized voltage stress of the switch in the proposed converter is almost equal to [9], while compared to [10,16,[18][19][20], the value of the maximum normalized voltage stress of the switch is lower.It is worth noting that the maximum normalized voltage stress of the switch in the proposed converter is more than [17].The maximum normalized voltage stress of the diode at lower yields is better than the converters studied (see Figure 6b).The maximum normalized voltage stress of the diode in the proposed converter is better than [16,[18][19][20], while the value of this parameter is higher compared to [9,10,17].

Experimental Results
Assuming that the switches and diodes are ideal and considering the parameters presented in Table 3, the correctness of the stated theoretical concepts and relations are examined.Based on the suggested converter topology described in Section 2, a hardwarein-loop (HiL) simulating setup is configured based on the OPAL-RT real-time simulator as depicted in Figure 7. Since the HiL is developed in a real-time platform, this simulation is a more practical validation setup than an off-line MATLAB simulation for the verification of system responses to unusual events.First, the operating of the proposed converter

Experimental Results
Assuming that the switches and diodes are ideal and considering the parameters presented in Table 3, the correctness of the stated theoretical concepts and relations are examined.Based on the suggested converter topology described in Section 2, a hardwarein-loop (HiL) simulating setup is configured based on the OPAL-RT real-time simulator as depicted in Figure 7. Since the HiL is developed in a real-time platform, this simulation is a more practical validation setup than an off-line MATLAB simulation for the verification of system responses to unusual events.First, the operating of the proposed converter in critical condition is carried out.Then, CCM and DCM results are recorded for the proposed converter.It should be noted that the recorded time period of the results shown is selected to show the performance of the converter in steady-state.To analyze the performance of the proposed dc-dc boost converter, the operating mode of the converter must first be determined.According to (23) and Table 3, the value of critical inductances for 1 L and 2 L are equal to 256 H , the converter will be in CCM; otherwise, it will be in DCM.The operation of the proposed converter will be in critical mode for 1 .The switch's current waveforms are illustrated in Figure 8a,b.As one can observe from these figures, the maximum peak current of switches is 15A .Additionally, the output voltage in this mode is equal to 209V .
Figure 9 shows the experimental results in CCM.As shown in Figure 9a,b, the maximum peak current of the inductors is 2.7A ; hence, the inductor size can be reduced.It can be noted that  25) to (28).The output voltage is almost equal to 209V , reconfirming the theoretical calculation (see Figure 9e).
Considering the presented parameters in   To analyze the performance of the proposed dc-dc boost converter, the operating mode of the converter must first be determined.According to (23) and Table 3, the value of critical inductances for L 1 and L 2 are equal to 256 µH.If L 1 = L 2 > L C1 = L C2 , the converter will be in CCM; otherwise, it will be in DCM.The operation of the proposed converter will be in critical mode for

Conclusions
In this paper, a new topology of a non-isolated boost dc-dc converter is proposed for the off-board EV charger.High voltage gain and high-frequency transformer-less are the main advantages of the proposed topology.Throughout this paper, the operation of the proposed converter was analyzed at CCM and DCM in detail.Additionally, the critical

Conclusions
In this paper, a new topology of a non-isolated boost dc-dc converter is proposed for the off-board EV charger.High voltage gain and high-frequency transformer-less are the main advantages of the proposed topology.Throughout this paper, the operation of the proposed converter was analyzed at CCM and DCM in detail.Additionally, the critical inductance calculations were carried out, and the designing considerations were extracted for choosing proper switches.Then, the proposed converter was compared with the existing topologies in the literature.The validity of the correctness of the theoretical concepts was verified through HiL setup based on the OPAL-RT simulator.As discussed in Section 2, the output voltage increased to 210 V and 295 V at CCM and DCM, respectively, by D = 50%, V i = 70 V and f = 30.5kHzwith the calculated efficiency equal to 93.1%.Additionally, the maximum peak current of switches reached 15 A, 13 A and 17 A at critical mode, CCM and DCM, respectively.Therefore, the proposed topology can be a suitable appliance as an EV charger.

Figure 1 .
Figure 1.The proposed topology for the boost dc-dc converter.

2 D is reversely biased and the diodes 1 DT begins when the switch of 1 S is turned off and the switch of 2 S 1 D
time interval, the diode of and o D are forward biased.In this time interval, the stored energy of the inductor circuit of the proposed topology is shown in Figure 2a.This time interval of off is turned on.In this situation, the diodes of 2 D and o D are turned on and the diode of is turned off.So, the inductor

Figure 2 .
Figure 2. The equivalent circuit of the proposed topology in CCM; (a) at

Figure 1 .
Figure 1.The proposed topology for the boost dc-dc converter.

Figure 1 .
Figure 1.The proposed topology for the boost dc-dc converter.

2 Dbegins when the switch of 1 S 2 S 1 D 2 LFigure 2 .
Figure 2. The equivalent circuit of the proposed topology in CCM; (a) at

Figure 2 .
Figure 2. The equivalent circuit of the proposed topology in CCM; (a) at T on , (b) at T o f f .

Figure 3 .
Figure 3.Some key waveforms of the proposed topology; (a) at CCM, (b) at DCM.

Figure 3 .
Figure 3.Some key waveforms of the proposed topology; (a) at CCM, (b) at DCM.

Figure 4 .
Figure 4.The equivalent circuit of the proposed topology in DCM; (a) at 01 ( , ) tt, (b) at

Figure 5 .
Figure 5.The relation between the value of the inductances and PCFS.

Figure 5 .
Figure 5.The relation between the value of the inductances and PCFS.

Figure 6 .
Figure 6.The maximum normalized voltage stress for (a) switch and (b) diode.

Figure 6 .
Figure 6.The maximum normalized voltage stress for (a) switch and (b) diode.

Figure 7 .
Figure 7. Photograph of the OPAL-RT setup adopted for the HiL verification.
. The switches' current waveforms are shown in Figure 9c,d, while their maximum values are 13A according to ( neglecting from the third term of the diodes losses relations and fifth and sixth term of switch losses relations yields the calculated efficiency is 93.1% .

Figure 7 .
Figure 7. Photograph of the OPAL-RT setup adopted for the HiL verification.

Figure 8 . 1 S 2 S
Figure 8.The results in critical mode, (a)

Figure 8 .
Figure 8.The results in critical mode, (a) S 1 current, (b) S 2 current, and (c) output voltage.

Figure 9
Figure9shows the experimental results in CCM.As shown in Figure9a,b, the maximum peak current of the inductors is 2.7 A; hence, the inductor size can be reduced.It can be noted that ∆i L1 = ∆i L2 = 1 A. The switches' current waveforms are shown in

Table 1 .
Comparison between proposed converter and the existing topologies.

Table 2 .
Comparison between proposed converter and the existing topologies.

Table 2 .
Comparison between proposed converter and the existing topologies.

Table 3 .
Parameters for the proposed converter topology.