1. Introduction
The MURAY detector [
1] is a compact and modular ionizing radiation tracking system designed for the detection of cosmic ray muons, and built for muographic purposes. It is based on triangular plastic scintillator bars [
2,
3] read out by Silicon Photomultipliers (SiPMs), combining robustness, portability, and high detection efficiency for field operations and experimental campaigns in various environments. The detector architecture allows for accurate reconstruction of muon trajectories with high background rejection capabilities, enabling studies that require high spatial and angular resolution over large detection areas.
Each tracking module consists of orthogonal layers of 64 extruded plastic scintillator bars arranged in an X–Y configuration. When a charged particle—or, in general, ionizing radiation—traverses a scintillator, it generates optical photons that are captured by embedded wavelength-shifting (WLS) fibers and transported to silicon photomultipliers (SiPMs) mounted at one end of the bars. These solid-state photodetectors are operated in Geiger mode and are capable of single-photon sensitivity with excellent timing characteristic and tunable gain [
4]. Their compactness, low voltage operation, and robustness make them ideal for use in portable detection systems.
The MURAY detector is composed of three such 1
X–Y planes, spaced vertically at a distance that depends on the application, as it can be seen in
Figure 1. This configuration allows for the three-dimensional reconstruction of ionizing radiation tracks by means of time-coincident hits in each plane. The spatial resolution and track reconstruction performance depend on the geometric arrangement of the modules, as well as on the electronic settings. The detector achieves a spatial resolution of about 2 mm using a charge centroid reconstruction, and an angular resolution of approximately 4 mrad in the current configuration, determined by the 50 cm separation between the outer tracking planes.
Developed for radiographic imaging with muons [
5,
6,
7,
8,
9,
10,
11,
12,
13], and successfully used for the detection of cavities in the subsoil [
14], the detector was installed inside a hillside at a depth of several tens of meters below ground level, within a system of anthropogenic cavities. This configuration was chosen to experimentally validate the muographic imaging capability by reconstructing a known cavity. Following a period of inactivity, the detector has recently undergone a reactivation process aimed at restoring full functionality and adapting its components to new experimental setups. This included the characterization and verification of the front-end electronics, the integration with an upgraded data acquisition system, and the implementation of further remote control capabilities. In this article, we describe the current configuration of the MURAY detector, the procedures adopted during the reactivation phase, and the preliminary results obtained during free-sky data acquisition.
Although the detector was originally designed to operate with vertically oriented planes for muographic imaging of volcanoes and later served as the basis for the R&D of detectors subsequently developed by our research group, it has been operated in a horizontal configuration since its first application to underground muography. In this setup, a distance of 50 cm is maintained between the first and third X–Y planes, allowing for a sufficiently large solid angle acceptance to image extended volumes.
Overall, the detector layout has remained essentially unchanged since 2013, following an initial upgrade that involved the replacement of the SiPMs and the master electronics board. In its original version, the system operated as a data logger, thus not allowing real-time data acquisition management nor dynamic adjustment of the detector operating parameters.
2. Hardware Characteristics of the Detector
The basic detection module of the MURAY system consists of 32 plastic scintillator bars, each 107 cm in length and with a triangular cross-section (base 3.3 cm, height 1.7 cm). The scintillator, originally developed for the MINERvA experiment [
15] at the Fermilab extrusion facility, is based on polystyrene doped with 1% PPO and 0.03% POPOP, with a peak emission around 420 nm and refractive index of about 1.6. The material has a density of approximately
and provides a light yield of the order of
photons/MeV. Each bar is coated with a 0.25 mm thick titanium dioxide (
) layer to enhance internal light reflectivity and shield against ambient light. A 1.5 mm diameter hole runs along the longitudinal axis of each bar to house a WLS fiber (
Figure 2a). This geometry improves the spatial resolution by enabling a weighted average of the energy deposited among adjacent via charge centroid reconstruction.
The chosen WLS fiber is the blue-to-green multiclad BCF92 with a diameter of 1 mm [
16], selected for its short emission time (about 2.7 ns), and it serves as a light guide. The fibers are fixed in place (
Figure 2b) using an high strength transparent silicone rubber compound RTV615 [
17] with a refractive index of 1.4, lower than that of the scintillator and ensuring optimal optical coupling.
The scintillator bars are glued together with epoxy adhesive 3M Scotch-Weld DP490 [
18] (Saint Paul, MN, USA) and enclosed between two 2 mm thick G11 sheets, a high-performance fiberglass laminate composed of filament glass cloth and epoxy resin. G11 provides excellent mechanical strength under varying environmental conditions and exhibits good thermal resistance. The modules are completely sealed with aluminum tape (
Figure 2c). Four modules are arranged to form a 1
X–Y plane.
The light captured by the 32 WLS fibers in each module is transmitted to a custom SiPM board for optical-to-electrical conversion. Each board hosts 32 SiPMs (
Figure 2d), one per scintillator bar. SiPMs were selected instead of conventional photomultiplier tubes (PMTs) due to their compactness, mechanical robustness, low power consumption (approximately 10 mW), and higher photon detection efficiency. Additionally, SiPMs provide a gain comparable to PMTs (
), excellent timing resolution (<100 ps), fast response (1 ns rise time), and operate at relatively low bias voltages (<100 V).
The specific SiPM model used in the MURAY detector is the Hamamatsu MPPC S12825-050P (Hamamatsu Photonics, Hamamatsu City, Shizuoka, Japan) [
19,
20,
21]. These devices feature 667 pixels with a 50 μm pitch and a total active area of 1.3 mm × 1.3 mm. Key performance parameters at 25 °C are listed in
Table 1.
To minimize signal degradation, both the SiPM board and front-end electronics are housed within an aluminum compartment that encloses the detection module. Because SiPMs are sensitive to temperature fluctuations—which can affect both the dark count rate and breakdown voltage—compensation is applied by adjusting the bias voltage based on temperature sensor readings, thereby maintaining a stable overvoltage level.
The detector design allows for SiPM thermal stabilization through either liquid circulation or Peltier-based systems. A thermally insulated enclosure with temperature controlled air circulation has been developed for use in free-sky conditions, where active temperature control is absolutely essential. The latter, in fact, allows for the targeted stabilization of the detector’s working condition or point (WP) and to protect the entire device from environmental agents that could damage it. During tests, the free-sky data acquisition was carried out at the Department of Physics of the University of Napoli Federico II under controlled environmental conditions, with a temperature of approximately 24 °C.
Overall, the design of the MURAY modules, including their mechanical structure, optical configuration, and thermal management, ensures tough and precise positioning. These characteristics make the MURAY detector an effective and reliable instrument for muographic applications in underground and challenging environmental conditions.
3. The Detector Electronics
As already mentioned, the photons produced within the detector’s scintillator bars are swiftly transported via WLS fibers to the SiPMs, whose detection produces electrical signals, through charge collection. However, due to the intrinsic characteristics of these signals, they cannot be analyzed directly. For this reason, a dedicated electronics has been developed, fulfilling the specific requirements of low power consumption, to address some issues associated with the use of SiPMs.
These include the temperature sensitivity of SiPMs, whose gain, noise, and breakdown voltage levels vary with temperature, and the stability of the bias voltage, which is critical since SiPMs require a precise and stable overvoltage to ensure consistent performance. Therefore, the detector data acquisition system (DAQ) must be able to compensate or remain stable in the presence of temperature fluctuations, especially when no dedicated thermal management is applied. It must also handle coincidences due to spurious events, the largest contributor of which is the dark count rate, which arises from thermally generated charge carriers that cause spontaneous avalanches even in the absence of light, thus reducing the signal-to-noise ratio. The SiPMs used in this work exhibit a dark count rate of the order of 100 kHz. In our operating conditions, the signal thresholds are set such that the effective dark rate is reduced to a few kHz.
The DAQ architecture includes a custom-designed Front-End Electronics (FEE) board for each detector module. This board efficiently reads the 32 output channels of the SiPM array and provides accurate sampling and digitization of the signals. A second board, the MasterPi Board (
Figure 3), is responsible for track detection based on a programmable logic [
22]. Its operations and functionalities are entirely managed by a Raspberry Pi single board computer in its very first version, which communicates with the MasterPi board via a General Purpose Input/Output (GPIO) interface. Both the Front-End Board and the MasterPi board were designed and developed by the Electronics and Detector Service (SER) of the Naples division of the INFN.
The core of the FEE board includes three main components: the Extended Analogue Silicon-PM Integrated ReadOut Chip (EASIROC) [
23], a Field-Programmable Gate Array (FPGA), and a 12-bit Analog-to-Digital Converter (ADC). The EASIROC is an Application Specific Integrated Circuit (ASIC) developed by the OMEGA company at the Laboratoire de l’Accélérateur Linéaire (LAL—Orsay, Paris), specifically designed to read out signals from SiPMs with very low power consumption (∼20 mW per channel). It incorporates 32 input channels, each with an individual 8-bit Digital-to-Analog Converter (DAC) to fine-tune the bias voltage channel by channel, enhancing gain and noise uniformity. Each channel can be independently biased within a 0 to 4.5 V range by subtracting the DAC-controlled voltage from a common reference voltage (
). The chip features dual pre-amplifiers to achieve a dynamic range from 1 to tens of photoelectrons (PE), with a noise level equivalent to a few PEs. Variable shapers are included to reduce electronic noise, and the chip also provides both charge measurement via analog outputs and digital outputs for timing purposes, that reference a programmable threshold set by its internal 10-bit discriminator (DAC10). The EASIROC outputs three types of digital signals: individual trigger outputs for each of the 32 channels, a multiplexed latch signal (Hit Mux Out), and a global OR of all 32 channels (OR32), usually called “fast-OR”. In addition, two analog outputs—Low Gain and High Gain—provide access to the analog memory content of each channel; their gain can be adjusted via the feedback capacitance of the EASIROC related preamplifiers, covering ranges of 1–15 (Low Gain) and 10–150 (High Gain). All unused features can be disabled to minimize power consumption.
The FPGA used on the FEE board is a Spartan-3 device developed by Xilinx (Xilinx Inc., San Jose, CA, USA). This programmable logic device enables the implementation of custom digital processing circuits and serves as a data buffer between the EASIROC and the MasterPi board. It uses a First-In, First-Out (FIFO) architecture, allowing data to be queued on each FEE board and read by the MasterPi, which uses the onboard random access memory (RAM) for fast and efficient data handling.
The analog signals from the EASIROC are digitized by a 12-bit ADC, enabling precise conversion of the analog information into digital form for further processing and storage.
This integrated and optimized design ensures accurate signal acquisition and robust data handling, while meeting the constraints of low power consumption and the specific needs of SiPM-based detection systems.
4. A New Experimental Setup
As for the detector upgrade, the MURAY system has been integrated with a new master board (
Figure 4) via dedicated electronic interfaces, both designed and developed by our group, enabling the adaptation of the existing front-end electronics to the most recent version of the data DAQ, that is equipped with a Raspberry Pi 4 (Raspberry Pi Foundation, Caldecote, UK), which provides a substantial improvement in processing power and stability, memory capacity, and data transfer speed compared to the previous Raspberry Pi used in the former DAQ. Offering enhanced performance, this new version of the master board supports the parallel connection of up to 16 FEE boards, a feature unavailable in the previous model.
The integration of internet-connected power management devices ensures seamless compatibility, improved performance, and full remote control of the detector, allowing on-demand activation, monitoring, and troubleshooting without the need for direct physical access.
In parallel, the mechanical structure of the detector was redesigned to enhance robustness and ensure reliable operation under challenging environmental conditions. The supporting frame was adapted to guarantee integrity during transport, while a custom enclosure with sealed walls and hermetically sealed connectors was developed to protect sensitive electronics from contaminants (
Figure 5). The mechanical design of the detector enclosure has also been equipped with an adjustable base to allow the detector to be tilted up to a maximum of approximately 23 degrees, allowing optimal positioning for free-sky measurements.
The system is supported by an uninterruptible power supply (UPS), which guarantees continuous operation, stable voltage delivery, and safe shutdown procedures in case of power failures. This combination of electronic integration, mechanical reinforcement, and environmental control results in a highly reliable and versatile detector setup, suitable for both laboratory studies and long-term measurement campaigns in harsh field environments.
5. FEE Characterization
Characterization of the front-end electronics is a crucial step in ensuring the detector’s proper operation. This process involves studying the behavior and performance of the electronics to identify potential problems and optimize their operation. Specifically, the analysis focused on the SiPM power system and the response of the acquisition system under various operating conditions, including random signal sampling, pulsed operation, and continuous acquisition. These measurements were performed on 15 FEE boards, 14 newly manufactured and one older board used solely as a reference. To avoid confusion, each board is identified by a code ER–XXX, where XXX corresponds to the serial number of the EASIROC chip mounted on the board.
5.1. Characterization of the SiPMs Bias Voltage Supply
The first characterization focused on the SiPM power supply system. Each FEE board is equipped with an integrated supply designed to provide stable bias voltages, programmable via an 8-bit DAC. The system is based on linear DC–DC converters and electronic switches, which allow the SiPMs to be biased at voltages different from the board supply. While the board itself is powered at 6 V, the switch can deliver a programmable bias voltage between 28 V and 75 V in the ON state, or a safety shutdown voltage of about 4.7–4.9 V in the OFF state to protect the SiPMs. A dedicated ground is employed to minimize the propagation of electrical noise through the FEE board.
The output voltage of the power supply system was measured using a Fluke 325 digital multimeter (Fluke Corporation, Everett, WA, USA), with the SiPMs disconnected to avoid potential damage. At the end of each measurement cycle, it was verified that the output returned to the shutdown voltage value. The experimental data were fitted with a linear model, and the parameters of the best-fit line were determined. All FEE boards showed a linear characteristic. The resolution of the power supply system was found to be about 200 mV, meaning that a single DAC step corresponds to a variation of 200 mV in the supplied bias voltage.
5.2. Response of the Readout Electronics to Injected Signals
The linear response of the charge measurement was evaluated for each channel of every board using a function generator Tektronix AFG3252 (Tektronix Inc., Beaverton, OR, USA). Test pulses with varying amplitudes were injected into a dedicated test input of each FEE board. The injected signals were designed to mimic the detector pulses in terms of amplitude and duration (100 ns).
For each amplitude setting, a sample of 10k pulses was acquired at a fixed rate of 1 kHz, and the corresponding ADC response was recorded. The mean ADC value and its standard deviation were computed for each amplitude, allowing the construction of the response curve. A linear fit was applied to these data to assess the proportionality between the input signal amplitude and the measured charge, as shown in
Figure 6.
The results confirm a linear behavior over the investigated range. The extracted fit parameters are consistent across all channels and boards, demonstrating a uniform response of the readout electronics and validating the reliability of the charge measurement over the operating range.
5.3. System Response to Random Signals
The characterization of the acquisition system response to random signals focused on the evaluation of the pedestal, i.e., the baseline ADC value in the absence of input signals. Since the acquisition system employs 12-bit ADCs for charge measurements, a precise determination of the pedestal is essential, as it defines the reference level from which all signals are measured. Factors such as temperature, power stability, and intrinsic electronic noise can affect this, making its characterization crucial.
Pedestal measurements were performed for all 32 channels of each FEE board in both the bias regime (with the programmed bias voltage applied to the SiPMs) and the shutdown regime (with the safety shutdown voltage applied). For each board and each regime, 50k events were collected. The resulting ADC distributions were Gaussian-like, centered on the pedestal values. Comparisons between representative boards (e.g., ER–094 and ER–231) showed negligible differences between the two regimes: variations were on the order of 1 ADC count in the mean and 0.01 in the RMS. A global analysis across all channels confirmed consistent results, with average pedestal values around 1550 counts (maximum variation of 13) and RMS values around 1.4 counts (maximum variation of 0.3), as shown in
Table 2.
These small fluctuations show that all channels share essentially the same pedestal and that the values remain stable across repeated measurements. The average pedestal per board, computed across all channels, was found to coincide within one standard deviation between the bias and shutdown regimes. This proves that the electronic noise of the acquisition system is independent of the SiPM supply voltage. The stability of the pedestal is therefore the most important outcome of this analysis, as it ensures accurate charge measurements, reduces noise contributions, and improves overall system reliability.
5.4. Characterization of the Acquisition System
The ADC count distributions obtained with the SiPMs connected and the FEE boards installed inside the detector modules are characterized by a pedestal peak, representing the baseline value, followed by photoelectron peaks (
Figure 7). The distance between the pedestal and the first PE peak defines the single-photoelectron gain (single-PE) factor, which provides the ADC-to-PE conversion coefficient and allows the SiPM gain to be determined. As expected, the gain increases with bias voltage above breakdown voltage, but at the cost of increased noise. Therefore, an optimal operating bias must be identified as a compromise between sufficient gain and acceptable noise.
Since the detector requires only 12 FEE boards out of the 14 previously tested, two boards with the poorest performance were excluded based on earlier analyses: ER–233 (largest standard error in the SiPM power supply characterization) and ER–244 (worst response in the pulsed regime). The remaining 12 boards were installed in the detector as indicated in
Table 3 and tested in acquisition mode. To verify light isolation, data were collected in two configurations: “no-light” mode (dark fabric covering the module) and “light” mode (no cover, ambient light). In both cases, one million events per module were acquired at a stable bias voltage of 69 V and an ambient temperature of about 24 °C.
The results reported in
Table 3 show excellent agreement between the two configurations, with differences well within statistical fluctuations. No systematic variation is observed across different planes or layers. The comparison clearly indicates that the presence of ambient light has a negligible impact on the detector response, confirming the effectiveness of the optical shielding and the robustness of the readout system.
In addition to the “good” channels, two types of non-ideal behaviors were observed. Subdued channels showed reduced event tails and poorly resolved PE peaks, generally due to under-biasing; they could often be recovered by slightly increasing the SiPM voltage, though at the risk of worsening other channels on the same board. Dead channels exhibited only the pedestal without visible PE peaks, either due to insufficient bias or to defective SiPMs. In the first case, recovery was sometimes possible by adjusting the bias; in the second, the 1 PE factor was inferred from neighboring good channels.
Overall, only minor issues were found. Boards equipped with ER–234 and ER–240 required small bias adjustments to recover subdued channels, while boards equipped with ER–235 and ER–232 exhibited non-functional channels (four and one, respectively as reported in
Table 4). All other boards showed stable and consistent behavior, ensuring the readiness of the detector for operation.
6. Detector Calibration and Working Point Optimization
The calibration measurements were performed in the particle laboratory of the Physics Department, University of Naples Federico II (Monte Sant’Angelo campus). The MURAY detector was assembled in its final configuration, consisting of twelve detection modules arranged in three orthogonal planes. Each plane is composed of two orthogonal layers, each read out by two FEE boards equipped with SiPM arrays.
The compact detector geometry, with an overall height of 50 cm and an inter-plane distance of 25 cm, provides a total active area of 1
and facilitates operation in confined environments, such as underground sites. The trigger logic was configured to select through-going muons by requiring a triple-plane coincidence according to
where
, and each layer signal
(
j ranging from 1 to 6) corresponds to the logical OR of the OR32 outputs from its two associated FEE boards. Coincidence timing was constrained within the muon transit time through the detector (∼1.7 ns) to suppress accidental triggers.
6.1. SiPM Bias Voltage Characterization
The SiPM operating voltage was optimized through two sets of pedestal acquisition runs. A coarse scan (9 runs, 13 min each) explored bias voltages from 65.0 V to 68.2 V, identifying the range 66.0–67.0 V as the region combining acceptable trigger rates with negligible dark counts. A subsequent fine scan (2 h per run) refined the analysis in the 66.5–66.7 V range.
The pedestal spectra from all channels were analyzed using a C++/ROOT v6 algorithm to identify PE peaks and extract the single-photoelectron gain (single-PE) factor. The linear fit in
Figure 8 of single-PE versus bias voltage confirmed the expected proportional behavior between gain and bias voltage, allowing the extraction of breakdown voltage
and SiPM gain
.
Non-functional or anomalous channels were found on some board which was thus placed in the middle plane. These boards are listed in
Table 4 and as it is shown, two subdued channels on board 12 were recovered by individually tuning their bias voltages via 8-bit DAC adjustments.
From the analysis of trigger and accidental rates, the optimal bias voltage range was confirmed to be at 66.5–66.7 V.
6.2. Threshold Optimization
The threshold, controlled by a 10-bit DAC, defines the minimum signal level required to generate an event trigger. The OR32 rate was measured as a function of the DAC threshold for six bias voltages (65.0–67.0 V) on all twelve FEE boards, as shown for one board in
Figure 9.
As expected, the OR32 rate increased stepwise with the DAC setting, reflecting the multi-peak nature of the PE spectra. Higher bias voltages resulted in wider plateau regions due to increased single-PE factor.
The optimal compromise between high trigger rate and low accidental rate was achieved for a bias voltage of 66.7 V and a DAC threshold corresponding to the fourth PE peak, i.e., DAC values between 520 and 610 across the boards.
Stability tests conducted over multiple runs revealed small variations in the OR32 rate—primarily due to temperature variations, since no thermal stabilization was employed—but no measurable changes in the pedestal distributions have been measured as shown in
Figure 7, confirming the robustness of the selected working point (WP).
6.3. Trigger Logic Optimization
To mitigate the effect of non-functional channels in the middle plane, a permissive trigger logic configuration
, alternative to that in Expression (
1), was tested. In both cases, trigger and accidental rates were measured as a function of the DAC threshold; the corresponding results are presented in the top plots of
Figure 10. In the standard logic, the WP corresponding to a cut at the 5th PE provided an optimal balance, with a high trigger rate and minimal accidental rate. In the permissive configuration, a new optimal point was found by setting the cut at the 5th PE, where both trigger and accidental rates increase achieving a modest increase in the trigger rate without degrading background suppression, as shown in
Table 5.
The signal-to-noise ratio (SNR), defined as
where
and
are the trigger and accidental rates, respectively, reached values close to unity in both configurations. The
remained stable over a wide DAC range, as illustrated in the bottom plots of
Figure 10, confirming the robustness of the optimized settings.
7. Discussion
The results obtained during tests and calibration established a stable and efficient operating configuration for the MURAY detector. The optimal working point corresponds to a SiPM bias voltage of 66.7 V and a trigger threshold set at the 5th PE level, regardless of the trigger logic, yielding signal-to-noise ratios close to unity. Both standard and permissive trigger logics ensure high trigger rates (∼85 Hz and 90 Hz respectively) and low accidental rates (<0.15 Hz).
The system demonstrated robust performance and stability over extended periods, validating its suitability for extended acquisition campaigns and field deployments, with only minimal sensitivity to ambient temperature variations in the absence of active thermal stabilization, and therefore suitable for the subsequent use of the equipment within the salt mine of Realmonte (Sicily).
Calibration of the detector allowed the muon flux to be measured, with respect to the variables zenith angle and azimuth. A long data-taking run was performed under free-sky conditions, with the detector’s planes oriented horizontally. Data were collected using both trigger logics, but as expected, the permissive logic allowed the recovery of additional muon events, resulting in a slight increase in trigger rate with negligible impact on background rejection.
The free-sky measurements confirm the correct reconstruction of the muon angular distribution, thus validating the detector’s overall design and tracking capability. The measured muon flux as a function of the zenith angle, shown in
Figure 11a, is in agreement with expectations [
24,
25]. The azimuthal distribution of the muon flux, shown in
Figure 11b, while expected to be flat, exhibits deviations in the form of peaks arising from the geometrical acceptance of the detector. These results demonstrate that the upgraded detector meets the requirements for reliable long-term muographic measurements in challenging environments.
8. Conclusions
In this work, we have presented the mechanical recovery, electronic upgrade, and full performance re-evaluation of the MURAY muon detector, originally developed for volcano radiography within the INFN framework. After a prolonged period of inactivity, the system has been successfully reactivated and integrated with a modern data acquisition architecture, including updated front-end electronics, a new Raspberry Pi 4-based master board, improved power management, and enhanced remote control capabilities.
The detailed characterization of the front-end electronics demonstrated excellent linearity and stability of the SiPM bias voltage supply. Pedestal measurements confirmed remarkable stability across channels and operating regimes, with negligible dependence on the SiPM bias condition. The acquisition system showed consistent single-photoelectron resolution and reliable gain behavior as a function of overvoltage, enabling precise calibration of all active channels.
Despite its original design dating back 15 years, the upgraded MURAY detector maintains competitive tracking capabilities and robust operational stability. The successful recovery of subdued channels through DAC8 tuning, the management of non-functional channels via masking strategies, and the validation of light isolation and environmental protection confirm the reliability of the system in realistic operating conditions.
The improved mechanical structure, environmental shielding, and remote operation features make the system particularly well adapted for long-term deployment in challenging environments, such as underground sites and geophysical campaigns.
Overall, this work shows that legacy detector systems, when properly upgraded and requalified, can continue to provide high-quality performance for modern muographic investigations. The MURAY detector is now in use in the Realmonte salt mine, and represents a reliable and versatile instrument for future applications in geophysics and underground imaging.
Author Contributions
Conceptualization, G.S., F.A. and L.C.; Detector upgrade design, G.S., D.I., L.R. and L.C.; Detector recovery, V.B., L.C., G.N. and G.S.; Detector mechanical upgrade, C.A., V.B., L.C., M.M., G.N. and G.S.; FEE board characterization, V.T. and L.C.; Detector calibration, G.S., V.T. and L.C.; DAQ upgrade, A.A., V.B., L.C., V.M., M.M. and G.S.; Slow control and remote control, V.B., L.C. and G.N.; Data analysis, G.N., V.T., G.S., F.A. and L.C.; Original draft writing, L.C. All authors have read and agreed to the published version of the manuscript.
Funding
The detector upgrade was partially supported by the Italian Ministry of University and Research (MUR) under the PRIN 2022 program (grant no. P2022EBPMH).
Data Availability Statement
The data presented in this study are not publicly available but may be available from the corresponding author upon reasonable request.
Acknowledgments
The authors would like to thank Umberto Di Cerbo, of the Naples Division of the INFN, for his assistance in upgrading the detector’s mechanics.
Conflicts of Interest
The authors declare no conflicts of interest.
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Figure 1.
View of the MURAY detector setup used during tests and electronics upgrade. Each plane consists of two orthogonal layers read out by SiPM-based front-end boards.
Figure 1.
View of the MURAY detector setup used during tests and electronics upgrade. Each plane consists of two orthogonal layers read out by SiPM-based front-end boards.
Figure 2.
Detailed view of the module and its internal components not visible in the assembled system. Each module has an edge-to-edge width of 54.4 cm, a height of approximately 2 cm, and a length of 130 cm. (a) Wavelength-shifting fibers inserted into the extruded scintillator holes during module assembly and routed to the SiPM interface carrier. (b) Detail of the coupling between fibers and scintillator bars. (c) Assembled module partially covered with aluminum tape to shield it from ambient light (the green-emitting fibers, visible through the SiPM interface carrier, correspond to the uncovered region of the module). (d) SiPM readout board showing the 32-SiPM array and the associated electronic connections during laboratory tests.
Figure 2.
Detailed view of the module and its internal components not visible in the assembled system. Each module has an edge-to-edge width of 54.4 cm, a height of approximately 2 cm, and a length of 130 cm. (a) Wavelength-shifting fibers inserted into the extruded scintillator holes during module assembly and routed to the SiPM interface carrier. (b) Detail of the coupling between fibers and scintillator bars. (c) Assembled module partially covered with aluminum tape to shield it from ambient light (the green-emitting fibers, visible through the SiPM interface carrier, correspond to the uncovered region of the module). (d) SiPM readout board showing the 32-SiPM array and the associated electronic connections during laboratory tests.
Figure 3.
The first version of the MasterPi board features a first-generation Raspberry Pi connected to the board via the GPIO. Visible on the left side of the board are the connector for the data cable that daisy-chains all the FEE boards, and the trigger cable connectors that connect in parallel to each FEE board.
Figure 3.
The first version of the MasterPi board features a first-generation Raspberry Pi connected to the board via the GPIO. Visible on the left side of the board are the connector for the data cable that daisy-chains all the FEE boards, and the trigger cable connectors that connect in parallel to each FEE board.
Figure 4.
The new MasterPi board adapted for use with the MURAY detector. A Raspberry Pi 4 SBC is connected to the master electronics board via GPIO. Active adapter boards have been designed and produced to connect both the data and trigger cables of the FEE boards in parallel with the new master board.
Figure 4.
The new MasterPi board adapted for use with the MURAY detector. A Raspberry Pi 4 SBC is connected to the master electronics board via GPIO. Active adapter boards have been designed and produced to connect both the data and trigger cables of the FEE boards in parallel with the new master board.
Figure 5.
Photograph taken in our laboratories of the MURAY detector enclosed in a hermetically sealed casing. The orange box highlights the MasterPi unit, while the yellow box identifies the auxiliary systems, including the power supply (UPS), remotely controllable switches, NAS, Ethernet switch, and data acquisition control hardware. The red crosses indicate the positions of the five temperature and humidity sensors installed inside the enclosure. The tilting hinge, visible at the bottom left of the structure, allows the entire system to be inclined up to 23°. The wheels mounted on the base enable the easy movement of the about one-ton apparatus.
Figure 5.
Photograph taken in our laboratories of the MURAY detector enclosed in a hermetically sealed casing. The orange box highlights the MasterPi unit, while the yellow box identifies the auxiliary systems, including the power supply (UPS), remotely controllable switches, NAS, Ethernet switch, and data acquisition control hardware. The red crosses indicate the positions of the five temperature and humidity sensors installed inside the enclosure. The tilting hinge, visible at the bottom left of the structure, allows the entire system to be inclined up to 23°. The wheels mounted on the base enable the easy movement of the about one-ton apparatus.
Figure 6.
Linear response of one channel of a FEE board. Each point was measured by sending 10k pulses of a given amplitude at a 1 kHz frequency to a dedicated test input of the board. The reported value represents the coefficient of determination of the linear fit, quantifying the goodness of the fit.
Figure 6.
Linear response of one channel of a FEE board. Each point was measured by sending 10k pulses of a given amplitude at a 1 kHz frequency to a dedicated test input of the board. The reported value represents the coefficient of determination of the linear fit, quantifying the goodness of the fit.
Figure 7.
Typical SiPM pedestal spectrum showing well-separated photoelectronic peaks at a bias voltage of 66.7 V. The first peak corresponds to the pedestal noise signal, followed by a first photoelectron peak (1 PE), with a constant spacing of about 35 ADC counts between neighboring PE peaks, the so-called single-photoelectron gain factor. The image shows the overlay of two pedestal spectra acquired at the same bias voltage hours apart, and therefore, with different environmental conditions with temperature decreasing from 27 °C (run 1) to 24 °C (run 2).
Figure 7.
Typical SiPM pedestal spectrum showing well-separated photoelectronic peaks at a bias voltage of 66.7 V. The first peak corresponds to the pedestal noise signal, followed by a first photoelectron peak (1 PE), with a constant spacing of about 35 ADC counts between neighboring PE peaks, the so-called single-photoelectron gain factor. The image shows the overlay of two pedestal spectra acquired at the same bias voltage hours apart, and therefore, with different environmental conditions with temperature decreasing from 27 °C (run 1) to 24 °C (run 2).
Figure 8.
Linear dependence of the single−PE factor on the bias voltage. The data points represent the measured values of the channel 18 of the board 1.
Figure 8.
Linear dependence of the single−PE factor on the bias voltage. The data points represent the measured values of the channel 18 of the board 1.
Figure 9.
Measured OR32 rate as a function of DAC threshold for different bias voltages. Plateau regions correspond to the working range around a given PE peak.
Figure 9.
Measured OR32 rate as a function of DAC threshold for different bias voltages. Plateau regions correspond to the working range around a given PE peak.
Figure 10.
Trigger rates (red dots) and accidental rates (black dots) measured under free-sky conditions for standard (
top left) and permissive (
top right) logic. The dashed vertical line indicates the baseline threshold value in DAC10 setting, based on working point settings; the vertical dashed lines represent the trigger rates measured for the two configurations, as listed in
Table 5. Additionally, the SNR as a function of threshold value is plotted for both trigger logic configurations.
Figure 10.
Trigger rates (red dots) and accidental rates (black dots) measured under free-sky conditions for standard (
top left) and permissive (
top right) logic. The dashed vertical line indicates the baseline threshold value in DAC10 setting, based on working point settings; the vertical dashed lines represent the trigger rates measured for the two configurations, as listed in
Table 5. Additionally, the SNR as a function of threshold value is plotted for both trigger logic configurations.
Figure 11.
Measured zenithal (a) and azimuthal (b) angular distributions of the muon flux with MURAY detector layers placed horizontal.
Figure 11.
Measured zenithal (a) and azimuthal (b) angular distributions of the muon flux with MURAY detector layers placed horizontal.
Table 1.
Key specifications of the Hamamatsu S12825-050P SiPMs at 25 °C, according to the datasheet.
Table 1.
Key specifications of the Hamamatsu S12825-050P SiPMs at 25 °C, according to the datasheet.
| Parameter | Value |
|---|
| Dark Count Rate (/) | 55 |
| Photon Detection Efficiency (%) | 40 |
| Gain | 1.7 × |
| Temp. Coeff. (mV/°C) | 54 |
Table 2.
Comparison of mean ADC counts measured in bias and shutdown conditions of the on-board SiPM power supply for each channel. The reported uncertainty corresponds to the standard deviation of the 32 mean values measured for each channel. The mean values are computed per board, each reading 32 SiPM channels.
Table 2.
Comparison of mean ADC counts measured in bias and shutdown conditions of the on-board SiPM power supply for each channel. The reported uncertainty corresponds to the standard deviation of the 32 mean values measured for each channel. The mean values are computed per board, each reading 32 SiPM channels.
| ID | Bias Mean Counts | Shutdown Mean Counts |
|---|
| ER–094 | | |
| ER–231 | | |
| ER–232 | | |
| ER–233 | | |
| ER–234 | | |
| ER–235 | | |
| ER–236 | | |
| ER–237 | | |
| ER–239 | | |
| ER–240 | | |
| ER–241 | | |
| ER–242 | | |
| ER–243 | | |
| ER–244 | | |
| ER–245 | | |
Table 3.
Detector board layout organized by plane, layer, and front-end board identification. The last four columns show mean pedestal values (MV) and corresponding standard deviations (SD) under ambient light conditions (“Light”) and with the detector covered by a light-shielding fabric (“No light”). The values are obtained by averaging over the 32 SiPM channels read out by each board.
Table 3.
Detector board layout organized by plane, layer, and front-end board identification. The last four columns show mean pedestal values (MV) and corresponding standard deviations (SD) under ambient light conditions (“Light”) and with the detector covered by a light-shielding fabric (“No light”). The values are obtained by averaging over the 32 SiPM channels read out by each board.
| Detector Layout | Light | No Light |
|---|
|
Plane
|
Layer
|
FEE Board
|
Chip ID
|
MV
|
SD
|
MV
|
SD
|
|---|
| (Top) | | 1 | ER–237 | 1549.16 | 3.09 | 1549.03 | 3.10 |
| 2 | ER–242 | 1578.15 | 2.49 | 1578.10 | 2.49 |
| 3 | ER–239 | 1556.59 | 3.57 | 1556.30 | 3.57 |
| 4 | ER–243 | 1568.50 | 2.70 | 1568.32 | 2.71 |
| (Middle) | | 5 | ER–231 | 1548.04 | 2.69 | 1547.99 | 2.68 |
| 6 | ER–235 | 1562.91 | 2.62 | 1569.54 | 2.49 |
| 7 | ER–240 | 1570.27 | 3.02 | 1569.92 | 2.99 |
| 8 | ER–232 | 1565.18 | 3.45 | 1564.96 | 3.46 |
| (Bottom) | | 9 | ER–236 | 1566.27 | 3.21 | 1566.01 | 3.23 |
| 10 | ER–241 | 1563.80 | 2.44 | 1563.59 | 2.45 |
| 11 | ER–245 | 1549.49 | 3.21 | 1549.30 | 3.19 |
| 12 | ER–234 | 1550.61 | 2.37 | 1550.32 | 2.37 |
Table 4.
List of Non-Functional Channels and Recovery Actions.
Table 4.
List of Non-Functional Channels and Recovery Actions.
| Board | Channels | Action |
|---|
| 6 | 16, 17, 26, 27, 28 | Masked |
| 8 | 4 | Masked |
| 12 | 7, 22 | Tuned |
Table 5.
Measured Rates in Free-Sky Configuration.
Table 5.
Measured Rates in Free-Sky Configuration.
| Logic | Trigger Rate [] | Accidental [] | SNR |
|---|
| Standard | 85.4 | 0.08 | 0.999 |
| Permissive | 90.2 | 0.13 | 0.998 |
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