Design of a Nonhomogeneous Nonlinear Synchronizer and Its Implementation in Reconﬁgurable Hardware

: In this work, a generalization of a synchronization methodology applied to a pair of chaotic systems with heterogeneous dynamics is given. The proposed control law is designed using the error state feedback and Lyapunov theory to guarantee asymptotic stability. The control law is used to synchronize two systems with different number of scrolls in their dynamics and deﬁned in a different number of pieces. The proposed control law is implemented in an FPGA in order to test performance of the synchronization schemes.


Introduction
Dynamical systems that exhibit chaotic behavior have proven to be very useful in science and engineering, for this same reason it is important to look for implementation alternatives that are fast and reliable. FPGAs are a very useful technology for these types of needs, due to their flexibility and the user friendly programming approach.
Since the discovery of systems with chaotic behavior, multiple analysis have been carried out [1][2][3][4], and the topic of synchronization of this class of systems has been a highly studied topic during the last 30 years [5]. This is due to the mistaken perception that this class of systems cannot be synchronized due to the complexity of their dynamics. This myth vanished in 1983 thanks to Yamada and Fujisaka [6] where a methodology for the synchronization of two chaotic systems using bidirectional coupling is presented, meanwhile in 1990 Pecora and Carroll [7] proposed the synchronization of the drive and response systems with different initial conditions. Since then, a wide series of alternative methodologies for the synchronization of chaotic systems have been developed [8][9][10][11][12][13][14][15][16] and thanks to this methodologies, a vast quantity of possible applications have been found in science and engineering, from physics [17,18], optics [19,20], biology [21][22][23], chemistry [24,25] and specially in the branch of secure communications [26][27][28].
A wide variety of chaotic systems have been implemented in circuits [29][30][31][32][33], this class of circuit implementations have certain disadvantages, such as the fact that they need very large changes in case the system wants to be modified. FPGAs have shown great flexibility in this regard [34][35][36] and although the original system changes, the only significant change is the reprogramming of the FPGA, which represents a great advantage when working on prototyping of new applications, a situation that represents cost savings and implementation times.
The aim of this work is to generalize a master-slave synchronization methodology in order to synchronize two chaotic systems with heterogeneous dynamics, which means that the master system and the slave system do not need to present the same behavior through time and it is not necessary that they are defined in the same number of parts, for example, the master system can be a system defined as a piecewise system, with n parts, while the slave system can be defined in a single part, with a single domain. In addition to this, the implementation of the most representative synchronization scheme is carried out in an FPGA, which allows these schemes to be used in multiple different applications.
The rest of this work is divided in the following way: in Section 2 the systems with which we will work are presented and a brief description of them is given; in Section 3, four different synchronization schemes are presented, including the methodology; in Section 4 the implementation of one of the schemes in an FPGA is presented and the results obtained are shown; finally, in Section 5 the conclusions are presented.

Preliminaries
This section presents in a non exhaustive way the dynamical systems that will be used in the rest of the paper.

Unstable Dissipative Systems
Now consider a unstable dissipative system (UDS) defined in [38] aṡ where χ = (χ 1 , χ 2 , χ 3 ) T , A = (α ij ) 3 j=1 and B contains the switching law of the form It is possible to define two types of UDS, and two types of correspond equilibria.
Definition 1 (Campos-Cantón et al. [39]). A system given by (2) with eigenvalues λ i , i = 1, 2, 3, satisfying ∑ 3 i=1 λ i < 0. Then, the system is said to be: (i) An UDS Type I, if one eigenvalue is negative real and the other two are complex conjugate with a positive real part. (ii) An UDS Type II, if one eigenvalue is positive real and the other two are complex conjugate with a negative real part.
For the equilibria, their two types are defined accordingly. In Definition 1, item (i) implies that the UDS Type I is dissipative in one of its components but oscillatory unstable in the other two, while item (ii) implies that an UDS Type II is dissipative and oscillatory in two of their components but unstable in the other one. Some chaotic dynamical systems may relate to these two types of UDS around equlibria, systems as the ones in [29,[40][41][42] can be characterized through a combination of UDS Type I and Type II.

Synchronization Scheme
The synchronization scheme diagram is depicted the Figure 1. The output X of the master FPGA is the input of the slave FPGA, the controller takes this input X and the output Y of the slave system inside of the slave FPGA and compensates the slave system output, which means that lim t→∞ |Y − X| = 0. The rest of this Section presents four master-slave synchronization schemes.

Consider the master system aṡ
while the slave system is defined aṡ where u = (u 1 , u 2 , u 3 ) T . The error vector is defined as e = x − χ, and is possible to obtaiṅ In order to stabilize the error system, the proposed Lyapunov function is whose derivative is which allows to design the control law u as where e = (e 1 , e 2 , e 3 ) T is the error vector, and P = P T = diag{p 2 1 , p 2 2 , p 2 3 } is a diagonal matrix of parameters selected to ensure negativeness of (8).

Master GLS-Slave UDS
For this scheme the master system is considered aṡ while the slave system isχ The error vector is defined as e = χ − x, consequently the error dynamics are represented bẏ Similarly to the previous scheme, the proposed Lyapunov function is while in this scheme the derivative results iṅ Under the before considerations, the proposed control law is where, in the same form as before P = P T = diag{p 2 1 , p 2 2 , p 2 3 } is a matrix of parameters selected to ensure the negativeness of (14).

Master GLS-Slave GLS
The master system for this synchronization scheme iṡ However, in this scheme the slave system is defined aṡ Once again, u = (u 1 , u 2 , u 3 ) T is the controller. The error is defined as e = y − x, and its dynamics is given byė In order to stabilize the error dynamics, the proposed Lyapunov function is where the derivative iṡ which allows to design the controll law u as

Master UDS-Slave UDS
Finally, the master system for this scheme iṡ The dynamics of the error ϕ − χ is given by and once again, the proposed Lyapunov function is with derivativė Consequently, the proposed control law is

Results
For the implementation of the synchronization scheme, the selected piecewise UDS given in [43] presents a four scrolls attractor and it is defined aṡ where B k is given by and the slave system isẋ Using the synchronization scheme described in the Section 3.1, the control law is defined as which will be implemented in a SPARTAN-3AN FPGA Starter Kit board from Xilinx, the general scheme can be appreciated in the Figure 2. It can be seen that in (a) the SPARTAN-3AN starter kit board in which the master system is implemented; in (b) the slave system is implemented with the control law (31); in (c) the Digital to Analog Converter (DAC) can be observed and in (d) the output data is acquired. In order to implement the synchronization scheme in the SPARTAN-3AN starter kit, the Simulink R toolbox: Xilinx System Generator was used. In the Figure 3 can be observed the classical Lorenz system without any kind of control, implemented in Simulink R using this toolbox as example. When implementing the master system in the FPGA, it is possible to acquire the output signal using the DAC from the National Instruments module NI-6211. With this is possible to obtain the plane projections (χ 1 , χ 2 ) and χ 1,2 vs t, this can be appreciated in the Figure 4. This is also applicable to the projection on the plane (χ 1 , χ 3 ), as can be seen in the Figure 5. The projections (χ 2 , χ 3 ) are shown in the Figure 6, and the FPGA resources utilized by the master system is presented in Table 1.    For the uncontrolled slave system, both of the projections on the planes (x 1 , x 2 ) and (x 1 , x 3 ) were obtained and they can be seen in Figure 7. The projections on the plane (x 2 , x 3 ) are depicted in Figure 8. It is important to highlight that the slave system arises a two-scroll attractor while the master system presents four scrolls. Consequently, once implemented the control law, the slave system will change its dynamics undergoing a four-scroll attractor behavior with the shape of the master systems's phase portrait. The FPGA utilization summary for the slave system is presented in Table 2.   For the synchronized slave system, both of the projections on the planes (x 1 , x 2 ) and (x 1 , x 3 ) were obtained and they can be observed in the Figure 9. The projections on the plane (x 2 , x 3 ) are depicted in the Figure 10. It is easy to see that the two-scroll slave system in fact adopted the master system behavior presenting four scrolls. The resource utilization of the FPGA is shown in the Table 3, the utilization increases compared with the master and the uncontrolled slave, this is due to the integration of the controller u. This proves that in a low cost, entry-level FPGA like the SPARTAN-3AN the system are possible to implement by taking in consideration that the utilization of the FPGA exceeds the 60% of the resources. For the MULTI18X18IOs of the system the utilization is 100%, this problem can be avoided by implementing the synchronization scheme in a more powerful FPGA.

Conclusions
A synchronization scheme for systems with heterogeneous chaotic behavior was implemented in an FPGA, this synchronization scheme can synchronize a pair of chaotic systems defined by a different number of pieces, is possible to apply the scheme to UDSs which is a kind of generalization for synchronization of piecewise systems with different quantities of pieces on the master and slave systems, which allows the use in a wide variety of applications in science and engineering. The synchronization scheme gives to the slave system a the dynamics of the master system. The synchronization scheme is designed taking into account the error system between the master and the slave, adding a parameter matrix P that controls the synchronization speed, whenever the parameter is adequate. The controller guarantees a fast synchronization with a minimum error.