High Step-Up Thirteen Level Switched-Capacitor Inverter Topology for HFAC Power System

: This article proposes two new high-frequency, thirteen-level switched capacitor inverter topologies. Compared with the counterpart existing topologies, which were recently published, the switch count, capacitor voltage, and voltage stress on the switch are reduced. In addition, the proposed topologies have inherited merits such as six-time voltage boosting levels and self-balanced capacitor voltages as well. The capacitor ripple voltages and the proposed topology performance are analyzed. The prototype setup is developed for 500W, and the results are veriﬁed. The maximum efﬁciency is approximately equal to 97.5% for simulation. Furthermore, it is approximately equal to 96.1% for experimental, and both are measured at an output power of 500 W. Finally, the characteristics of the proposed topologies are tested under several scenarios, such as modulation index variations and load changes, and the ﬁndings are reported.


Introduction
About 40 years ago, NASA first suggested the use of high-frequency AC (HFAC) power distribution systems for space purposes [1].Many additional applications, such as telecommunications systems, computers, prime movers, high-speed induction motors, aircraft, and ships, find the HFAC power distribution strategy to be a desirable alternative to the traditional DC power distribution approach [2].The primary benefit of using HFAC power distribution is the elimination of two crucial conversion steps from the overall power distribution across different network zones.Following is a summary of the benefits of HFAC power distribution over traditional DC power distribution: (1) it is more effective; (2) it is more dependable; (3) it is better at dissipating heat; (4) it has a higher power density; and (5) it has the possibility of connector-less power transfer.Furthermore, the HFAC power system, which operates at more than the fundamental frequency (50/60 Hz), has offered more advantages, such as reducing the size and weight of the components, which makes them cheaper than the low-frequency AC (LFAC) system.However, the high-frequency system with an electrostatic component is more suitable and easier to replace if it fails.Due to the variety of applications of the HFAC power distributions, different topologies have been proposed.Among these topologies are Mapham's inverter, improved Mapham's inverter, dual asymmetric resonant bridges, double-tuned resonant inverter, tertiary-side resonant inverter, series resonant converter, series-parallel resonant converter, fifth-order resonant converter, double-tuned/series, two-stage resonant, boost/double tuning, double tuned/APWM, and others [1].
Multilevel inverters (MLIs) have become ubiquitous due to the intriguing features they provide.Comparing the MLI output waveforms to the conventional square wave inverters, the harmonic content is significantly reduced by the staircase waveforms.The MLIs can be divided into three categories: cascaded, diode-clamped, and capacitor-clamped (also known as flying capacitors).Diode-clamped MLIs need way more diodes as the level rises, capacitor voltages become out of balance, and the voltage rating for the blocking diodes is high.Voltage imbalance affects capacitor clamped MLIs as well, and when the voltage level rises, more additional storage capacitors are needed, increasing the cost and complexity of the packaging process.The need for separate, isolated DC sources is the cascaded MLI's main flaw.Therefore, many improvements have been made to overcome the disadvantages of these conventional multilevel inverters, resulting in the presentation of new families/structures of multilevel inverters such as impedance source multilevel inverters, hybrid multilevel inverters, transformer-less multilevel inverters, and flying/switched capacitor multilevel inverters with and without boosting ability.
In the past ten years, several types of switched-capacitor multilevel inverters (SCMLIs) have been presented [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19].When compared to traditional inverter topologies (cascaded, neutral-point, and flying capacitor MLIs), SCMLIs typically use fewer components and eliminate the capacitor voltage balancing problem by periodically charging the capacitor to a constant voltage.By charging the capacitors (when connected in parallel to the voltage source) and discharging them to the load (when linked in series with other capacitors and the voltage source), it is therefore possible to achieve a greater number of voltage levels with just a single voltage source and capacitors.In addition, it has more applications, especially in renewable energy sources such as PV and wind generators.As presented in [3], a new hybrid SCMLI topology with a dual input DC-source structure is introduced.This topology needs a higher number of capacitors and a high-voltage stress switch at the load side.In [4,5], thirteen-level switched capacitor multilevel inverter (13L SCMLI) topologies with a voltage gain of six times and 50% reduced voltage stress on the switches are presented but fail to lower the device count.Further, [4] provides the redundant path for level 2. A new 13L SCMLI topology was proposed in [6], and the component is the same as in [4], but the structure is different, and this topology does not provide a redundant path.However, the above topologies use either a higher number of switches or high voltage stress on switches.To resolve this problem, a new SCMLI topology is proposed in [7,8].Another topology can be configured as 9L, 11L, and 13L by changing the modulation strategy with a maximum voltage of 0.66 times v in as proposed in [8].Even though the device count is reduced, the switch voltage is still high.Another single DC-source with a 13L inverter is presented in [9] with 15 switches and a high total standing voltage, but the maximum blocking voltage is half of the output voltage (v o ).The topologies mentioned above are demonstrated for the fundamental frequency system.A new high-frequency multilevel inverter with quasi-soft charging to reduce the inrush current is presented in [10].The proposed topology has the ability to generate high voltage levels, but the maximum output voltage value is equal to the v in, i.e., unity voltage gain.Several other HFAC topologies are proposed in [11][12][13].Two different configurations with reduced switch counts are proposed in [11].Even though this topology generates the 13L inverter, the voltage gain is limited to two times that of the v in .Furthermore, a new high-voltage boost SCMLI topology is presented in [13], where the output voltage is the sum of the capacitor voltage and DC source magnitude.Although this topology uses fewer switches, the diode count is high.From the above discussion, the HFAC multilevel inverters possess high efficiency and compact component sizes.Nonetheless, the number of components is still high, which makes them unsuitable for real-time applications.
From the above discussion, the following issues are not addressed altogether in any topology:

•
The reduction in the voltage stress of the switches and capacitors

•
Less number of the switch count.
As a result, this research focuses on reducing the power components with high voltage gain.The proposed topology is designed to produce a six-times voltage gain with a maximum of eighteen components, and the voltage stress is half of the output voltage.

Comparison of Proposed 13-Level Inverter Structures
Figure 1 shows the three different structures of the proposed thirteen-level inverters.Each structure has two SC units: (i) a front-boost SC unit and (ii) a back-boost SC unit.The back-boost SC unit is already reported in [4], but the front-end boost SC unit is a novel configuration that has three switches with two switch capacitors.

•
The reduction in the voltage stress of the switches and capacitors • Less number of the switch count.
As a result, this research focuses on reducing the power components with high voltage gain.The proposed topology is designed to produce a six-times voltage gain with a maximum of eighteen components, and the voltage stress is half of the output voltage.

Comparison of Proposed 13-Level Inverter Structures
Figure 1 shows the three different structures of the proposed thirteen-level inverters.Each structure has two SC units: (i) a front-boost SC unit and (ii) a back-boost SC unit.The back-boost SC unit is already reported in [4], but the front-end boost SC unit is a novel configuration that has three switches with two switch capacitors.The back-end boost unit has a single capacitor called a multiplier/voltage double cell, which is charged equal to the sum of the vin, vC1, and vC2.The generalized structure of the proposed 13L inverter is shown in Figure 1a, and the voltage multiplier SC unit is illustrated in Figure 1b,c.The proposed topology uses ten switches with an anti-parallel diode; one is RB-IGBT (S2), i.e., a series with a diode.Both the SC units perform the same operation except for the component count.

Principle of Operation Mode
Figure 2 shows the proposed circuit's various modes of positive cycle operation.Each positive mode of operation is discussed as follows.Mode I (+0vin): the vin charges the C1, while the C2 is discharging.The switches S2, S4, S11, S7, S8, and diode D1 will be in the conduction mode, and the output voltage expression is given by Mode II (+vin): the vin shared by both C1 and C2.The switches S2, S4, S11, S7, and S9, and diode D1 are still in the conduction mode, and the output voltage is calculated from (2), where the switches S9 only turned ON will give the output voltage equal to the vin.i.e., if any switch is turned ON means "1" if not "0."When the switch is turned ON, it will be assumed that the corresponding voltage will appear at the load.The back-end boost unit has a single capacitor called a multiplier/voltage double cell, which is charged equal to the sum of the v in , v C1 , and v C2 .The generalized structure of the proposed 13L inverter is shown in Figure 1a, and the voltage multiplier SC unit is illustrated in Figure 1b,c.The proposed topology uses ten switches with an anti-parallel diode; one is RB-IGBT (S 2 ), i.e., a series with a diode.Both the SC units perform the same operation except for the component count.

Principle of Operation Mode
Figure 2 shows the proposed circuit's various modes of positive cycle operation.Each positive mode of operation is discussed as follows.Mode I (+0v in ): the v in charges the C 1, while the C 2 is discharging.The switches S 2 , S 4 , S 11 , S 7 , S 8, and diode D 1 will be in the conduction mode, and the output voltage expression is given by Mode II (+v in ): the v in shared by both C 1 and C 2 .The switches S 2 , S 4 , S 11 , S 7, and S 9, and diode D 1 are still in the conduction mode, and the output voltage is calculated from (2), where the switches S 9 only turned ON will give the output voltage equal to the v in .i.e., if any switch is turned ON means "1" if not "0."When the switch is turned ON, it will be assumed that the corresponding voltage will appear at the load.

C-Charging and D-Discharging
Mode III (+2vin): the vin, C1 is discharging, and C2 gets charged equal to vin.The switches, S1, S2, S4, S11, S7, and S9, will be on conduction, and the output voltage is expressed by From Equation (2), whenever the switch S9 is turned ON the output voltage will be equal to the vin, i.e., vo = 1 × vin.Similarly, if the switch S1 is turned ON, the load voltage is equal to the capacitor voltage vC1 i.e., vo = 1 × vC1, if both S1 and S9 are turned ON the output voltage will be the sum of the vin + vC1.The remaining switches are not turned ON during mode III, so S3 = 0, i.e 0 × vC2, and S6 = 0, S11 = 1, (0 + 1 − 1) × vC3 = 0. Similarly, these Equations from ( 4)-( 7) are obtained as follows: Mode IV (+3vin): both the capacitors, i.e., C1 and C2, are discharging, and C3 charges with the sum of the vin + vC1 + vC2, i.e., vC3 = 3vin.The switches S1, S3, S4, S5, S6, and S9, will be in conduction mode, and the output voltage expression is defined by Mode V (+4vin): the output voltage will be the sum of the C3 voltage and vin, where C3 is started to discharge, and the longest discharging cycle is considered at this level.The output voltage can be expressed as: From Equation (2), whenever the switch S 9 is turned ON the output voltage will be equal to the v in , i.e., v o = 1 × v in .Similarly, if the switch S 1 is turned ON, the load voltage is equal to the capacitor voltage v C1 i.e., v o = 1 × v C1 , if both S 1 and S 9 are turned ON the output voltage will be the sum of the v in + v C1 .The remaining switches are not turned ON during mode III, so S 3 = 0, i.e 0 × v C2, and S 6 = 0, S 11 = 1, (0 + 1 − 1) × v C3 = 0. Similarly, these Equations from (4)-( 7) are obtained as follows: Mode IV (+3v in ): both the capacitors, i.e., C 1 and C 2 , are discharging, and C 3 charges with the sum of the v in + v C1 + v C2, i.e., v C3 = 3v in .The switches S 1, S 3 , S 4 , S 5 , S 6, and S 9, will be in conduction mode, and the output voltage expression is defined by Mode V (+4v in ): the output voltage will be the sum of the C 3 voltage and v in , where C 3 is started to discharge, and the longest discharging cycle is considered at this level.The output voltage can be expressed as: Mode VI and VII (+5v in and +6v in ): both levels can be obtained by summing up the voltages of v in + v C1 + v C3 or v in + v C2 + v C3 for the fifth mode, i.e., +5v in, and the sum of all the voltage sources is added together to reach the maximum voltage of +6v in in the sixth mode, respectively, as given by Similarly, for the negative output, instead of switches S 4 , S 6 , S 9 , and S 11, the switches S 5 , S 7 , S 8 , and S 10 will be turned ON.However, the capacitor, charging path is not changed.

Charging and Discharging Cycles
The charging and discharging cycles of capacitors C 1 , C 2 , and C 3 are shown in Figure 3a.The longest discharging cycles for C 1 and C 2 are equal and smaller than those for C 3 .The discharging period of C 3 is lesser when compared to the thirteen-level topology discussed in [6,7].Further, the pulse generation scheme for the proposed topology is shown in Figure 3b,c.In Figure 3b, the triangular carrier signal is compared with the reference signal to produce the required signal.Further, those signals are processed using the logic Equation ( 8) based on Figure 3c, generating the corresponding switching signal for the particular switch.

(
) ( ) ( ) ( ) ( ) Mode VI and VII (+5vin and +6vin): both levels can be obtained by summing up the voltages of vin + vC1 + vC3 or vin + vC2 + vC3 for the fifth mode, i.e., +5vin, and the sum of all the voltage sources is added together to reach the maximum voltage of +6vin in the sixth mode, respectively, as given by ( ) ( ) ( ) ( ) ( ) Similarly, for the negative output, instead of switches S4, S6, S9, and S11, the switches S5, S7, S8, and S10 will be turned ON.However, the capacitor, charging path is not changed.

Charging and Discharging Cycles
The charging and discharging cycles of capacitors C1, C2, and C3 are shown in Figure 3a.The longest discharging cycles for C1 and C2 are equal and smaller than those for C3.The discharging period of C3 is lesser when compared to the thirteen-level topology discussed in [6,7].Further, the pulse generation scheme for the proposed topology is shown in Figure 3b,c.In Figure 3b, the triangular carrier signal is compared with the reference signal to produce the required signal.Further, those signals are processed using the logic Equation ( 8) based on Figure 3c, generating the corresponding switching signal for the particular switch.
Further, the charging duration of the capacitors is limited to only π/14 rad, thus ensuring rapid recovery after the discharging time.The charging and discharging magnitude of any capacitor can be computed using the longest discharging cycle as given in ( 9) The longest discharging durations of C 1 and C 2 are equal.The discharge starts at t 5 and ends at 9π/14 radians.The discharging magnitude can be calculated using the load current flowing during the above-mentioned period, and it can be given as By substituting the value of the load current and limits, Q C1 , Q C2 and Q C3 can be estimated from The ripple losses and Q influence the capacitor rating.Meanwhile, the value of Q depends on the peak current, power factor, and frequency.The optimum values of the three capacitances are estimated using the following relations.

Frequency Curve
In order to analyze the effect of the frequency on the capacitance, a 100 Ω load operating at a unity power factor and imposing ripple losses of a maximum of 5% on each capacitor are assumed.For an output voltage of 300 V, the value of capacitance at various operating frequencies ranging from 100 Hz to 700 Hz is depicted in Figure 4.It is observed that the value of capacitance decreases with increased frequency.Thus, this topology is compact and suitable for applications such as aviation and space stations.
The magnitude of the load current and its phase difference with respect to voltage influence the ripple losses of the capacitor.For an operating frequency of 'f ' Hz and the current through the capacitance I C , the ripple voltage ∆V Ci can be estimated by The magnitude of the load current and its phase difference with respect to voltage influence the ripple losses of the capacitor.For an operating frequency of 'f' Hz and the current through the capacitance IC, the ripple voltage ΔVCi can be estimated by

Conduction Losses
Let the internal resistance of each switch and diode during conduction be considered as Rsw-on and RD-on respectively.Meanwhile, the internal resistance of capacitance is taken as RCi.
With the above-said notations, the equivalent circuit of the topology while synthesizing +6vin is depicted in Figure 5.The conduction loss per instant while synthesizing the level +6vin can be written as follows: ( ) By substituting the instantaneous loss equation in the average loss, the average conduction loss while synthesizing level +6vin over a period of one cycle can be determined by ( ) The average conduction loss while synthesizing other levels can be estimated similarly, and the total conduction losses can be found by using the following expression.

Conduction Losses
Let the internal resistance of each switch and diode during conduction be considered as R sw-on and R D-on respectively.Meanwhile, the internal resistance of capacitance is taken as R Ci .
With the above-said notations, the equivalent circuit of the topology while synthesizing +6v in is depicted in Figure 5.The conduction loss per instant while synthesizing the level +6v in can be written as follows: By substituting the instantaneous loss equation in the average loss, the average conduction loss while synthesizing level +6v in over a period of one cycle can be determined by The average conduction loss while synthesizing other levels can be estimated similarly, and the total conduction losses can be found by using the following expression.
Processes 2023, 11, x FOR PEER REVIEW 8 of 13 Figure 5. the equivalent circuit for the sixth level (+6vin).

Self-Balancing Ability
Based on the switching diagram shown in Figure 2 and the switching states shown in Table 1, using Kirchhoff's voltage law, the net charging current through the capacitor C1 can be estimated as −3vin/Z over a cycle 2π.During the same period, the net current through the capacitor C2 is observed as −3vin/Z where the Z is the impedance of the current path.Thus, over a cycle, the algebraic sum of the net currents through capacitors C1 and C2 is zero, which ensures the self-voltage balancing ability of the proposed topology.

Self-Balancing Ability
Based on the switching diagram shown in Figure 2 and the switching states shown in Table 1, using Kirchhoff's voltage law, the net charging current through the capacitor C 1 can be estimated as −3v in /Z over a cycle 2π.During the same period, the net current through the capacitor C 2 is observed as −3v in /Z where the Z is the impedance of the current path.Thus, over a cycle, the algebraic sum of the net currents through capacitors C 1 and C 2 is zero, which ensures the self-voltage balancing ability of the proposed topology.

Result and Discussions
The proposed topology is simulated in MATLAB/Simulink to check the performance under various conditions.As shown in Figure 6, the simulation results of the proposed topology under the changed load go from a resistive-inductive to a pure resistive load.It is clear that the output voltage is 300 V for a 50 V input voltage and the load current is 3 A for a resistive load.Further, the output voltage total harmonic distortion (THD) of the simulation is shown in Figure 6b.The scaled-down prototype is developed for 500 W, and various dynamic validations are performed with different cases.The hardware prototype model was developed using the MOSFET IRFP460, 500 V/20 A, the TLP 250 driver circuit, the snapin capacitors ELXG800VNN332MA40S, 50 V/330 µF, and LGU2C471MELA, 160 V/470 µF, and the diode V20PW22, 200 V/20 A. The input voltage is 50 V, fed from 220 V/100 A in the rectifier unit, and the output voltage (v o ) is 300 V.The rheostat and multi-winding inductor are used as loads.The proposed circuit is tested for both fundamental frequencies of 400 Hz and 1 kHz, with a switching frequency of 20 kHz.The conventional level-shifted pulse width modulation scheme is embedded into the Texas launchpad TMS320F28379D for required pulse generation.
Initially, the proposed multilevel inverter is tested for a power factor of 0.85 with a maximum output of 380 VA, and the corresponding output voltage (v o ) and current (i o ) waveforms are shown in Figure 7a.In addition, the capacitors' (C 1 -C 3 ) voltage and current waveforms are shown in both Figure 7a,b.The maximum capacitor current is 10 A~12 A due to the direct charging of the capacitor from the DC source.In reducing or suppressing this inrush current, the small loop inductor is used in the circuit charging, as discussed in [10].Initially, the proposed multilevel inverter is tested for a power factor of 0.85 with a maximum output of 380 VA, and the corresponding output voltage (vo) and current (io) waveforms are shown in Figure 7a.In addition, the capacitors' (C1-C3) voltage and current this inrush current, the small loop inductor is used in the circuit charging, as discussed in [10].In most applications, either the source or the load are not constant, or both can be variables.Further, to validate the performance of the proposed topology by applying step input changes from 40 V to 50 V, the waveforms are captured as shown in Figure 7c,d.The capacitor C1 has step changes from 40 V to 50 V, confirming that the proposed topology is suitable for step input changes.Another important validation is the sudden change in the load value to observe the dynamic performance of the proposed topology.From the unity power factor, a 0.85 lagging power factor is applied at the load, and the corresponding waveforms are shown in Figure 7e.As discussed earlier, the proposed topology is suitable for a high-frequency AC system, and it is mandatory to validate it with other high fundamental frequencies.During experimental validation, 1 kHz is chosen as the fundamental frequency, and the corresponding waveforms are shown in Figure 7f for 1 kHz to 400 Hz with an output RMS current of 1.1 A to 1.7 A, respectively.
Further, the voltages of the capacitors (vC1-vC3) are shown in Figure 6, which proves that the proposed topology can withstand various loading conditions and achieve selfbalancing.In Table 2, a comparison of the proposed topology with recent SCMLI In most applications, either the source or the load are not constant, or both can be variables.Further, to validate the performance of the proposed topology by applying step input changes from 40 V to 50 V, the waveforms are captured as shown in Figure 7c,d.The capacitor C 1 has step changes from 40 V to 50 V, confirming that the proposed topology is suitable for step input changes.Another important validation is the sudden change in the load value to observe the dynamic performance of the proposed topology.From the unity power factor, a 0.85 lagging power factor is applied at the load, and the corresponding waveforms are shown in Figure 7e.As discussed earlier, the proposed topology is suitable for a high-frequency AC system, and it is mandatory to validate it with other high fundamental frequencies.During experimental validation, 1 kHz is chosen as the fundamental frequency, and the corresponding waveforms are shown in Figure 7f for 1 kHz to 400 Hz with an output RMS current of 1.1 A to 1.7 A, respectively.
Further, the voltages of the capacitors (v C1 -v C3 ) are shown in Figure 6, which proves that the proposed topology can withstand various loading conditions and achieve selfbalancing.In Table 2, a comparison of the proposed topology with recent SCMLI topologies is considered.Most of the 13 L inverters in SCMLI are designed for a fundamental frequency of 50 Hz, but those topologies may also operate at high frequencies.The proposed topology has a low switch count with high voltage gain.The topology presented in [11] has a low value for the ratio of total components (TC) versus a number of levels (N Level ), which gives the minimum number of components required per voltage level, but the voltage gain is two times, which is 66% less than the proposed topology.Similarly, the topology presented in [7] has the same total blocking voltage (TBV), and the maximum blocking voltage (MBV) is close to the proposed topology, but the gain is half that of the proposed topology.The proposed topology is superior to the other topologies with a reduction of power components, low voltage stress, and high voltage gain.The efficiency of the proposed inverter is measured in both simulation and experiment, as plotted in Figure 8 using the Fluke meter.The maximum efficiency is ≈97.5% for simulation and ≈96.1% for experimentals, measured at an output power of 500 W. Further calculating the CEC efficiency will give a better operating profile of the inverter.For the proposed inverter, the CEC efficiency of ≈91.60% and ≈89.68% for simulation and experiment, respectively, is calculated based on different percentages of operating power and values shown in Figure 8.The proposed topology produced the expected output voltage.It achieved voltage boosting at the load, which is measured in experimental testing, confirming that the proposed topology's accuracy is high.However, the reliability of the proposed topology depends on the capacitor's life; if any capacitor fails, the output voltage will be reduced.It is worth mentioning that the reliability of all the SCMLI topologies' depends on the capacitor's life.

Conclusions
A novel thirteen-level switched-capacitor inverter topology with reduced power electronics components for a high-frequency AC power system was proposed.The topology configuration is arranged so that the capacitor's voltages are maintained at the rated voltage by applying the switching sequence as per Table 1, and it does not require any additional control circuit.Additionally, the maximum voltage across the switch is half of the output voltage, v o .The experimental results confirmed that the proposed topology can provide six-time voltage boosting with a single DC source, and the same is tested for 500 W at an efficiency of 96.0%.Since the proposed topology has low voltage stress and high voltage gains and is also based on the above experimental results and discussion, it is suitable for high-frequency AC power system applications such as space, aircraft, telecommunications, etc.

Figure 2 .
Figure 2. Proposed 13L inverter (a-g) Various operation cycle during positive half cycle and zero state.

Figure 2 .
Figure 2. Proposed 13L inverter (a-g) Various operation cycle during positive half cycle and zero state.C-Charging and D-Discharging Mode III (+2v in ): the v in, C 1 is discharging, and C 2 gets charged equal to v in .The switches, S 1, S 2 , S 4 , S 11 , S 7, and S 9, will be on conduction, and the output voltage is expressed by

Figure 3 .
Figure 3. Pulse generation scheme (a) Typical 13L waveform with Capacitor charging chart, (b) Level shifted modulation scheme, and (c) comparison of reference and triangular carrier signals.Figure 3. Pulse generation scheme (a) Typical 13L waveform with Capacitor charging chart, (b) Level shifted modulation scheme, and (c) comparison of reference and triangular carrier signals.

Figure 3 .
Figure 3. Pulse generation scheme (a) Typical 13L waveform with Capacitor charging chart, (b) Level shifted modulation scheme, and (c) comparison of reference and triangular carrier signals.Figure 3. Pulse generation scheme (a) Typical 13L waveform with Capacitor charging chart, (b) Level shifted modulation scheme, and (c) comparison of reference and triangular carrier signals.

Figure 5 .
Figure 5.The equivalent circuit for the sixth level (+6v in ).

Figure 6 .
Figure 6.Simulation results of proposed thirteen level inverter (a) load variation with output voltage, current and capacitor voltage, and (b) FFT Analysis.

Figure 6 .
Figure 6.Simulation results of proposed thirteen level inverter (a) load variation with output voltage, current and capacitor voltage, and (b) FFT Analysis.

Figure 7 .
Figure 7. Experimental results (a) vo, io, vC1 and iC1, (b) capacitors voltage and current, (c) step input change from 40 V to 50 V (d) for R = 100 Ω + 25 mH (e) load changes from resistive to inductive load vo, io, vC1 and vC3 and (f) output frequency changes from 1 kHz to 400 Hz.

Figure 7 .
Figure 7. Experimental results (a) v o , i o , v C1 and i C1 , (b) capacitors voltage and current, (c) step input change from 40 V to 50 V (d) for R = 100 Ω + 25 mH (e) load changes from resistive to inductive load v o , i o , v C1 and v C3 and (f) output frequency changes from 1 kHz to 400 Hz.

Table 2 .
Comparison of Proposed 13L SCMLI with Recent Other Topologies.Levels /N Source /N Switches /N Driver /N Diode /N Capac -number of levels, source, switches, driver, diode, and capacitors, TBVpu-Total blocking voltage per unit, MBVpu-Maximum blocking voltage per unit, TC-Total Components. N