Sub-THz Small-Signal Equivalent Circuit Model and Parameter Extraction for 3 nm Gate-All-Around Nanosheet Transistor

: This paper presents a novel RF small-signal equivalent circuit model and parameter extraction for 3 nm nanosheet gate-all-around ﬁeld effect transistor (GAAFET). The extrinsic parasitic effect induced by ground-signal-ground (GSG) layout is evaluated by 3D full-wave electromagnetic simulation, and an improved ﬁve-step analytical parameter extraction method is proposed for such extrinsic GSG layout. The model parameters for the intrinsic device are analytically determined with the help of nonlinear rational function ﬁtting. The accuracy of the proposed extraction method was conﬁrmed via comparisons between device simulator and electromagnetic simulator with frequency responses up to 300 GHz. Excellent agreement is obtained between the simulated and modeled S-parameters, and the calculated error is lower than 2.689% for the extrinsic layout, and 0.897% for the intrinsic device in the whole frequency range among multi-bias points.


Introduction
As the feature size continues to shrink, traditional planar MOSFETs can no longer meet the scaling rules of Moore's law, suffering from the serious short channel effects [1]. Multi-gate structures such as FinFET have been applied to industrial manufacturing since the 22 nm technology node [2]. When entering to sub 3 nm node, the gate-all-around (GAA) nanosheet architecture has become a convincing candidate beyond FinFET [3]. When entering millimeter-wave even T-Hz band, the transistors will experience severe parasitic effects [4]. An accurate physically oriented circuit model and parameter extraction technique for a GAA nanosheet transistor are very important to evaluate the fabrication process, optimize the device structure and help in circuit design [5][6][7].
The accurate de-embedding is the first step to model the high-frequency behavior and extract the model parameters. Generally, the OPEN and SHORT method has been widely adopted to strip the parasitism of the test pad and interconnect line over the low frequency range [8]. However, the efficiency and accuracy of the OPEN-SHORT de-embedding method will degrade seriously when the frequency is larger than 40 GHz. Thus, some improved de-embedding techniques such as the OPEN-SHORT-THRU method and multistep de-embedding structures [9,10]. For higher operation frequency such as mmW or T-Hz range, 3D full-wave electromagnetic field simulation has also been proposed to model the extrinsic parasitism coupling and extract the PAD parasitism, which has been successfully applied in III-V devices and planar MOSFET [10][11][12]. However, few reports document electromagnetic simulation to extract the extrinsic parasitic effects of FinFET or GAAFET, because the parasitic effects are more diversified suffering the complex three-dimensional ring gate, multi-fingered electrode and substrate contact ring structure.
Over the last three decades, several research studies have focused on the parameter extraction for the MOSFET small-signal equivalent circuit model [13][14][15][16]. Earlier works generally rely on numerical optimization to match the simulated curves with the measurement data [14]. However, the extracted parameters are often sensitive to the initial-guess values, and some non-physical results may be obtained such as a negative capacitance or resistance. To overcome this problem, another analytical or semianalytical methods are proposed [13,15,16]. For example, all the signal model parameters of FinFET are analytically extracted through S-parameter under different bias conditions, and the high accuracy is obtained over the 50 GHz frequency range [16]. The substrate R sub including the bulk effect is extracted by shorting the source and drain, which improves the accuracy of Y 22 at the high frequency range [13]. The gate parasitic resistance R g , which is important for the frequency characteristics, is ignored in several works [17].
In this paper, a novel analytical parameter extraction method is established for RF small-signal equivalent circuit of GAAFET at 3 nm node. The extrinsic parasitic parameters of the 3D test layout are extracted and compared to HFSS 3D full-wave electromagnetic simulation. The 3 nm GAAFET was built and simulated in Sentaurus TCAD to extract intrinsic parasitic parameters. Excellent agreement between the modeled and simulated data illustrates the improved modeling accuracy.

Device Structure and Equivalent Circuit Model
The 3D schematic view of the device structure for the vertically stacked GAA NSFET is shown in Figure 1a-c, depicting the 2D cross-section views along the channel and gate direction. The physical gate length L g is 15 nm. Three nanosheets with ellipse cross-section are vertically stacked. The width and height of each nanosheet are separately 20 nm and 5 nm. The gate oxide is composed of SiO 2 and HfO 2 and the equivalent oxide thickness is 0.68 nm. The spacer is composed of 4.2 nm SiO 2 and 1.6 nm HfO 2 . The doping of the channel and source/drain are 1 × 10 15 cm −3 and 1 × 10 21 cm −3 , respectively. TiN with aa work function of 4.37 eV is adopted as the gate metal. Figure 2 shows the adopted two-finger coplanar GSG PAD layout to de-embed the impact of the test structure and the compounding equivalent circuit model. Each parasitic parameter from the layout is also marked out. Here, (C gde , G gde ), (C gse , G gse ) and (C dse , G dse ) are the interconnection parasitic capacitance-conductance pairs between PAD electrodes. (R ge , L ge ), (R de , L de ) and (R se , L se ) represent the parasitic resistance-inductance pair of PAD electrodes. (C gdp , G gdp ), (C gsp , G gsp ) and (C dsp , G dsp ) are interconnection capacitance-conductance pairs between PAD electrodes.
Processes 2022, 10, x FOR PEER REVIEW 2 of 12 document electromagnetic simulation to extract the extrinsic parasitic effects of FinFET or GAAFET, because the parasitic effects are more diversified suffering the complex threedimensional ring gate, multi-fingered electrode and substrate contact ring structure. Over the last three decades, several research studies have focused on the parameter extraction for the MOSFET small-signal equivalent circuit model [13][14][15][16]. Earlier works generally rely on numerical optimization to match the simulated curves with the measurement data [14]. However, the extracted parameters are often sensitive to the initialguess values, and some non-physical results may be obtained such as a negative capacitance or resistance. To overcome this problem, another analytical or semianalytical methods are proposed [13,15,16]. For example, all the signal model parameters of FinFET are analytically extracted through S-parameter under different bias conditions, and the high accuracy is obtained over the 50 GHz frequency range [16]. The substrate Rsub including the bulk effect is extracted by shorting the source and drain, which improves the accuracy of Y22 at the high frequency range [13]. The gate parasitic resistance Rg, which is important for the frequency characteristics, is ignored in several works [17].
In this paper, a novel analytical parameter extraction method is established for RF small-signal equivalent circuit of GAAFET at 3 nm node. The extrinsic parasitic parameters of the 3D test layout are extracted and compared to HFSS 3D full-wave electromagnetic simulation. The 3 nm GAAFET was built and simulated in Sentaurus TCAD to extract intrinsic parasitic parameters. Excellent agreement between the modeled and simulated data illustrates the improved modeling accuracy.

Device Structure and Equivalent Circuit Model
The 3D schematic view of the device structure for the vertically stacked GAA NSFET is shown in Figure 1a-c, depicting the 2D cross-section views along the channel and gate direction. The physical gate length Lg is 15 nm. Three nanosheets with ellipse cross-section are vertically stacked. The width and height of each nanosheet are separately 20 nm and 5 nm. The gate oxide is composed of SiO2 and HfO2 and the equivalent oxide thickness is 0.68 nm. The spacer is composed of 4.2 nm SiO2 and 1.6 nm HfO2. The doping of the channel and source/drain are 1 × 10 15 cm −3 and 1 × 10 21 cm −3 , respectively. TiN with aa work function of 4.37 eV is adopted as the gate metal. Figure 2 shows the adopted two-finger coplanar GSG PAD layout to de-embed the impact of the test structure and the compounding equivalent circuit model. Each parasitic parameter from the layout is also marked out. Here, (Cgde, Ggde), (Cgse, Ggse) and (Cdse, Gdse) are the interconnection parasitic capacitance-conductance pairs between PAD electrodes. (Rge, Lge), (Rde, Lde) and (Rse, Lse) represent the parasitic resistance-inductance pair of PAD electrodes. (Cgdp, Ggdp), (Cgsp, Ggsp) and (Cdsp, Gdsp) are interconnection capacitance-conductance pairs between PAD electrodes.    (a) (b) Figure 2. (a) The adopted two-finger coplanar GSG PAD layout and (b) the equivalent circuit of GSG PAD layout. Figure 3 shows the proposed improved small-signal equivalent circuit model of intrinsic GAAFET. Cgdo and Cgso are the capacitance between the gate and source/drain. Rg, Rs, Rd and Rsub are separately the resistance of the gate, source, drain and substrate. Cjd is the capacitance between the drain and substrate. Cgsi and Cgdi are the capacitance between the source/drain overlap and gate region. Rgsi and Rgdi are the resistance of the source and drain overlap region. Rds and Lds are the channel's resistance and inductance. τm characterizes the transmission delay between the source and drain. Csdx characterizes the DIBL effect, and gm is the transconductance.

Extrinsic Layout Test Structures and Parameter Extraction Algorithm
As shown in Figure 2b, 18 parasitic elements are contained in the extrinsic GSG layout parasitic circuit. It is unrealistic to extract many parasitic parameters by directly fitting measured or simulated S (or Y)-parameters. Thus, a kind of multi-step extraction method has been proposed [10]. However, because the parasitic parameters are sensitive to the layout structure, two kinds of short structures may not match expectations when performing the fourth and fifth steps. Here, we propose an improved multi-step test structure method to better characterize the circuit performance.
First, similar to the conventional method in [18,19], the gate and drain electrodes are removed, and the PAD of the source, gate and drain is simulated to extract the coupling parasitic capacitance and conductance between PADs. The layout and corresponding subcircuit model are shown in Figure 4a. The Y-matrix of such PADs structure is as follows:  Figure 2. (a) The adopted two-finger coplanar GSG PAD layout and (b) the equivalent circuit of GSG PAD layout. Figure 3 shows the proposed improved small-signal equivalent circuit model of intrinsic GAAFET. C gdo and C gso are the capacitance between the gate and source/drain. R g , R s , R d and R sub are separately the resistance of the gate, source, drain and substrate. C jd is the capacitance between the drain and substrate. C gsi and C gdi are the capacitance between the source/drain overlap and gate region. R gsi and R gdi are the resistance of the source and drain overlap region. R ds and L ds are the channel's resistance and inductance. τ m characterizes the transmission delay between the source and drain. C sdx characterizes the DIBL effect, and g m is the transconductance. (a) (b) Figure 2. (a) The adopted two-finger coplanar GSG PAD layout and (b) the equivalent circuit o GSG PAD layout. Figure 3 shows the proposed improved small-signal equivalent circuit model of in trinsic GAAFET. Cgdo and Cgso are the capacitance between the gate and source/drain. R Rs, Rd and Rsub are separately the resistance of the gate, source, drain and substrate. Cjd i the capacitance between the drain and substrate. Cgsi and Cgdi are the capacitance between the source/drain overlap and gate region. Rgsi and Rgdi are the resistance of the source and drain overlap region. Rds and Lds are the channel's resistance and inductance. τm character izes the transmission delay between the source and drain. Csdx characterizes the DIBL ef fect, and gm is the transconductance.

Extrinsic Layout Test Structures and Parameter Extraction Algorithm
As shown in Figure 2b, 18 parasitic elements are contained in the extrinsic GSG lay out parasitic circuit. It is unrealistic to extract many parasitic parameters by directly fitting measured or simulated S (or Y)-parameters. Thus, a kind of multi-step extraction method has been proposed [10]. However, because the parasitic parameters are sensitive to th layout structure, two kinds of short structures may not match expectations when perform ing the fourth and fifth steps. Here, we propose an improved multi-step test structur method to better characterize the circuit performance.
First, similar to the conventional method in [18,19], the gate and drain electrodes ar removed, and the PAD of the source, gate and drain is simulated to extract the couplin parasitic capacitance and conductance between PADs. The layout and corresponding sub circuit model are shown in Figure 4a. The Y-matrix of such PADs structure is as follows: Thus, Ggdp, Ggsp and Gdsp can be obtained from the real part of Ypad,12, Ypad,11 and Ypad,2 and Cgdp, Cgsp and Cdsp are the slope of the imaginary part of Ypad,12, Ypad,11 and Ypad, 22 verse ω, as depicted below.

Extrinsic Layout Test Structures and Parameter Extraction Algorithm
As shown in Figure 2b, 18 parasitic elements are contained in the extrinsic GSG layout parasitic circuit. It is unrealistic to extract many parasitic parameters by directly fitting measured or simulated S (or Y)-parameters. Thus, a kind of multi-step extraction method has been proposed [10]. However, because the parasitic parameters are sensitive to the layout structure, two kinds of short structures may not match expectations when performing the fourth and fifth steps. Here, we propose an improved multi-step test structure method to better characterize the circuit performance.
First, similar to the conventional method in [18,19], the gate and drain electrodes are removed, and the PAD of the source, gate and drain is simulated to extract the coupling parasitic capacitance and conductance between PADs. The layout and corresponding subcircuit model are shown in Figure 4a. The Y-matrix of such PADs structure is as follows: 4c. After de-embedding the THRU1_PAD from THRU1, the admittance matrix of the gate electrode YGATE = YTHU1 − YTHU1_PAD is calculated as: Thus, similar to the extraction of Ggdp, Ggsp, Gdsp, Cgdp, Cgsp and Cdsp in Equations (2)-(7), the gate electrode resistance and inductance Rge and Lge can also be easily obtained. Thus, G gdp , G gsp and G dsp can be obtained from the real part of Y pad,12 , Y pad,11 and Y pad,22 , and C gdp , C gsp and C dsp are the slope of the imaginary part of Y pad,12 , Y pad,11 and Y pad, 22 verses ω, as depicted below. 12 (2) In the second step, the THRU1 structure is introduced to extract R ge and L ge . The lower half of the drain electrode is removed and the upper half is mirrored to the lower half. Then, the gate electrode is extended to connect the lower PAD, as shown in Figure 4b. Based on such THUI1 structure, the THRU1_PAD structure will be obtained when the gate electrode is removed and the corresponding sub-circuit is depicted, as seen in Figure 4c. After de-embedding the THRU1_PAD from THRU1, the admittance matrix of the gate electrode Y GATE = Y THU1 − Y THU1_PAD is calculated as: Thus, similar to the extraction of G gdp , G gsp , G dsp , C gdp , C gsp and C dsp in Equations (2)- (7), the gate electrode resistance and inductance R ge and L ge can also be easily obtained.
In the third step, a kind of THRU2 structure is introduced. The upper half of the gate electrode is removed, and the lower half is mirrored to the upper half, then the drain electrode is extended to connect to the upper and lower PAD, as shown in Figure 4d. The corresponding THRU2_PAD structure is depicted in Figure 4e by removing the drain electrode in the THUR2 structure. The corresponding sub-circuits are separately depicted in Figure 4d,e. Similarly, the admittance matrix of the drain electrode Y DRAIN = Y THU2 − Y THU2_PAD is written as: So far, the drain electrode resistance R de and inductance L de are obtained.
In the fourth step, a kind of THRU1_SHORT is structured to extract R se and L se . The gate electrode is connected to the source PAD based on the THRU1 structure, as shown in Figure 4f. The Y-matrix of the source electrode Y SOURCE is calculated as: Thus, the source electrode resistance R se and inductance L se can be easily obtained.
In the fifth step, the entire layout test structure, as shown in Figure 2a, is simulated to obtain the remaining inter-electrode parasitic capacitance and inductance pairs (C gde , G gde ), (C gse , G gse ) and (C dse , G dse ). The corresponding circuit is shown in Figure 2b. The parasitic network on the electrodes can be expressed as: The Y-matrix of the parasitic network between the electrodes can be expressed as: Similar to extracting the parameters of the PAD structure, all parasitic capacitance and inductance pairs between the electrodes can be extracted here. HFSS simulation is then performed to obtain the high-frequency characteristics of the designed test structure in Figures 2 and 4, and the frequency range is up to 300GHz. Then, all the model parameters related with GSG PAD can be extracted based on Equations (1)-(12).

Improved Extraction Method of Intrinsic Device Equivalent Circuit
As depicted in Figure 3a, the equivalent circuit of the intrinsic device includes 16 circuit elements. In our previous work [5], a two-step method has been proposed to extract intrinsic parameters based on the ON-state and OFF-state. However, gate resistance R g is ignored, which is very important for the impedance matching and thermal noise of the gate metal [17]. Here, an improved extraction method including gate resistance R g for intrinsic devices is proposed in this work. When the device is biased at the OFF-state (V gs ≤ 0, V ds = 0), the equivalent circuit of the intrinsic device will be reduced as shown in Figure 3b. Thus, Y-parameters Y o 11 of the OFF-state equivalent circuit in Figure 3b can be calculated as follows: The coefficients N ij and M ij are functions of model parameters in Figure 3b, where the coefficients N 10 -N 50 in the numerator are shown as follows: Since the source and drain are symmetrical, there exists C gdo = C gso and R s = R d . Thus, the bias-independent parameters (C gso , C gdo , R s , R d , R g , C jd , R sub ) can be directly obtained by grouping Equations (18)- (22), as shown below: After removing the bias-independent parameter in Figure 3b, the Y-parameter of the equivalent circuit within the redline in Figure 3a can be obtained as: Processes 2022, 10, 1198 Then, the bias-dependent parameters (C gsi , C gdi , R gsi , R gdi , τ m , g m , R ds , L ds , C sdx ) can be directly obtained by grouping Equations (28)-(34), as shown below: So far, the model parameters for the intrinsic circuit have been analytically extracted, once the coefficients N 10 -N 50 and K 10 -K 90 are accurate.

Validation of Extraction Method for Extrinsic Layout
After accurately extracting the parasitic parameters of the extrinsic GSG test layout, the full-wave EM simulation in HFSS is compared with the ADS simulation using the equivalent circuit. The accuracy of the proposed improved extrinsic layout extraction method is confirmed over 10 MHz-300 GHz. Figure 5 shows the comparison between simulated and modeled S-parameters for the standard OPEN test structure in Figure 2a. The S-parameters obtained by the full-wave EM simulation show an excellent agreement with the extracted equivalent circuit over a wide bandwidth, which confirms the accuracy of the proposed improved extraction method.
So far, the model parameters for the intrinsic circuit have been analytically extracted, once the coefficients N10-N50 and K10-K90 are accurate.

Validation of Extraction Method for Extrinsic Layout
After accurately extracting the parasitic parameters of the extrinsic GSG test layout, the full-wave EM simulation in HFSS is compared with the ADS simulation using the equivalent circuit. The accuracy of the proposed improved extrinsic layout extraction method is confirmed over 10 MHz-300 GHz. Figure 5 shows the comparison between simulated and modeled S-parameters for the standard OPEN test structure in Figure 2a. The S-parameters obtained by the full-wave EM simulation show an excellent agreement with the extracted equivalent circuit over a wide bandwidth, which confirms the accuracy of the proposed improved extraction method.  Figure 6a shows the extracted inter-electrode and inter-pad capacitors. Consistent with [18,19], Cgdp and Cgde are much smaller than the other capacitances because of the large space and small co-planar capacitance between the gate and drain electrode [20,21]. Moreover, Cgse and Cdse decrease with increasing frequency, due to the neglection of the inductance of the source, gate and drain PADs [22]. Figure 6b shows the variation of Ggsp, Gdsp, Ggdp, Ggse, Gdse and Ggde as functions of frequencies. For the substrate capacitance and inductance, there is a relation of G (ω)/C (ω) = ωtanδ (where δ represent dielectric constant), and the inductances are basically proportional to its corresponding capacitances [23]. The parasitic resistance-inductance pairs (Rge, Lge), (Rde, Lde) and (Rse, Lse) between the source and gate electrodes are shown in Figure 7, respectively. Due to the current crowding phenomenon and the skin effect, the source resistance Rse rises rapidly as the frequency enters the mmW band. Due to the skin effect, Lge and Lde gradually decrease as the frequency increases. The conductor inductance of the microstrip line is inversely proportional to its width, while the width of the source electrode is wider than the other electrodes, which leads to a smaller source electrode inductance Lse.  Figure 6a shows the extracted inter-electrode and inter-pad capacitors. Consistent with [18,19], C gdp and C gde are much smaller than the other capacitances because of the large space and small co-planar capacitance between the gate and drain electrode [20,21]. Moreover, C gse and C dse decrease with increasing frequency, due to the neglection of the inductance of the source, gate and drain PADs [22]. Figure 6b shows the variation of G gsp , G dsp , G gdp , G gse , G dse and G gde as functions of frequencies. For the substrate capacitance and inductance, there is a relation of G (ω)/C (ω) = ωtanδ (where δ represent dielectric constant), and the inductances are basically proportional to its corresponding capacitances [23]. The parasitic resistance-inductance pairs (R ge , L ge ), (R de , L de ) and (R se , L se ) between the source and gate electrodes are shown in Figure 7, respectively. Due to the current crowding phenomenon and the skin effect, the source resistance R se rises rapidly as the frequency enters the mmW band. Due to the skin effect, L ge and L de gradually decrease as the frequency increases. The conductor inductance of the microstrip line is inversely proportional to its

Validation of Extraction Method for Intrinsic Device
Sentaurus TCAD is adopted to obtain the high-frequency characteristics of intrinsic NSFET under the ON-state. The critical physical model used in the device simulation includes the drift-diffusion model, density-gradient model, Philips unified mobility model, interface mobility degradation model, velocity saturation and doping-dependent SRH recombination. The simulated high-frequency S-parameters are used to verify the accuracy and feasibility of the small-signal circuit and parameter extraction method. With the help of mathematical fitting software such as MATLAB, the lowest order terms Ni0 and Ki0 in Equations (12)- (16) and (22)

Validation of Extraction Method for Intrinsic Device
Sentaurus TCAD is adopted to obtain the high-frequency characteristics of intrin NSFET under the ON-state. The critical physical model used in the device simulation cludes the drift-diffusion model, density-gradient model, Philips unified mobility mod interface mobility degradation model, velocity saturation and doping-dependent SRH combination. The simulated high-frequency S-parameters are used to verify the accura and feasibility of the small-signal circuit and parameter extraction method. With the he of mathematical fitting software such as MATLAB, the lowest order terms Ni0 and Ki0 Equations (12)- (16) and (22)

Validation of Extraction Method for Intrinsic Device
Sentaurus TCAD is adopted to obtain the high-frequency characteristics of intrinsic NSFET under the ON-state. The critical physical model used in the device simulation includes the drift-diffusion model, density-gradient model, Philips unified mobility model, interface mobility degradation model, velocity saturation and doping-dependent SRH recombination. The simulated high-frequency S-parameters are used to verify the accuracy and feasibility of the small-signal circuit and parameter extraction method. With the help of mathematical fitting software such as MATLAB, the lowest order terms N i0 and K i0 in Equations (12)- (16) and (22)-(29) can be accurately determined. As for the 3 nm nanosheet transistor in the proposed OFF-state bias (V gs = −0.65 V, V ds = 0 V), the fitting results of N i0 and the corresponding confidence interval are shown in Table 1. The narrow confidence interval verifies the accuracy of N i0 . According to Equations (17)−(21), the bias-independent parameters under such OFF-state are separately extracted as: C gso = C gdo = 1.466 × 10 −17 F, R s = R d = 837.16 Ω, R g = 17.29 Ω, C jd = 9.9 × 10 −19 F and R sub = 9943.3 Ω. The comparison between the TCAD device simulation in Sentaurus and equivalent circuit simulation in ADS is shown in Figure 8, from which a good agreement exists over 10 MHz-300 GHz.
Similar to the above OFF-state, the coefficients K i0 for the ON-state can also be accurately determined. For example, the fitting results for the linear region (V gs = 0.65 V, V ds = 0.05 V) are shown in Table 2. The reliability of K i0 can also be proved by the corresponding narrow confidence interval. According to Equations (30)-(34), the bias-independent intrinsic model parameters under such ON-state are calculated as: C gsi = 2.968 × 10 −17 F, C gdi = 2.77 × 10 −17 F, R gsi = 916.33 Ω, R gdi = 1331.3 Ω, τ m = 32.2 fs, g m =2.71 × 10 −5 S, C sdx = 1.90 × 10 −18 F and R ds = 2357 Ω. S-parameter comparison between the Sentaurus device simulation and ADS Processes 2022, 10, 1198 9 of 12 equivalent circuit simulation under a linear region (V gs = 0.65 V, V ds = 0.05 V) and saturation region (V gs = 0.65 V, V ds = 0.65 V) is depicted in Figure 9. Excellent agreement is obtained over the entire frequency. The maximum error in the linear region and saturation region are 0.2504% and 2.689%, which confirms the accuracy of the proposed extraction method.  Similar to the above OFF-state, the coefficients Ki0 for the ON-state can also be ac rately determined. For example, the fitting results for the linear region (Vgs = 0.65 V, V 0.05 V) are shown in Table 2. The reliability of Ki0 can also be proved by the correspond narrow confidence interval. According to Equations (30)-(34), the bias-independent trinsic model parameters under such ON-state are calculated as: Cgsi = 2.968 × 10 −17 F, Cg 2.77 × 10 −17 F, Rgsi = 916.33 Ω, Rgdi = 1331.3 Ω, τm = 32.2 fs, gm=2.71 × 10 −5 S, Csdx = 1.90 × 1 F and Rds = 2357 Ω. S-parameter comparison between the Sentaurus device simulation a ADS equivalent circuit simulation under a linear region (Vgs = 0.65 V, Vds = 0.05 V) a saturation region (Vgs = 0.65 V, Vds = 0.65 V) is depicted in Figure 9. Excellent agreemen obtained over the entire frequency. The maximum error in the linear region and saturat region are 0.2504% and 2.689%, which confirms the accuracy of the proposed extract method.    Figure 10a shows the comparison between simulated and modeled maximum available gain (MAG), maximum stable gain (MSG), Mason's unilateral gain (MUG), unilateral figure of merit (Uf ) and H 21 . As expected, ADS-modeled data agree well with the Sentaurus simulated one over the whole frequency range. The extracted cutoff frequency F t and maximum oscillation frequency F max under different biases shown in Figure 10b. As expected, F t and F max increase first and then decrease with increasing V gs . Excellent agreement between the simulated and modeled RF figures of merit (FOM) proves that the extracted small-signal equivalent circuit can effectively predict the RF response of the device up to 300 GHz. Subsequently, the bias dependence of intrinsic model parameters is discussed. Figure 11 shows the variation of extracted critical model parameters as a function of V gs . C gsi /C gdi gradually increases as V gs increases, and then becomes flat when V gs is large enough, which is consistent with the typical C-V curve of MOS capacitor.
Moreover, C gdi is smaller than C gsi under the same V ds , and the difference between two capacitances increases with increasing V ds , especially in the saturation region, which is the result of the thinner depletion layer near the drain region. g m sharply increases when the transistor operates in the saturation region, and the increasing trend slows down once the transistor enters the linear region, due to the carrier velocity saturation effect under high electric field. τ m is found to first increase and then decrease with increasing V gs . Similar to the planar MOSFET, τ m can be expressed as: obtained over the entire frequency. The maximum error in the linear region and saturation region are 0.2504% and 2.689%, which confirms the accuracy of the proposed extraction method.   Figure 10a shows the comparison between simulated and modeled maximum available gain (MAG), maximum stable gain (MSG), Mason's unilateral gain (MUG), unilateral figure of merit (Uf) and H21. As expected, ADS-modeled data agree well with the Sentaurus simulated one over the whole frequency range. The extracted cutoff frequency Ft and maximum oscillation frequency Fmax under different biases shown in Figure 10b. As expected, Ft and Fmax increase first and then decrease with increasing Vgs. Excellent agreement between the simulated and modeled RF figures of merit (FOM) proves that the extracted small-signal equivalent circuit can effectively predict the RF response of the device up to 300 GHz. Subsequently, the bias dependence of intrinsic model parameters is discussed. Figure 11 shows the variation of extracted critical model parameters as a function of Vgs. Cgsi/Cgdi gradually increases as Vgs increases, and then becomes flat when Vgs is large enough, which is consistent with the typical C-V curve of MOS capacitor. Moreover, Cgdi is smaller than Cgsi under the same Vds, and the difference between two capacitances increases with increasing Vds, especially in the saturation region, which is the result of the thinner depletion layer near the drain region. gm sharply increases when the transistor operates in the saturation region, and the increasing trend slows down once the transistor enters the linear region, due to the carrier velocity saturation effect under high electric field. τm is found to first increase and then decrease with increasing Vgs. Similar to the planar MOSFET, τm can be expressed as: In the above formula, the mobility µn decreases with increasing Vgs. These two items in the denominator contribute a competitive relationship, which causes τm to increase first and then decrease.  Figure 10a shows the comparison between simulated and modeled maximum available gain (MAG), maximum stable gain (MSG), Mason's unilateral gain (MUG), unilateral figure of merit (Uf) and H21. As expected, ADS-modeled data agree well with the Sentaurus simulated one over the whole frequency range. The extracted cutoff frequency Ft and maximum oscillation frequency Fmax under different biases shown in Figure 10b. As expected, Ft and Fmax increase first and then decrease with increasing Vgs. Excellent agreement between the simulated and modeled RF figures of merit (FOM) proves that the extracted small-signal equivalent circuit can effectively predict the RF response of the device up to 300 GHz. Subsequently, the bias dependence of intrinsic model parameters is discussed. Figure 11 shows the variation of extracted critical model parameters as a function of Vgs. Cgsi/Cgdi gradually increases as Vgs increases, and then becomes flat when Vgs is large enough, which is consistent with the typical C-V curve of MOS capacitor. Moreover, Cgdi is smaller than Cgsi under the same Vds, and the difference between two capacitances increases with increasing Vds, especially in the saturation region, which is the result of the thinner depletion layer near the drain region. gm sharply increases when the transistor operates in the saturation region, and the increasing trend slows down once the transistor enters the linear region, due to the carrier velocity saturation effect under high electric field. τm is found to first increase and then decrease with increasing Vgs. Similar to the planar MOSFET, τm can be expressed as: In the above formula, the mobility µn decreases with increasing Vgs. These two items in the denominator contribute a competitive relationship, which causes τm to increase first and then decrease.

Conclusions
In this paper, an improved RF small-signal equivalent circuit model and corresponding parameter extraction method is proposed for GAAFET at 3 nm node. The equivalent circuit contains both the extrinsic GSG test layout and intrinsic device. The parasitic parameters of the GSG test layout are first obtained by an improved five-step method. The model parameters of the intrinsic GAAFET are analytically extracted with the help of nonlinear rational function fitting. The validity of the proposed small-signal equivalent circuit model and the corresponding extraction method have been demonstrated, through excellent agreement between TCAD/HFSS 3D full-wave simulation and equivalent circuit frequency response up to 300 GHz. The error is lower than 2.69% for intrinsic devices, and lower than 0.89% for the extrinsic GSG test layout in the whole frequency range. Moreover, an obvious influence of WFV is found on the variation of critical model parameters, especially under the condition of smaller gate grain size. Data Availability Statement: The datasets generated during and/or analysis during the current study are available from the corresponding author on reasonable request.

Conflicts of Interest:
The authors declare no conflict of interest. In the above formula, the mobility µ n decreases with increasing V gs . These two items in the denominator contribute a competitive relationship, which causes τ m to increase first and then decrease.

Conclusions
In this paper, an improved RF small-signal equivalent circuit model and corresponding parameter extraction method is proposed for GAAFET at 3 nm node. The equivalent circuit contains both the extrinsic GSG test layout and intrinsic device. The parasitic parameters of the GSG test layout are first obtained by an improved five-step method. The model parameters of the intrinsic GAAFET are analytically extracted with the help of nonlinear rational function fitting. The validity of the proposed small-signal equivalent circuit model and the corresponding extraction method have been demonstrated, through excellent agreement between TCAD/HFSS 3D full-wave simulation and equivalent circuit frequency response up to 300 GHz. The error is lower than 2.69% for intrinsic devices, and lower than 0.89% for the extrinsic GSG test layout in the whole frequency range. Moreover, an obvious influence of WFV is found on the variation of critical model parameters, especially under the condition of smaller gate grain size. Data Availability Statement: The datasets generated during and/or analysis during the current study are available from the corresponding author on reasonable request.

Conflicts of Interest:
The authors declare no conflict of interest.