An Evolutionary Algorithm-Based PWM Strategy for a Hybrid Power Converter

In the past years, the interest in direct current to direct current converters has increased because of their application in renewable energy systems. Consequently, the research community is working on improving its efficiency in providing the required voltage to electronic devices with the lowest input current ripple. Recently, a hybrid converter which combines the boost and the Cuk converter in an interleaved manner has been introduced. The converter has the advantage of providing a relatively low input current ripple by a former strategy. However, it has been proposed to operate with dependent duty cycles, limiting its capacity to further decrease the input current ripple. Independent duty cycles can significantly reduce the input current ripple if the same voltage gain is achieved by an appropriate duty cycle combination. Nevertheless, finding the optimal duty cycle combination is not an easy task. Therefore, this article proposes a new pulse-width-modulation strategy for the hybrid interleaved boost-Cuk converter. The strategy includes the development of a novel mathematical model to describe the relationship between independent duty cycles and the input current ripple. The model is introduced to minimize the input current ripple by finding the optimal duty cycle combination using the differential evolution algorithm. It is shown that the proposed method further reduces the input current ripple for an operating range. Compared to the former strategy, the proposed method provides a more balanced power-sharing among converters.


Introduction
The electric and electronic devices usually require several voltage levels for their different components, dc-dc converters are electronic circuits that provide the required voltage to a certain component [1], such as a microprocessor in a computer, which requires a 1 V power supply and it is usually accompanied to a (direct current to direct current) dc-dc converter, to provide the required voltage level and power, the power converter for a microprocessor is usually dedicated since other digital circuits require different voltage levels, for example, 3.3 V or 5 V.
We can define a dc-dc converter as a power-electronics-based circuit that can change (and regulate) the voltage level from input to output, in a wide variety of applications and levels, for example, from 3.3 V to 1 V for microprocessors, or from but also from 12 V to 200 V, for photovoltaic panels applications.
The interest for dc-dc converters has recently grown because of their application in other fields such as renewable energy generation systems, especially with photovoltaic panels and fuel cells, The interest for dc-dc converters has recently grown because of their application in other fields such as renewable energy generation systems, especially with photovoltaic panels and fuel cells, those energy sources, have a relatively low output voltage, in the range of 10 to 40 volts, while gridtie inverters require a voltage in the range of 200 V. Commercial solutions contain both the dc-dc converter and the inverter in a single package. The research community is working to improve both the dc-dc converter and the dc-ac inverter.
Dc-dc converters have a wide variety of topologies and applications, in the photovoltaic panels application, a step-up or boost topology is required (a converter that increases the voltage); Figure 1 shows the schematic of the traditional boost converter [1]. Those power electronics converters are controlled by Pulse Width Modulation (PWM), a technique in which transistors are open and closed periodically, and their operation is controlled by manipulating the width of pulses, or the time they remain closed. The main characteristics of its operation can be summarized as the switching functions of the transistor, or PWM is obtained by comparing a triangular carrier against a dc signal D, which represents the duty cycle, when D overpasses the triangular carrier, the transistor s is closed (on), the diode is called s ̅ to indicate it complementary to s, the transistor keeps closed a time DTS, where TS is the switching period, the inverse of the switching frequency fS. In Figure 1, if the constant signal D decreases, their comparison with the triangular carrier will produce the time DTS to get shorter, the relation between D divided over the peak value of the triangular carrier is the same as DTS divided over TS, making this comparison procedure, a simple manner to modify (modulate) the width of the pulses that control the open and close function of the transistor. The inductor current iL waveform is composed of their dc component IL plus an ac (triangular) waveform; the maximum deviation from the dc component is called current ripple ΔiL.
The ripple can be calculated starting from the traditional inductor Equation (1) (see Equation (2.1) in [1]), which indicated the derivative of the current with respect to time in an inductor is equal to the voltage applied across their terminals.
Equation (1) can be used to calculate the input current ripple, which in this converter, in which the inductor is connected in series with the input source, the input current ripple is equal to the inductor current ripple. If the inductor is connected to a constant voltage, the derivative equation becomes an incremental equation: This incremental Equation (2) is the reason why the derivatives or slopes in the signal iL in Figure  1 are constant (it was two slopes, one positive and one negative, but they both seems as constant derivatives), when the switch is closed (which occurs during a time DTS), the inductor is connected directly to the input voltage, as it can be seen in Figure 1, the current ripple is measured as half of the total current change. The current ripple (which is half of the total peak-to-peak variation), can be The ripple can be calculated starting from the traditional inductor Equation (1) (see Equation (2.1) in [1]), which indicated the derivative of the current with respect to time in an inductor is equal to the voltage applied across their terminals.
Equation (1) can be used to calculate the input current ripple, which in this converter, in which the inductor is connected in series with the input source, the input current ripple is equal to the inductor current ripple. If the inductor is connected to a constant voltage, the derivative equation becomes an incremental equation: This incremental Equation (2) is the reason why the derivatives or slopes in the signal i L in Figure 1 are constant (it was two slopes, one positive and one negative, but they both seems as constant derivatives), when the switch is closed (which occurs during a time DT S ), the inductor is connected directly to the input voltage, as it can be seen in Figure 1, the current ripple is measured as half of the total current change. The current ripple (which is half of the total peak-to-peak variation), can be expressed as Equation (3), which is equivalent to Equation (2.43) in [1], note that Equation (3) utilizes the inverse of the switching period T S , which is the switching frequency f S .

of 18
In the traditional boost converter (Figure 1), there are two practical ways (from the engineering point of view) of reducing the switching ripple, by increasing the inductance (L), or the switching frequency (f S ). As mentioned before, it is important to maintain a low input current ripple since this reduces the RMS current provided by the power source.
Another desirable characteristic of the dc-dc converter is to have a non-pulsating input current with low ripple. A pulsating current or current with large ripple produces an early aging of the renewable energy source [2], since their rms (the root mean square) value of the current is larger, which produces additional power conduction. The ideal situation would be having a constant input current with zero ripple, or a very small (negligible) ripple, but this may be impossible or too expensive in a real situation, for the full operating range of the converter.
The state-of-the-art of power electronics contains many topologies of dc-dc converters [3,4], among the different solutions, interleaved converters, such as the interleaved boost converter, have been successfully applied, several converters in parallel, each of them have a specific input-current switching-ripple, by shifting the switching functions of converters, the switching ripple or variation can get a kind of signal cancelation, while their dc components add together to have a more powerful converter with less input current ripple.
One of the operation rules in interleaved converters is that all parallel converters must have the same duty cycle, or voltage gain, since their input voltage is the same, if one of them try to increase the voltage more than another parallel converter, a severe power imbalance will destroy the system. A characteristic of interleaved converters is that they have operation points in which the input current ripple is zero, for example, the two-phases interleaved boost converter has zero input current ripple when the duty cycle is 0.5, this operation point depends on the number of interleaved phases and cannot be selected.
On the other hand, hybrid interleaved converters have been proposed, such as in [5]; for this particular converter, the zero-input current ripple can be selected; this allows us to operate the converter in their optimal operation region.
In the traditional interleaving converters, all converters have the same duty cycle; in the hybrid converter [5], the PWM strategy assigns one duty cycle depending on the other one, they are dependent. The hybrid converter may have independent duty cycles, but then, the same voltage gain can be achieved with infinite combinations of duty cycles, each combination with different input current ripple.
Finding the optimal combination of duty cycles is not an easy task. Therefore, this article proposes a new PWM strategy for the hybrid interleaved boost-Cuk converter [5]. The strategy includes the development of a novel mathematical optimization model to describe the relationship between independent duty cycles and the input current ripple. The model is introduced to minimize the input current ripple by finding the optimal duty cycles using the differential evolution (DE) algorithm.
It is shown that the proposed method further reduces the input current ripple for an operation range, compared against the former strategy, which already had a low input current ripple, the proposed strategy also provides a better (more balanced) power-sharing among converters.

Literature Review
In the past years, researchers have applied metaheuristic algorithms to solve complex optimization problems successfully. Some examples of powerful metaheuristic algorithms are differential evolution (DE) [6], genetic algorithm (GA) [7], and particle Swarm optimization (PSO) [8], to mention a few. These methods are considered some of the most popular techniques because they are accurate, simple, and easy to implement.
State-of-the-art metaheuristic techniques have been effectively applied to solve related optimization problems such as the improved interleaved boost converter [18], which uses the PSO algorithm to find the optimal Type-III controller. In [9], a chaotic version of the PSO algorithm is proposed to improve the maximum power point tracking capability for a photovoltaic system [19]. The PSO was also implemented for tuning gains in a PI controller of a four-phase interleaved boost converter [20]. On the other hand, the DE was used in [21] for the optimal design of high-power mode converters. Other related implementations of DE and PSO algorithm can be found in [22][23][24][25].
Although the presented approaches are somehow related to converters, the proposed strategy is different in all aspects, namely the type of converter and its topology, the specific energy system application, and the objective to be improved by the implemented optimization algorithm.

Converters of Interest
As mentioned before, interleaved converters are converters of the same type, connected in parallel, Figure 2a shows a two-phase interleaved boost converter (the number of converters is sometimes referred to as the number of phases), along with their PWM strategy, Figure 2b shows PWM waveforms at the bottom and important current waveforms, both switching functions have the same duty cycle, but triangular carriers are shifted 180 • , which produces that switching functions are also shifted.
State-of-the-art metaheuristic techniques have been effectively applied to solve related optimization problems such as the improved interleaved boost converter [18], which uses the PSO algorithm to find the optimal Type-III controller. In [9], a chaotic version of the PSO algorithm is proposed to improve the maximum power point tracking capability for a photovoltaic system [19]. The PSO was also implemented for tuning gains in a PI controller of a four-phase interleaved boost converter [20]. On the other hand, the DE was used in [21] for the optimal design of high-power mode converters. Other related implementations of DE and PSO algorithm can be found in [22][23][24][25].
Although the presented approaches are somehow related to converters, the proposed strategy is different in all aspects, namely the type of converter and its topology, the specific energy system application, and the objective to be improved by the implemented optimization algorithm.

Converters of Interest
As mentioned before, interleaved converters are converters of the same type, connected in parallel, Figure 2a shows a two-phase interleaved boost converter (the number of converters is sometimes referred to as the number of phases), along with their PWM strategy, Figure 2b shows PWM waveforms at the bottom and important current waveforms, both switching functions have the same duty cycle, but triangular carriers are shifted 180°, which produces that switching functions are also shifted.
The input current is equal to the sum of the current through inductors, inductors drain the same dc current since duty cycles are equal, but the phase shift produces that their ac component (switching ripple), have a certain cancelation, and the input current ripple is smaller than the ripple in individual inductors.  The input current is equal to the sum of the current through inductors, inductors drain the same dc current since duty cycles are equal, but the phase shift produces that their ac component (switching ripple), have a certain cancelation, and the input current ripple is smaller than the ripple in individual inductors.
The advantage is that smaller inductors can be selected to perform with the same current ripple of the single boost converter (Figure 1), despite the number of components, which is larger in Figure 2a, since passive components (inductors and capacitors) are smaller for the interleaved version, and electronic devices are getting miniaturized with the new technology, interleaved converters are usually smaller than their non-interleaved counterpart. The reduction of the size of inductors is especially beneficial since it is usually the largest and heaviest component in the circuit. The converters that accompany the computer microprocessor is an interleaved buck converter.
The interleaved boost converter actually achieves zero input current ripple, when the duty cycle is 0.5, switching functions are perfectly complementary in this case, but converters operate into a region of duty cycles, not a single one because they contain the closed-loop control which compensates the duty cycle if a perturbation occurs (such as a variation on the input voltage).

The Hybrid Converter with the Existing PWM Strategy
The hybrid converter under study is shown in Figure 3a, as proposed in [5], is made by the interconnection of a Cuk and a boost converter, they share the same input voltage, the load is connected in a differential mode from the output of the Cuk, to the output of the boost converter, since the Cuk provides a negative output voltage with respect to the boost converter, the voltage gain is larger than interleaving two boost converters since their outputs are independent, converters may have different duty cycles. The advantage is that smaller inductors can be selected to perform with the same current ripple of the single boost converter (Figure 1), despite the number of components, which is larger in Figure  2a, since passive components (inductors and capacitors) are smaller for the interleaved version, and electronic devices are getting miniaturized with the new technology, interleaved converters are usually smaller than their non-interleaved counterpart. The reduction of the size of inductors is especially beneficial since it is usually the largest and heaviest component in the circuit. The converters that accompany the computer microprocessor is an interleaved buck converter.
The interleaved boost converter actually achieves zero input current ripple, when the duty cycle is 0.5, switching functions are perfectly complementary in this case, but converters operate into a region of duty cycles, not a single one because they contain the closed-loop control which compensates the duty cycle if a perturbation occurs (such as a variation on the input voltage).

The Hybrid Converter with the Existing PWM Strategy
The hybrid converter under study is shown in Figure 3a, as proposed in [5], is made by the interconnection of a Cuk and a boost converter, they share the same input voltage, the load is connected in a differential mode from the output of the Cuk, to the output of the boost converter, since the Cuk provides a negative output voltage with respect to the boost converter, the voltage gain is larger than interleaving two boost converters since their outputs are independent, converters may have different duty cycles.   The capacity to operate with different duty cycles in each power stage is an additional degree of freedom, that was used in [5] to select the duty cycle in which the input current ripple is equal to zero. Figure 3c shows the PWM strategy, and Figure 3b shows current waveforms in the duty cycle in which the input current ripple is zero, the current through inductors have an ac component which perfectly cancels each other at the input side.
As mentioned before, this particular operation point is just one of an operation range. When the duty cycle changes (due to the operation of the closed-loop control), a ripple appears, similar to Figure 2, the ripple is still smaller compared to the current ripple in one inductor.
Having the freedom to choose the duty cycle in which the current ripple is zero, is an advantage, for example, let us think on an application of the traditional interleaved boost converter, in which zero ripple duty cycle is 0.5, if the operation range of the duty cycle is between 0.6 and 0.7, the converter will never reach their ideal operation, in that case, it would be beneficial to choose the ideal operation to be in the duty cycle of 0.65.
This article proposes to operate this converter with a novel PWM strategy, in which the converter still have the zero ripple duty cycle in a chosen value, but it will be shown that the proposed strategy reduces the input current ripple in the full operation range, in the vicinity of the zero ripple duty cycle. Furthermore, it will be shown that the proposed strategy also provides a better balance on power-sharing among converters. For this purpose, the switching ripple will be analyzed first in their current operation.

Mathematical Model of the Hybrid Converter
In order to analyze the input current-ripple of the converter, which depends on variables such as the input voltage, the inductance of inductors and the equilibrium state-variables of the system, am equilibrium model of the state variables, (current through inductors and voltage across capacitors) is introduced in this section.
Since converters that compose the hybrid converter are well-known with proven operation [1], their model can be straight forward presented, considering the state variables as the current through inductors and the voltage across capacitors, the state equilibrium can be expressed as: where D x (x = 1, 2) is the duty cycle for each transistor s x , the voltage V Cy (y = 1, 2, 3) as the voltage of each capacitor C y , and the current i Lz (z = 1, 2, 3) as the current of each inductor L z , a capital letter in equations indicates the equilibrium value of each variable; I o represents the output current. The output voltage is provided by the series connection of C 1 and C 3 , considering the load resistance R, then the output characteristics can be expressed as Equation (7).

Current PWM Strategy
The current PWM strategy for the hybrid converter is based on the definition that the duty cycle of the converter is assigned to s 2 , d = d 2 , and the duty cycle of s 1 (d 1 ), is defined as a fraction of d by multiplying d by a factor k. By assigning the same relationship to inductors.
The factor k can be calculated from the duty cycle in which the input current ripple is desired to be zero, this duty cycle can be named D Z, and the relationship can be expressed as: This is a straightforward procedure; a full explanation and design procedure were provided in [5]. The input current ripple must be explained in two different conditions, where D > D Z , and then D < D Z .

Proposed PWM Strategy
The current PWM strategy has a good performance, but when defining one duty cycle is proportional to the second one during the full operation range, a degree of freedom is lost, in the proposed strategy, the factor k is variable, duty cycles can be still expressed as in Equation (8), but k is not constant, and we can choose the best value in each operation point.
The factor k, which now is variable, defines the relationship among duty cycles, inductors cannot be changed during the operation, their relationship is constant, and then, a second factor is defined k L , which is constant and defines the relationship among inductors: Now there are two variables to choose during the operation, which are either duty cycles D 1 and D 2 , or the general duty cycle D and the factor k. A challenge arises, there is an infinite number of combinations of those two variables to achieve certain voltage gain. In the former strategy, when k was constant, there was one duty cycle for each voltage gain. The strategy consists of choosing the combination of D and k, which minimizes the input current ripple.
It is intuitively expected that during the zero-ripple gain, k will be equal to k L , but in other cases, it will be different, and this degree of freedom can be used to further reduce the input current ripple.

The Case When D > D Z
Let us start with the case then D > D Z , in other words, when there is an overlap on the switching functions, see Figure 4, under those conditions, there are two different periods in which the maximum ripple may appear (in gray in Figure 4): (1 − kD)T S (the large gray period in Figure 4) and (1 − D)T S (the short gray period in Figure 4).
During the period (1 − kD)T S , the input current ripple may be expressed as Equation (12).
During the period (1 − D)T S , the input current ripple may be expressed as Equation (14). Which, considering Equations (5) and (8) can be simplified as: Since there are two different periods in which the current ripple may reach a maximum value, the optimization algorithm must minimize them both; intuitively, they are expected to be equal to each other. Similarly, when D < D Z, there are two periods in which the maximum current ripple may appear.  During the period (1 − D)TS, the input current ripple may be expressed as Equation (14).
Which, considering Equations (5) and (8) can be simplified as: Since there are two different periods in which the current ripple may reach a maximum value, the optimization algorithm must minimize them both; intuitively, they are expected to be equal to each other. Similarly, when D < DZ, there are two periods in which the maximum current ripple may appear.

The Case when D < DZ
When D < DZ, there is a dead-time (a period in which transistors are both off) on the switching functions, see Figure 5, under those conditions, there are two different periods in which the maximum ripple may appear, marked in gray in Figure 5, those periods are DTS (the large gray period in Figure  5) and kDTS (the short gray period in Figure 5).
During the period DTS, the input current ripple may be expressed as Equation (16).

The Case When D < D Z
When D < D Z , there is a dead-time (a period in which transistors are both off) on the switching functions, see Figure 5, under those conditions, there are two different periods in which the maximum ripple may appear, marked in gray in Figure 5, those periods are DT S (the large gray period in Figure 5) and kDT S (the short gray period in Figure 5).  During the period (1 − D)TS, the input current ripple may be expressed as Equation (14).
Which, considering Equations (5) and (8) can be simplified as: Since there are two different periods in which the current ripple may reach a maximum value, the optimization algorithm must minimize them both; intuitively, they are expected to be equal to each other. Similarly, when D < DZ, there are two periods in which the maximum current ripple may appear.

The Case when D < DZ
When D < DZ, there is a dead-time (a period in which transistors are both off) on the switching functions, see Figure 5, under those conditions, there are two different periods in which the maximum ripple may appear, marked in gray in Figure 5, those periods are DTS (the large gray period in Figure  5) and kDTS (the short gray period in Figure 5).
During the period DTS, the input current ripple may be expressed as Equation (16).
Δi in Figure 5. PWM important waveforms in the proposed converter when D < DZ. During the period DT S , the input current ripple may be expressed as Equation (16).
Which, considering Equations (4) and (8), can be simplified as Equation (17). During the period kDT S , the input current ripple may be expressed as Equation (18).
Which, considering Equations (5) and (8) can be simplified as: Then, the algorithm to choose the duty cycle D, and the scalar factor k, must minimize Equations (13) and (14) in the case the gain requires a D > D Z , and Equations (17) and (19) otherwise, this can be an iterative process, at the same time, the algorithm must comply the gain, which can be expressed from Equation (7) as Equation (20).

The Optimization Process
Evolutionary-based metaheuristics and swarm intelligence algorithms, such as particle swarm optimization (PSO), firefly algorithm (FA), genetic algorithm (GA), cuckoo search (CS), grey wolf optimizer (GWO), and ant colony optimization (ACO) has been extensively used for solving complex optimization problems. Some recent applications on the industry are described in [26], where authors reported that the PSO had been mainly implemented in the electric power industry, including as the most popular areas the reactive power and voltage control, system identification, and intelligent control, and the generation expansion problem. Moreover, ACO has been primarily used for machine learning tasks such as feature selection and parameter optimization for support vector machines. According to the authors, other applications of the ACO include fields such as data mining, energy savings in wireless sensor networks, and water distribution systems.
On the other hand, in [27], an evolutionary-based algorithm has been used for truck scheduling at cross-docking terminals. It analyses the performances of the evolutionary method in finding the optimal schedule by varying the mutation levels. Also, a delayed start parallel evolutionary algorithm has been proposed for truck scheduling at a cross-docking facility [28].
The performance of swarm-based algorithms has also been analyzed in other real applications, such as for wind farm decision systems in [29], where the authors included optimization algorithms, namely FA, CS, GA, and ACO. Furthermore, a review of swarm-based algorithms for feature selection is presented in [30]. In the survey, the performances of the most promising swarm intelligence methods, namely PSO, ACO, FA, and GWO, are analyzed. Finally, a supervised learning approach based on PSO is introduced for social aware cognitive radio handovers in [31].
The presented real applications have proved the efficiency of evolutionary-based and swarm-based metaheuristics for solving complex optimization problems. Therefore, an evolutionary method, which can also be considered as a swarm-based technique, has been selected in this research.
In the proposed technique, the differential evolution (DE) algorithm is used to optimize the general duty cycle D and the factor k. The objective is to choose the best values of D and k in each operation point, such that their combination minimizes the input current ripple.

Differential Evolution Algorithm
The differential evolution algorithm is a popular evolutionary algorithm (EA) that is based on operators such as mutation, recombination, and selection. In its basic operation, the DE algorithm uses a set of search agents X = {x 1 , x 2 ..., x m }, where each individual x i represents a potential solution that improves over time under an evolutionary process.
The DE algorithm starts by randomly initializing the population, which is evaluated in the fitness function. After that, individuals evolve in an iterative process by the influence of mutation, recombination, and selection operators.
Under the mutation operator, individuals are transformed by a mutant vector, which is calculated as Equation (21): where the mutant vector is v and F is a weighted factor whose values are in the interval of [0, 2], elements x r1 , x r2 , and x r3 , are randomly selected particles from the set of search agents.
In the recombination process, new candidate solutions are generated by combining the mutant vector v with an individual x i . The result from this combination is a trial solution u, which is defined by Equation (22): where p is the recombination probability parameter, while rand represents a random value in the interval [0, 1], subscript j corresponds to the index of the problem dimension. After recombination, the population is evaluated in the fitness function. The last operation of the DE algorithm is the selection of the best elements. The selection determines which individuals will remain for the next generation and which will be discarded. Considering the problem is a minimization type, the selection is based on the fitness value of candidate solutions u and x i , which can be expressed as Equation (23).
where f(u) and f(x i ) are the fitness values of u and x i, respectively. The process of mutation, recombination, and selection is repeated in an iterative process until a stop criterion is reached. The described DE algorithm can be summarized in Figure 6.

Proposed Mathematical Model
In order to optimize the general duty cycle D and the factor k by implementing the DE algorithm, a mathematical model is proposed. This model acts as the objective function and is used to minimize the input current ripple.
Since there are two different periods in which the current ripple may reach a maximum value, the objective function must be designed to minimize the highest input current ripple. Considering At the end of the search process, the solution is the best element among the population. The best individual is considered the global best particle whose fitness value is the lowest in the population.

Proposed Mathematical Model
In order to optimize the general duty cycle D and the factor k by implementing the DE algorithm, a mathematical model is proposed. This model acts as the objective function and is used to minimize the input current ripple.
Since there are two different periods in which the current ripple may reach a maximum value, the objective function must be designed to minimize the highest input current ripple. Considering the case when D > D Z , the model contemplates the minimization of the highest input current ripple between definitions Equations (13) and (15). Similarly, when D < D Z , the highest input current ripple among Equations (17) and (19) is minimized under the designed cost function.
Additionally, the proposed model must include some constraints such as the achievement of the desired voltage gain, the input current ripple considering the switching time, and the search domain that contemplates the permissible values of D and k. Under the above restrictions, the proposed model can be expressed as Equation (24): Subject to where t is the permissible tolerance, which considers the 1% of the desired voltage gain G, while f 1 (D,k) and f 2 (D,k) are defined in Equations (28) and (29), respectively:

Implementation of DE in the Proposed Model
To minimize the highest input current ripple, the implementation of the DE algorithm must consider each individual from the population as a bidimensional vector that represents the combination of the possible values of D and k. Therefore, an individual x i is defined as Equation (30).
The quality of the candidate solution is given by the evaluation of x i in the objective function described by Equation (24). Thus, Equation (24) can be rewritten as Equation (31): Since the proposed model represents a constrained optimization problem, the evaluation of the population in the objective function requires the implementation of a penalty function. This function is employed to modify the fitness value of a candidate solution when one or more constraints are not met. Thus, the penalty function is used to guide the search toward feasible solutions. In the proposed strategy, the penalty function is expressed as in Equation (32): where w is a constant factor that regulates how much the fitness value of a candidate solution is penalized. The violated constrain indicator is c, where c {0, 1}. The value of c is 1 when the constraint described in Equation (25) is not fulfilled; this value will activate the penalty function. Otherwise, its value is 0, additionally, x i1 = D and x i2 = k.
Considering the penalty function for the evaluation of the population, the objective function defined in Equation (31) can be rewritten as Equation (33): In the optimization process, a population of m candidate solutions is randomly initialized under the lower and upper bounds defined by Equations (26) and (27). Then, the population is evaluated in the objective function given by Equation (33). After that, the iterative process begins, where individuals are mutated and recombined by using Equations (21) and (22), respectively. Finally, the best elements are selected to be the new population, which will be part of the next generation. The process is repeated until the maximum number of generations g max is reached. The complete procedure is summarized in Algorithm 1.

Algorithm 1. Optimization process.
Input: m, g max Output: D,k

2.
Initialize the population

4.
Identify the global best individual

5.
For each element x i in the population

Experiments and Results
Several numerical experiments have been conducted to evaluate the performance of the proposed technique, where the former strategy is compared with the proposed method.
In the experiments, different desired voltage gain values are considered to demonstrate the robustness of our technique. These values range from 3 to 6, which are a representative sample of the most significant values.
Regarding the parameter configuration of the DE method, the weighted factor F has been randomly selected from a uniform distribution within the range from 0.2 to 0.8, the recombination probability p is equal to 0.2, and the constant factor w is 10. For all calculations, the case study includes the parameters for a converter shown in Table 1, which can be considered as standard realistic data. Since the DE algorithm is a stochastic method, the reported results consider the average value obtained from 30 independent executions. The size of the population m has been configured to 20, while the maximum number of generations g max is 100 for each execution. The source code is available at Mathworks using the following link https://la.mathworks.com/ matlabcentral/fileexchange/78146-pwm-hybrid-power-converter-using-differential-evolution.
Results obtained by the former strategy are reported in Table 2. The best outcomes are highlighted in boldface. A close inspection in Table 2 demonstrates that the new strategy achieves the lowest input current ripple ∆ ig in all experiments, and also proves a better balance in the power-sharing among converters than the old strategy. Figure 7 shows the reported values in Table 2. From this figure, it is evident how the new strategy achieves lower values for the input current ripple in the full operating range. An exception occurs when the gain G is 3.166¯. In that case, both methods reach the same minimum value for the input current ripple.  A convergence-graph is presented in Figure 8 to evaluate the speed performance of the DE algorithm. In the test, four operation points are considered to analyze the velocity of the optimization algorithm in reaching the optimal value. This figure shows, in a single execution, the obtained input current ripple in every generation, where the considered gains are 3.5, 4, 5, and 6 for Figure 8a-d, respectively. These gain values have been selected according to the most representative and significant operation points.
The reported results have been validated and analyzed under a statistical context. In the analysis, the Wilcoxon test has been implemented [32] to determine the difference between both strategies in comparison. A null hypothesis is established in the Wilcoxon test, in which there is no evidence that  A convergence-graph is presented in Figure 8 to evaluate the speed performance of the DE algorithm. In the test, four operation points are considered to analyze the velocity of the optimization algorithm in reaching the optimal value. This figure shows, in a single execution, the obtained input current ripple in every generation, where the considered gains are 3.5, 4, 5, and 6 for Figure 8a-d, respectively. These gain values have been selected according to the most representative and significant operation points.   The obtained p-values for two samples are lower than the significance level, reaching a p-value of 0.0000639 in all operating points. Statistically, these values are too small, so they can be considered zero. Besides, the obtained p-values are the same in all operating points because the 30 observations of each configuration are lower than the hypothesized median value of the former strategy, causing the median value of the proposed method to be lower than the hypothesized median. Except for G=3.166̅ , where all observations are higher, causing the median value of the proposed method to be higher than the hypothesized median. Both scenarios generate the same p-values and indicate a significant difference between the approaches in comparison. Summarizing, the obtained p-values for two samples confirm that there is evidence against the null hypothesis, indicating a significant difference among both approaches for all the numerical experiments.
Similarly, the p-values for one sample are lower than the significance level, reaching a p-value of 0.000032 in all operating points. These results confirm that there is evidence against the null hypothesis, indicating that our approach reaches a lower input current ripple than the old strategy for all the numerical experiments. An exception occurs when G = 3.166̅ , where the null hypothesis is accepted. In this case, all observations were higher than the hypothesized median value of the former strategy, which can be confirmed by the corresponding Wilcoxon statistic, whose value is 465. This means that the new approach did not achieve a lower input current ripple than the old method for this operating point, and can be confirmed by observing the reported Δig value from Table 2 for G = 3.166̅ , where both approaches reached the same input current ripple.
Considering the statistical results, we can conclude that the Wilcoxon test supports the reported outcomes from Table 2, in which the proposed strategy has demonstrated its superiority against the former strategy. The reported results have been validated and analyzed under a statistical context. In the analysis, the Wilcoxon test has been implemented [32] to determine the difference between both strategies in comparison. A null hypothesis is established in the Wilcoxon test, in which there is no evidence that indicates a significant difference among both approaches. On the other hand, the null hypothesis is rejected when a significant difference is observable.
Additionally, the Wilcoxon test considering one sample has been conducted to determine if the median value of the proposed strategy is significantly lower than the hypothesized median value of the former method for each operating point. A null hypothesis is established in which there is no evidence that indicates the median value of the proposed method is significantly lower than the hypothesized median value of the former strategy. This test will statistically confirm if our approach reaches a lower input current ripple than the old strategy.
In both analyses, the 30 ∆ ig results obtained from 30 independent executions for each operation point are contemplated as the observations of the proposed strategy. Regarding the former strategy, the obtained result ∆ ig is considered 30 times since it always reaches the same value for every operating point. The Wilcoxon statistic and the p-values obtained from both tests in every operating point indicate if the null hypothesis has been accepted or rejected. Therefore, if the p-values are lower than the significance level of 0.05, the null hypothesis is rejected.
The obtained p-values for two samples are lower than the significance level, reaching a p-value of 0.0000639 in all operating points. Statistically, these values are too small, so they can be considered zero. Besides, the obtained p-values are the same in all operating points because the 30 observations of each configuration are lower than the hypothesized median value of the former strategy, causing the median value of the proposed method to be lower than the hypothesized median. Except for G=3.166¯, where all observations are higher, causing the median value of the proposed method to be higher than the hypothesized median. Both scenarios generate the same p-values and indicate a significant difference between the approaches in comparison. Summarizing, the obtained p-values for two samples confirm that there is evidence against the null hypothesis, indicating a significant difference among both approaches for all the numerical experiments.
Similarly, the p-values for one sample are lower than the significance level, reaching a p-value of 0.000032 in all operating points. These results confirm that there is evidence against the null hypothesis, indicating that our approach reaches a lower input current ripple than the old strategy for all the numerical experiments. An exception occurs when G = 3.166¯, where the null hypothesis is accepted. In this case, all observations were higher than the hypothesized median value of the former strategy, which can be confirmed by the corresponding Wilcoxon statistic, whose value is 465. This means that the new approach did not achieve a lower input current ripple than the old method for this operating point, and can be confirmed by observing the reported ∆ ig value from Table 2 for G = 3.166¯, where both approaches reached the same input current ripple.
Considering the statistical results, we can conclude that the Wilcoxon test supports the reported outcomes from Table 2, in which the proposed strategy has demonstrated its superiority against the former strategy.
As a complementary analysis, the speed performance of the algorithms is presented. For the proposed method, 30 independent executions have been considered. The experiments have been implemented on a PC with 8 GB of memory and an Intel ® Core i7 Processor (3.4 GHz).
From the speed test, the elapsed real-time of the former strategy ranges from 0.01 to 0.02 s. These variations are due to delays in the internal computation process. On the other hand, the proposed method differs from 0.19 to 0.21 s because of the same reason. These variations are bigger than those reported by the old strategy because the new approach requires more calculus, causing more delays.
Summarizing, it is evident that the former strategy is faster than the proposed method. As it was expected, our approach requires more computational time to find the optimal duty cycle combination. However, the execution time is approximately 20% of one second, which is quite fast, considering that the new strategy is an iterative method.

Discussion
As shown in Table 2, the former strategy provides a large current ripple for all operation points, except with the zero ripple operation point, in which both strategies provide zero input current ripple. Furthermore, the power-sharing among power stages is more balanced (the current among inductors has less difference).
One compromise of the optimization is evidently the time it takes to optimize (minimize the input current ripple), the former strategy takes less time to choose the duty cycle, but the input current-ripple is not optimized. In a real application there are two choices to implement the optimized duty cycle, the first option would be to calculate off-line the optimized k for each duty cycle, and chose the consequent k from a look-up table, a second options, which depends on the application, is to have a microcontroller (a small microprocessor), to run the DE algorithm online, the advantage of the second option it would be to have a better optimization in the case the duty cycle is in between two duty cycles of the look-up table, it would be better to optimize it again, instead of doing the linear interpolation, in the other hand, it would require more computational power from the control system of the converter.

Conclusions
This article introduced a new PWM strategy for the hybrid interleaved boost-Cuk converter, the proposed strategy uses the differential evolution (DE) algorithm to find the duty cycle and the scalar factor k, which defines the duty cycle of each interleaved stage in an independent manner, the algorithm fulfills the required gain, and at the same time, it minimizes the input current ripple. It is shown that the proposed method achieves a smaller input current ripple in the full operation range compared against the input current ripple for the former strategy, which already had a low input current ripple, the proposed approach also provides a better (more balanced) power-sharing among converters. Although the proposed method is computationally more expensive than the former strategy, the obtained duty cycle combination significantly decreases the input current ripple, which satisfies one of the most desired characteristics for a converter, in which a non-pulsating input current with low ripple is achieved. Otherwise, a pulsating current or current with higher ripple produces an early aging of the renewable energy source because the root-mean-square value of the current is larger, generating additional power conduction.
As future work, the performance analysis of other evolutionary algorithms for the duty cycle optimization problem can be conducted. This research will provide valuable information on selecting the best optimization option. Furthermore, the mathematical model can be improved by a possible merging of constraints in order to allow finding a lower ripple by the evolutionary algorithm.