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Article

Wafer Delay Minimization in Scheduling Single-Arm Cluster Tools with Two-Space Process Modules

1
Department of Engineering Science, Faculty of Innovation Engineering, Macau University of Science and Technology, Taipa, Macao 999078, China
2
IKAS Industries Company, Ltd., Chongqing 401120, China
*
Author to whom correspondence should be addressed.
Mathematics 2024, 12(12), 1783; https://doi.org/10.3390/math12121783
Submission received: 3 April 2024 / Revised: 26 May 2024 / Accepted: 30 May 2024 / Published: 7 June 2024
(This article belongs to the Special Issue Discrete Event Dynamic Systems and Applications)

Abstract

:
In semiconductor manufacturing, multi-space process modules (PMs) are adopted in some cluster tools for wafer processing. With multi-space PMs, a PM can have multiple wafers concurrently. Also, the internal chamber in a PM should rotate to make the robot able to load/unload a wafer into/from a space in the PM. This means that the wafer staying time in PMs is affected by both the rotation operations of the internal chambers of PMs and the robot tasks. Thus, minimizing the wafer delay time is quite challenging. In this work, for cluster tools with single-arm robots and two-space PMs, efforts are made for wafer delay minimization in scheduling the tools. Specifically, a two-wafer backward strategy is presented to operate the tools in a steady state. Then, the workloads of each processing step and the robot are analyzed. Further, to find optimal schedules with the objective of minimizing the total wafer delay time, efficient algorithms are established. Finally, case studies show that the wafer delay time at some steps can be totally eliminated by the proposed method. In the meantime, in all cases, the proposed method can work well in reducing the total wafer delay time at all steps.

1. Introduction

In semiconductor fabs, as the key equipment for wafer fabrication, cluster tools handle 70–80% of wafer fabrication processes [1]. When semiconductor fabs have to process a large batch of identical wafers, the fabs require a steady-state production system, and cluster tools can do so [2]. For cluster tools, there are two loadlocks (LLs) for holding the wafers, multiple chambers or process modules (PMs) for processing wafers, and one robot for wafer transportation within the tool [3,4,5,6,7,8]. The PMs surround the robot. With a single-arm robot or dual-arm robot, a tool is called a single-arm cluster tool (SACT), as shown in Figure 1a, or a dual-arm cluster tool (DACT), as shown in Figure 1b.
In a cluster tool, after loading a wafer lot containing several wafers into LLs, each wafer is transferred by the robot to a PM for processing. Cluster tools are not only subject to time constraints but also various process constraints, such as varied wafer flows, PM parallelization, the absence of buffers between PMs, the prohibition of wafer returns to the LL before completing all processing steps, and limits on wafer delays within PMs. Wafer strict timing constraints, together with other complex constraints, make the scheduling problem of cluster tools much more complicated [9,10]. Due to the necessity of utilizing the robotic arms for wafer transportation, the key issue in scheduling cluster tools is to schedule the robotic arms [11].
With two LLs, once one wafer lot is processed, another wafer lot can be processed in a tool immediately. It ensures that the tools operate in a steady state most of the time. Significant efforts have been devoted to achieving the steady state scheduling of cluster tools in [12,13,14,15,16,17]. It is found that for an SACT, a backward strategy is proven to be optimal, while a swap strategy is optimal for a DACT [18,19]. Those studies do not take wafer residency time constraints (RTCs) into account. However, as the circuit width gets narrower and narrower, RTCs are proposed to ensure wafer quality assurance. With RTCs satisfied, wafers avoid staying in PMs for a relatively long time. Otherwise, it may cause quality problems for wafers due to the complex internal environment of PMs.
The time for the wafer to stay in a PM consists of two components: one is the wafer processing time, and the other is the wafer delay time. Reducing the delay time is crucial to satisfying RTCs. For DACTs, ref. [20] indicates that making wafers wait on the robot during swap operations can effectively reduce the wafer delay time. For SACTs, by delaying the unloading time point at a step, the wafer delay time at the next step is decreased [21,22,23]. Also, for both SACTs and DACTs, a schedule satisfying RTCs could be produced by the feedback control approaches proposed in [24,25]. Additionally, for DACTs with RCTs, if a conventional swap strategy fails to meet RTCs, ref. [26] presents new robot task sequences to decrease the wafer delay time. Under the K-cyclic schedules of DACTs, ref. [27] analyzes the wafer delay time in the worst situation and provides instructions to minimize such delay time in the worst situation. For a robotic cell that is similar to cluster tools, with robot-collaborated processes and RTCs, a tabu circulatory time point searching algorithm is constructed to minimize the average cycle time [28].
Cluster tools allow for the concurrent processing of multiple wafer types. With multi-wafer types and RTCs, ref. [11] proposes a multiplex backward sequence to operate SACTs in a steady state. In [20], a proper cyclic processing plan for multiple wafer types is proposed so as to reduce wafer delays in cluster tools. For multi-cluster tools with two-wafer types, ref. [29] devises an efficient algorithm to generate a schedule satisfying RTCs. The quality of the product requires maintaining consistency in the operations of cluster tools in all task cycles so that the wafer delay time remains unchanged. Thus, ref. [30] presents an integrated scheduling method for DACTs to maximize steady schedule patterns to maintain consistency in the operations of the tools.
In practice, the activity time within cluster tools may fluctuate within a bounded range. For DACTs with RTCs and uncertain activity time, in [31], cases are identified as always schedulable or never schedulable. Subsequently, in [32,33,34,35], through a robot waiting time adjustment policy, the disturbances in robot tasks are offset for both SACTs and DACTs as much as possible. Also, the wafer delay time in the worst situation is analyzed, and algorithms with polynomial computational complexity are established to find optimal schedules. For multi-cluster tools with uncertain activity times, algorithms are developed in [36] to analyze the worst-case wafer delay time. Then, a given schedule, if it satisfies RTCs, can be easily checked. Additionally, new scheduling approaches introduced in [37] aim to ensure the stability of cluster tools and adapt to processing time variation. To maintain consistency of wafer delay by considering uncertain activity time, ref. [38] proposes a feedback control approach for scheduling cluster tools effectively.
Over the past decade, more and more studies have been focused on optimizing transient processes with cluster tools. In [39], for DACTs operated under a determined robot task sequence, the initial and final transient processes starting from and ending with an empty state are optimized, respectively. In [40,41,42], for both SACTs and RTCs, feasible schedules are found for the initial and final transient processes. For DACTs with revising processes, under a one-wafer periodical schedule, efficient algorithms are developed [43] to minimize the time required for the initial transient process. Moreover, significant efforts have been made to optimize the lot switching process in both SACTs and DACTs [44,45,46,47,48]. In order to improve the wafer lot delivery efficiency between two semiconductor tools, expressions for obtaining lot completion times considering lot switching operations are given in [6]. The mentioned studies on cluster tools are carried out in each PM, which has only one space. However, to enhance the throughput of cluster tools, PMs are now designed to have more than one space, such that multiple wafers can enter a PM for processing at a time. Figure 2 illustrates an SACT with two-space PMs. In a multiple-space PM, at a state where only one space is near the door of the PM, only one wafer can be removed from or loaded into the PM at a time. Additionally, the internal chambers of a PM can rotate such that each space can rotate to the door of the PM. This way, the robot can load or unload a wafer into each space within the PM efficiently.
For cluster tools with one-space PM, after a wafer enters a PM by performing the robot loading task, the PM can start its processing activity, implying that the processing activities follow the robot tasks. As a result, it is vital to determine the robot’s task sequence [49,50]. Nevertheless, in this work, the internal chambers of PMs ought to perform rotation operations such that the robot can accurately load wafers into PMs for processing, except for processing activities. It should be noted that if a PM is still conducting such a rotation operation when the robot reaches the PM for loading or unloading, the robot has to wait. It implies that such rotation operations might delay the robot’s task time. Consequently, for cluster tools with multiple-space PMs, it is necessary to analyze how the rotation operations affect the robot task schedule. This makes the results obtained for cluster tools with one-space PMs in the existing studies not directly applicable to multiple-space PMs. It motivates us to conduct a scheduling analysis of SACTs with multiple-space PMs to minimize the wafer delay time. Also, without loss of generality, this work deals with the case where a PM has two spaces. Note that the results obtained in this work can be readily extended to cases where a PM has more than two spaces in an SACT.
The rest of the paper encompasses four sections. In Section 2, a two-wafer backward strategy is presented, and then the workloads of each processing step and the robot are analyzed. In Section 3, algorithms are established to find optimal schedules with the objective of minimizing wafer delay time. The applications of the proposed method are demonstrated by several examples in Section 4. The conclusion is given in Section 5.

2. System Analysis

2.1. Two-Wafer Backward Strategy

A serial-parallel wafer flow pattern in a cluster tool is defined as SPWFP = (m1, m2, …, mn), where n denotes the number of processing steps (operations) to complete a wafer and mi is the number of parallel PMs equipped for the i-th step. In this work, the LLs are labeled as Steps 0 and n + 1. Then, with the wafer flow pattern (m1, m2, …, mn), an unprocessed wafer enters the tool through Step 0, visits Steps 1 − n for processing, and finally goes back to Step n + 1 after being processed.
The robot is responsible for transporting wafers to PMs for processing. The actions of the robot and their corresponding timing are shown in Table 1. Robot tasks include unloading, loading, and moving. The robot tasks “unloading” and “loading” realize that a wafer is picked out from a PM and dropped into a PM, respectively. Let  N n +  = {1, 2, …, n} and Nn =  N n +   {0}. UDi and LDi, iNn ∪ {n + 1}, stand for the robot tasks of unloading and loading at a PM at Step i, respectively. The robot moving from Steps i to j is denoted by Mij, ij, i, jNn ∪ {n + 1}, and (i, j) ⊄ {0} × {n + 1}, where {0} × {n + 1} is the Cartesian product of {0} and {n + 1}.
Robot tasks take time. In real production scenarios, the processing time in a PM is relatively long compared with the robot’s task time, and it often needs more than 50 s. However, the robot’s moving time is normally 1~3 s, and both unloading and loading times are less than 8 s. The robot’s task time is quite short, and they are all treated as constants. In the meantime, due to the similar movement mechanism, the time taken for loading and unloading is assumed to be the same. Then, the time to perform Mi,j is represented by μ, and the time to perform UDi or LDi is represented by λ.
A two-space PM can process two wafers simultaneously. With a one-arm robot in an SACT, to process two wafers concurrently by a PM, one wafer should enter the PM earlier than the other. Also, every time a wafer enters a PM, it should occupy a space at the door of the PM. The time spent by a wafer staying in a PM is also called wafer sojourn time. We use τi1 and τi2 to denote the sojourn time of two wafers concurrently processed in a PM at Step i, i ∈  N n + . Note that τi1 and τi2 are for the wafers entering the PM earlier and later, respectively. Furthermore, αi, i ∈  N n + , denotes the processing time at Step i. Then, at Step i, to complete the processing of wafers, τi1αi and τi2αi should be satisfied, i ∈  N n + .
For a two-space PM, after the robot performs UDi/LDi at a PM, the PM should rotate so that the robot can perform UDi/LDi at the PM again. Thus, two wafers can sequentially enter the PM, or two wafers can sequentially leave the PM. We use  R i u  and  R i l , i ∈  N n +  to stand for the rotation operations of a PM after UDi and LDi at the PM are performed, respectively. The time to complete  R i u  or  R i l  is denoted by r. Note that LLs cannot rotate.
With a PM occupied by two wafers at a state, when the robot arrives there to unload them, it may stay there to wait until the wafers are completed. The time for such robots waiting at Step i is denoted by ωi, iNn, and the waiting activity is denoted by Ai, iNn. Moreover, for the two spaces in a PM, when one of them is at the door of the PM and the other is at the opposite place. Thus, after a wafer leaves the space at the door by performing a robot unloading task, the internal chamber of the PM rotates such that the other space rotates to the door. Then, when the robot is ready to unload a wafer from the other space, the PM may not complete the rotation and is still rotating. At this moment, the robot needs to stay there to wait. At Step i, i ∈  N n + , such a robot waiting activity at a PM is denoted by  A i ru . Furthermore, when two wafers enter an empty PM, after one wafer enters one of the spaces of the PM by performing the robot loading task, the internal chamber of the PM should rotate such that the other space rotates to the door. Then, when the robot reaches the PM again to load another wafer, it may need to stay there to wait for the completion of the rotation operation of the PM. At Step i, i ∈  N n + , such a robot waiting activity at a PM is denoted by  A i rl . The time to perform  A i ru  and  A i rl  is denoted by  ω i ru  and  ω i rl , respectively.
For an SACT with one-space PMs, from the perspective of productivity, a backward strategy is effective. Based on such a conventional backward strategy, a two-wafer backward strategy is presented for an SACT with two-space PMs. Let RTSi = 〈UDiMi(i+1)LDi+1M(i+1)iUDiMi(i+1)LDi+1〉, iNn, denote a robot task sequence. To maximize the productivity of a cluster tool, all PMs are full of wafers for processing. Then, by a two-wafer backward strategy, without robot waiting activities being considered, robot task sequence 〈RTSnM(n+1)(n−1)RTSn−1Mn(n−2) → … → RTS1M20RTS0M1n〉 is repeatedly performed. Also, this task sequence forms a robot task cycle. In such a robot task cycle, there are two completed wafers returned to LL. Therefore, a steady-state schedule under the two-wafer backward strategy is called a two-wafer cyclic schedule.

2.2. Properties of the System

By a two-wafer backward strategy for an SACT with two-space PMs, if the robot is staying at a PM at Step i and the next robot task sequence is RTSi = 〈UDiMi(+1)LDi+1M(i+1)iUDiMi(i+1)LDi+1〉, implying that Step i + 1 should have an empty PM such that two wafers can be loaded into that PM after RTSi is performed. When starting RTSi at the PM of Step i, after UDi is executed for the first time in RTSi, the internal chamber of the PM at Step i should start to rotate such the other space occupied by a wafer rotates to the door of the PM. Then, when Mi(i+1) is executed for the first time in RTSi, the robot reaches the emptied PM at Step i + 1 and can load a wafer into the PM immediately since the PM is empty. Further, after LDi+1 is executed, the internal chamber of the PM at Step i + 1 should rotate as well, such that the empty space rotates to the door. Next, the robot should move to the PM at Step i again to unload the other wafer there. Notice that when the robot reaches the PM, the internal chamber of the PM might still be rotating, and the robot has to wait, i.e.,  A i ru  is performed. Furthermore, after UDi and Mi(i+1) are sequentially executed for the second time in RTSi, the internal chamber of the PM at Step i + 1 might still be rotating, and the robot has to wait too, i.e.,  A i + 1 rl  is performed.
It follows from the above robot task sequence analysis that  ω i ru  can be decided by comparing the time taken by the PM rotating activity and 〈Mi(i+1)(μ) → LDi+1(λ) → M(i+1)i(μ)〉, and  ω i + 1 rl  can be decided by comparing the time taken by the PM rotating activity and 〈M(i+1)i(μ) →  A i ru ( ω i ru ) → UDi(λ) → Mi(i+1)(μ)〉. Thus,  ω i ru  and  ω i rl  are calculated by Equation (1) Equation and (2), respectively.
ω i ru = max ( r ( 2 μ + λ ) ,   0 ) ,   i     N n +
ω i rl = max ( r ( ω i - 1 ru + 2 μ + λ ) ,   0 ) ,   i     N n + \ { 1 }
Similarly,  ω 1 rl  can be decided by comparing the time taken by the PM rotating activity at Step 1 and 〈M(i+1)i(μ) → UDi(λ) → Mi(i+1)(μ)〉 since LLs do not perform a rotation operation. Then, we have the following equation:
ω 1 rl = max ( r ( 2 μ + λ ) , 0 )
By Equation (1), if r − (2μ + λ) > 0, then  ω i ru  = r − (2μ + λ), for ∀i ∈  N n + . In this situation,  ω i rl  = 0 holds. If r − (2μ + λ) ≤ 0, then  ω i ru  = 0, for ∀i ∈  N n + . In this situation,  ω i rl  = 0 holds as well. Thus, we have the following equation:
ω i rl = 0 ,         i f   i N n + \ { 1 } m a x ( r 2 μ + λ ,   0 ) ,     i f   i = 1
Since r, μ, λ, and λ0 are known as constants,  ω i rl  and  ω i ru  are deterministic and can be calculated by (1) and (4).
By considering robot waiting activities, RTSi is rewritten as RTSi = 〈UDi(λ) → Mi(i+1)(μ) → LDi+1(λ) → M(i+1)i(μ) →  A i ru ( ω i ru ) → UDi(λ) → Mi(i+1)(μ) → LDi+1(λ)〉, for ∀i ∈  N n + ; RTS0 = 〈UD0(λ) → M01(μ) → LD1(λ) → M10(μ) → UD0(λ) → M01(μ) →  A 1 rl ( ω 1 rl ) → LD1(λ)〉. Notice that executing RTSi takes deterministic time, which is represented as ϑi. By (1) and (4), we have
ϑi = 4λ + 3μ + max(r − (2μ + λ), 0)
Petri nets are widely used in the modeling and analysis of discrete event systems. It consists of two fundamental components: places and transitions. These components are interconnected by directed arcs [51,52,53,54,55,56].
A Petri net can be defined as  P N = P , T , I , O , M , K , where P is a finite set of places:  P = p 1 , p 2 , , p n ; T is a finite set of transitions:  T = t 1 , t 2 , , t n P T  and  P T = I  is an input function,  I : P × T N = 0,1 , 2 , O  is an output function,  O : P × T N M : P N  is a marking that represents the numbers of tokens in places with  M 0  being the initial marking;  K : P 1,2 , 3 ,  is a capacity function in which K(p) represents the largest number of tokens that p can hold at any time. A transition  t T  in a finite capacity PN is enabled if  p P M p I p , t K p M p I p , t + O p , t . If a transition is enabled, it can fire. Firing an enabled transition  t  in marking  M  yields:  M , p M p I p , t + O p , t .
Figure 3 shows a Petri net (PN) model adopted to describe the dynamical behavior of an SACT with two-space PMs under the two-wafer backward strategy. A Petri net model is composed of places, transitions, tokens, and directed arcs. Pictorially, places are denoted by circles, i.e., “Mathematics 12 01783 i001”, and transitions are denoted by the black rectangular box “Mathematics 12 01783 i002”, and tokens are denoted by the black dot “Mathematics 12 01783 i003”. Directed arcs are used to represent the relationships between places and transitions. Detailed concepts about Petri nets can be found in [22].
In the PN model, a timed place is adopted to describe RTSi, iNn. If a token visits a place represented by RTSi, it spends ϑi time units to stay there. A timed place is used for describing M(i+1)(i−1) too, i ∈  N n + . Additionally, a timed place is added to model M1n. If a token enters such a timed place, representing the robot moving, it should stay there for μ time units. Note that by the two-wafer backward strategy, after the robot reaches a PM with two wafers at a step for unloading one of them, the processing activity of the PM might not be completed. As a result, the robot needs to stay there while waiting, and Ai, iNn, is modeled by a timed place. The time for a token staying in such a place representing Ai is ωi ≥ 0. Furthermore, place pi, iNn, in the PN model stands for Step i with p0 denoting LLs. Thus, a token in pi, i ∈  N n + , represents that a PM at Step i is performing the processing for two wafers, or the wafers have been processed, and they just stay in the PM. At Step i, if multiple parallel PMs are applied, mi tokens are put into place pi initially. Also, initially, a place representing An has a token, implying that the robot is waiting at a PM at Step n.
Transitions are used to connect places without any real meaning, as shown in Figure 3. By the transition firing sequence, a place-visiting sequence by a token can be obtained, and it is shown in Figure 4. Notice that such a place-visiting sequence just represents a robot task cycle under the two-wafer backward strategy.
For the PN model in Figure 3, once a token in the place representing An sequentially visits the places along the transition firing sequence, as shown in Figure 4, it finally returns to the place of An. At this time, a place-visiting circuit is formed. It represents a robot task cycle as well as indicates the workload of the robot. During such a robot task cycle, a token from pi, i ∈  N n + , also sequentially visits places denoting RTSi, M(i+1)(i−1), Ai−1, and RTSi−1. Then, it returns to pi. Such a place-visiting sequence forms a place-visiting circuit as well. In this place-visiting circuit, two wafers are transported to Step i + 1 from Step i, and two wafers are transported to Step i from Step i − 1. Thus, this circuit represents the workload of Step i. Additionally, there is a circuit including p0, and the places representing RTS0, M1n, and An. This circuit represents the workload of LLs. Therefore, (n + 2) circuits exist in the PN model in total.
Let φ denote the time to execute the robot task cycle, i.e., the workload of the robot. From the PN model and some previous research [49,50], we have
φ = 4 ( n + 1 ) μ + 4 ( n + 1 ) λ + ( n + 1 )   ×   max ( r ( 2 μ + λ ) ,   0 ) + i = 0 n ω i
Let Θi, iNn, be the workload of Step i. With mi parallel PMs at Step i, based on the Petri net, we have
Θ i = ( τ i + 8 λ + 7 μ + 2   ×   max ( r ( 2 μ + λ ) ,   0 ) + ω i 1 ) / m i ,   i     N n +
Θ0 = τ0 + 8λ + 7μ + 2 × max(r − (2μ + λ), 0) + ωn
where τi is the time during which two wafers are staying in a PM at Step i. Note that at Step i, i ∈  N n + , the processing time is αi, resulting in τiαi should hold. Since there is no processing activity needed at the LLs, τ0 ≥ 0 should hold.
A two-wafer cyclic schedule results from the two-wafer backward strategy. Under such a schedule, two completed wafers go back to LLs, and each step completes two wafers. Thus, from the PN model, the time taken for each circuit should be the same under the steady state, which makes Proposition 1 hold.
Proposition 1. 
For an SACT with two-space PMs, if it is operated by the two-wafer backward strategy under a steady state, Θi = φ and τi ≥ αi, fori ∈  N n + .
Notice that in Equation (6), 4(n + 1)μ + 4(n + 1)λ + (n + 1) × max(r − (2μ + λ), 0) is deterministic and  i = 0 n ω i  caused by the robot waiting is adjustable. This means that determining where and how long the robot waits is crucial in scheduling an SACT with two-space PMs with the targets of system cycle time minimization and τiαi, i ∈  N n + . Let di = τiαi, i ∈  N n + , denote the delay time of the two wafers in a PM at Step i after they are processed. It follows from (6) to (8) that without changing the value of φ, di can be decreased by increasing the value of ωi−1. With this finding, in the next section, with τiαi, i ∈  N n + , being satisfied, efficient algorithms are established to regulate the robot waiting time so as to maximize the output of the system and minimize the total wafer delay time.

3. Scheduling and Wafer Delay Time Minimization

Based on Proposition 1 and Equation (7), without changing the value of φ, the increased value of ωi−1 should equal the decreased value of τi. This implies that it is vitally important to regulate the robot’s idle time as waiting time such that an obtained schedule is optimal in terms of productivity and at the same time  i = 0 n 1 ω i  is maximized as much as possible.
From the PN model, the productivity of an SACT with two-space PMs is determined by the heaviest circuit in the net, i.e., the largest workload among all steps and the robot. Thus, it is necessary to know the lower bounds of workloads for all steps and the robot. Let φ1 denote the lower bound of the workload of the robot, and ΠiL, iNn, be the lower bound of the workload of Step i. Then, we have
φ1 = 4(n + 1)μ + 4(n + 1)λ + (n + 1) × max(r − (2μ + λ), 0)
Π iL = ( α i + 8 λ + 7 μ + 2   ×   max ( r ( 2 μ + λ ) ,   0 ) ) / m i ,   i     N n +
Π0L = 8λ + 7μ + 2 × max(r − (2μ + λ), 0)
Let Ct be the cycle time of an SACT with two-space PMs (i.e., the robot cycle time) during which there are two wafers being completed. Then, if Ct = max(φ1, ΠiL|iNn), the minimal system cycle time is achieved, i.e., the productivity is maximal. Thus, we aim to find a schedule such that Ct = max(φ1, ΠiL|iNn). Moreover, wafer delays should be reduced as much as possible. However, in some cases, eliminating the wafer delays at all steps is impossible. Thus, for each step, a priority level should be given so that the wafer delays are decreased according to the priority levels.
Let PV be a 1 × n vector in which each element is a nonnegative integer and is no greater than n. If PV(i) > PV(j), ij, it means that the wafer delay at Step i should be reduced with a higher priority than that at Step j. Let Πmax = maxiL|i ∈  N n + ). Then, for some cases, we present the following algorithm to find a schedule such that wafer delays are decreased as much as possible.
In the Algorithm 1, by Statement (3), ωi−1 = mi × ( Π m a x Π i L ), i ∈  N n + . Due to  Π m a x Π i L  ≥ 0, ωi−1 ≥ 0 holds. Therefore, ωi−1, i ∈  N n + , is correctly determined. By Statement (6) in the algorithm, ωn = Πmaxφ1 i N n + m i × ( Π m a x Π i L ) ≥ 0 due to Πmaxφ1 ≥  i N n + m i × ( Π m a x Π i L ) . Therefore, ωn is correctly determined. Also, by Algorithm 1, we have φ = φ1 i N n + m i × ( Π m a x Π i L )  + Πmaxφ1 −  i N n + m i × ( Π m a x Π i L )  =  Π m a x . This means that the system cycle time (robot cycle time) is Πmax with two wafers being completed. The flowchart for Algorithm 1 can be found in Figure 5.
Algorithm 1: For an SACT with two-space PMs operated by the two-wafer backward strategy under a steady state, if Πmaxφ1 ≥  i N n + m i × ( Π m a x Π i L ) , then ωi, iNn, is determined as follows:
(1)i = 1;
(2)While in
(3) ωi−1 = mi × (Πmax − ΠiL);
(4) i = i + 1;
(5)End
(6)ωn = Πmaxφ1 −  i N n + m i × ( Π m a x Π i L ) ;
Lemma 1. 
For an SACT with two-space PMs operated by the two-wafer backward strategy under a steady state, if Πmax − φ1  i N n + m i × ( Π m a x Π i L )  and Algorithm 1 is adopted to determine the robot waiting time, then τi = αi, fori ∈  N n + , i.e., no wafer delay exists.
Proof. 
By Algorithm 1, we have φ = Πmax. Then, by Proposition 1 and Equation (7), we have (τi + 8λ + 7μ + 2 × max(r − (2μ + λ), 0) + ωi−1)/mi = Πmax, i ∈  N n + . Thus, τi = mi ×  Π m a x − [8λ + 7μ + 2 × max(r − (2μ + λ), 0) + ωi−1] = mi × Πmax − [8λ + 7μ + 2 × max(r − (2μ + λ), 0) + mi × ( Π m a x Π i L )] = mi ×  Π i L  − [8λ + 7μ + 2 × max(r − (2μ + λ), 0)] due to ωi−1 = mi × ( Π m a x Π i L ) by Algorithm 1. Further, by Equation (10), we have τi = αi. Therefore, the lemma holds. □
By Algorithm 1 and Lemma 1, the robot idle time is Πmaxφ1, which should be assigned as the robot waiting time. Due to Πmaxφ1 ≥  i N n + m i × ( Π m a x Π i L ) , the robot waiting time can be determined so that no wafer delay exists. However, in some cases, although the robot should have idle time, the wafer delays cannot be eliminated at all steps. In this situation, the steps with higher priority levels should be given higher priority to reduce the wafer delays. Let argmax(PV) be an index such that PV(argmax(PV)) = max(PV(i)|i ∈  N n + ). If there is a tie for more than one step, then argmax(PV) should be randomly selected from them. The following algorithm is presented to reduce wafer delays in cases where the robot’s idle time is not enough.
Statement (3) in the algorithm gives the step at which the wafer delay should be reduced since it has the highest priority. By Equation (7), the wafer delay time at Step i can be decreased by setting ωi−1. Thus, Statements (4)–(10) are applied to determine the robot waiting time carefully to reduce the wafer delay time as much as possible. Specifically, if φ2mi × (Πmax − ΠiL), ωi−1 = mi × (Πmax − ΠiL) ≥ 0. Therefore, the robot waiting time determined by Statement (5) is correct. This also means no wafer delay exists at Step i, which will be shown in a lemma presented later. If φ2 < mi × (Πmax − ΠiL), ωi−1 = φ2 ≥ 0. Therefore, the robot waiting time determined by Statement (5) is correct. In this situation, at Step i, after ωi−1 is determined, some wafer delay time may still exist. Notice that φ2 ≥ 0 holds for all the time based on Statements (4), (6), and (9). Further, Statement (11) records the steps at which the wafer delays have been reduced as much as possible by setting the robot waiting time. After Statements (2)–(12) are performed, the robot idle time is totally assigned as the robot waiting time. Statements (14)–(20) are applied to determine the robot waiting time that is not yet set by Statements (2)–(12) to be zero. After ωi, iNn, is determined by Algorithm 2, we have  i = 0 n ω i  = Πmaxφ1 and φ = Πmax. Therefore, the system cycle time is Πmax, with two wafers being completed. The flowchart for Algorithm 2 can be found in Figure 6.
Algorithm 2: For an SACT with two-space PMs operated by the two-wafer backward strategy under a steady state, if 0 < Πmaxφ1 i N n + m i × ( Π m a x Π i L ) , then ωi, iNn, is determined as follows:
(1) φ2 = Πmaxφ1;
(2) While φ2 > 0
(3) i = argmax(PV);
(4) if φ2mi × (Πmax − ΠiL)
(5) ωi−1 = mi × (Πmax − ΠiL);
(6) φ2 = φ2mi × (Πmax − ΠiL);
(7) Else
(8) ωi−1 = φ2;
(9) φ2 = 0;
(10) End
(11) PV(i) = −1;
(12) End
(13) j = max(PV(i) | i ∈  N n + );
(14) While j ≥ 0
(15) i = argmax(PV);
(16) ωi−1 = 0;
(17) PV(i) = −1;
(18) j = max(PV(i) | i ∈  N n + );
(19) End
(20) ωn = 0;
Lemma 2. 
For an SACT with two-space PMs operated by the two-wafer backward strategy under a steady state, if 0 < Πmax − φ1 i N n + m i × ( Π m a x Π i L )  and Algorithm 2 is adopted to determine the robot waiting time, then τi ≥ αi, fori ∈  N n + .
Proof. 
By Algorithm 2, we have φ = Πmax. If ωi−1 is determined by Statement (5) in Algorithm 2, based on Proposition 1 and Equation (7), we have (τi + 8λ + 7μ + 2 × max(r − (2μ + λ), 0) + ωi−1)/mi = [τi + 8λ + 7μ + 2 × max(r − (2μ + λ), 0) + mi × (Πmax − ΠiL)]/mi = Πmax. Further, by Equation (10), we have τi = mi × Πmax − [8λ + 7μ + 2 × max(r − (2μ + λ), 0) + mi × (Πmax − ΠiL)] = mi × ΠiL − [8λ + 7μ + 2 × max(r − (2μ + λ), 0)] = αi. If ωi−1 is determined by Statement (8) in Algorithm 2, ωi−1 < mi × (Πmax − ΠiL). Similarly, By Equation (10), we have τi = mi × Πmax − [8λ + 7μ + 2 × max(r − (2μ + λ), 0) + ωi−1] > mi × Πmax − [8λ + 7μ + 2 × max(r − (2μ + λ), 0) + mi × (Πmax − ΠiL)] = mi × ΠiL − [8λ + 7μ + 2 × max(r − (2μ + λ), 0)] = αi. If ωi−1 is determined by Statement (16) in Algorithm 2 such that ωi−1 = 0, similarly, we have τi > αi. Therefore, the theorem holds. □
By Algorithm 2 and Lemma 2, since the robot does not have enough idle time set as waiting time, the wafer delay time cannot be totally eliminated. Nevertheless, it has been applied to reduce the wafer delay time as much as possible. Furthermore, there are some cases in which the robot is the bottleneck and no robot idle time exists to reduce the wafer delay time. The next algorithm is to identify such cases.
In this algorithm, ωi, iNn, are all determined to be zero. Therefore, the algorithm is correct. Thus, the system cycle time is φ1, with two wafers being completed.
Lemma 3. 
For an SACT with two-space PMs operated by the two-wafer backward strategy under a steady state, if Πmax < φ1 and Algorithm 3 is adopted to determine the robot waiting time, then τi > αi, fori ∈  N n + .
Proof. 
By Algorithm 2, we have  i = 0 n ω i  = 0, leading to that φ = φ1. Then, based on Proposition 1 and Equation (7), we have (τi + 8λ + 7μ + 2 × max(r − (2μ + λ), 0) + ωi−1)/mi = [τi + 8λ + 7μ + 2 × max(r − (2μ + λ), 0)]/mi = φ1. Then, with φ1 > Πmax = maxiL| i ∈  N n + ), we have τi = mi × φ1 − [8λ + 7μ + 2 × max(r − (2μ + λ), 0)] > mi × Πmax − [8λ + 7μ + 2 × max(r − (2μ + λ), 0)] ≥ mi × ΠiL − [8λ + 7μ + 2 × max(r − (2μ + λ), 0)] = αi. Therefore, the lemma holds. The flowchart for Algorithm 3 can be found in Figure 7. □
Algorithm 3: For an SACT with two-space PMs operated by the two-wafer backward strategy under a steady state, if Πmax < φ1, then ωi, iNn, is determined as follows:
(1) i = 0;
(2) While in
(3)     ωi = 0;
(4)     i = i + 1;
(5) End
By Lemma 3, some wafer delay time may exist at each step. The reason for this phenomenon is that the time to execute the robot task cycle is quite longer than the lower bound of the workload at the bottleneck step. This makes the robot the bottleneck. Thus, no robot idle time exists to be waiting time so as to reduce the wafer delay time. Up to now, we have presented three algorithms to find schedules for all cases under the two-wafer backward strategy. The next question is whether such schedules are optimal. Theorem 1 answers this question.
Theorem 1. 
For an SACT with two-space PMs, if its schedule is obtained by one of Algorithms 1−3, then the schedule is optimal in terms of productivity.
Proof. 
For the cases that are scheduled by Algorithms 1 and 2, we have φ = Πmax. Assume that there is a steady state schedule under the two-wafer backward strategy such that φ < Πmax. With the loss of generality, let Step k be the bottleneck step such that Πmax = ΠkL. Then, by Proposition 1 and Equation (7), we have τk = mk × φ − [8λ + 7μ + 2 × max(r − (2μ + λ), 0) + ωk-1] < mk × ΠkL − [8λ + 7μ + 2 × max(r − (2μ + λ), 0)] = αk. This implies that the wafer processing activity is not completed at Step k. Therefore, there does not exist a steady-state schedule under the two-wafer backward strategy such that φ < Πmax. Notice that if the system is scheduled by Algorithm 3, we have φ = φ1. This means that the robot task cycle time cannot be shortened anymore. Therefore, the theorem holds. □
In practice, in order to ensure the consistency of the quality of all wafers, the timing patterns of all wafers should be kept the same in terms of the wafer delay time at each step. Under a steady state, with the schedules obtained by Algorithms 1–3, for all wafers to be processed in the system, the timing patterns of the wafer delay time at each step are the same. Nevertheless, it is necessary to keep such timing patterns during the initial and final transient processes. To do so, virtual wafers are introduced into the system during the initial and final transient processes.
At the initial transient process, assume that each PM has two virtual wafers being processed. Then, according to the processing parameters, one of the Algorithms 1–3 is applied to operate the system. Further, under the initial transient process, the system is operated in a steady state. During each robot task cycle, two virtual wafers leave the system, and two real wafers enter the system. When all virtual wafers leave the system, the system is full of real wafers, so the system reaches a steady state. If the system goes through the final transient process, it is still operated in a steady state. However, each time the robot unloads a wafer from LLs, this wafer should be a virtual one. Once the system is full of virtual wafers, it is actually emptied, i.e., the final transient process ends. In this way, one can ensure that the timing patterns of wafer delay time at each step are the same as those at the initial and final transient processes.

4. Case Studies

The applications of the proposed method are demonstrated by several examples below. The time unit is second, and it is omitted in the following cases:
Example 1. 
For an SACT, SPWFP = (1, 2, 1). This wafer flow pattern indicates that after raw wafers enter the tool, three operations should be sequentially completed. Also, in the tool, there are four PMs named PM1, PM2, PM3, and PM4. PM1 is used to complete Operation 1, PM2 and PM3 are parallel process modules used for completing Operation 2, and PM4 is used to complete Operation 3. Therefore, after a raw wafer enters the tool, it should be delivered to PM1 for processing first, then moved to PM2 or PM3 for processing, and finally moved to PM4 for processing. Once it is unloaded from PM4 by the robot, it should be returned to LLs. This also implies that all operations are completed. Additionally, each operation is called a processing step. Thus, Step i represents Operation i, {1, 2, 3}. Note that the processing time at Steps 1–3 is α1 = 145.0, α2 = 280.0, and α3 = 170.0. The rotation time of the internal chamber of PMs is r = 8.0. The robot’s task time is λ = 3.0 and μ = 2.0. By Equations (1) and (4), we have  ω 1 ru  =  ω 2 ru  =  ω 3 ru = ω 1 rl  = 1.0 and  ω 2 rl  =  ω 3 rl  = 0.0 because r = 8.0 > 2μ + λ. Further, by Equations (9) and (10), we have φ1 = 84.0, Π1L = 185.0, Π2L = 160.0, and Π3L = 210.0. Thus, the conditions given in Algorithm 1 and Lemma 1 are satisfied, and an optimal schedule can be obtained by setting ω0 = 25.0, ω1 = 100.0, ω2 = 0.0, and ω3 = 1.0. The system cycle time is Ct = 210.0. Also, the delay time at each step is totally eliminated. However, if the SACT is operated by a backward and earliest starting strategy (BESS), by simulation, under the steady state, we have ω0 = ω1 = ω2 = 0.0 and ω3 = 126.0, resulting in d1 = 25.0, d2 = 100.0, and d3 = 0.0. Such wafer delays may cause quality problems for wafers. The Gantt chart of Example 1 can be seen in Figure 8.
Example 2. 
For an SACT, SPWFP = (1, 1, 1). This wafer flow pattern is similar to the one in Example 1. The difference is that each step has only one PM. Also, PM1, PM2, and PM3 are used to complete operations (wafer processing) at Steps 1 and 3, respectively. Then, after a raw wafer enters the tool, it should be delivered to PM1 for processing first, then moved to PM2 for processing, and finally moved to PM3 for processing. Once it is unloaded from PM3 by the robot, it should be returned to loadlocks. This also implies that all operations are completed. The processing time at Steps 1–3 is α1 = 90.0, α2 = 120.0, and α3 = 100.0. The rotation time of the internal chamber of PMs is r = 6.0. The robot’s task time is λ = 4.0 and μ = 2.0. By Equations (1) and (4), we have  ω 1 ru  =  ω 2 ru  =  ω 3 ru = ω 1 rl  =  ω 2 rl  =  ω 3 rl  = 0.0 because of r = 6.0 < 2μ + λ. Further, by Equations (9) and (10), we have φ1 = 96.0, Π1L = 136.0, Π2L = 166.0, and Π3L = 146.0. For this example, the conditions given in Algorithm 1 and Lemma 1 are satisfied. Then, an optimal schedule can be obtained by Algorithm 1 by setting ω0 = 30.0, ω1 = 0.0, ω2 = 20.0, and ω3 = 20.0. The system cycle time is Ct = 166.0. Similar to Example 1, the wafer delay time at all steps is totally eliminated. However, if the SACT is operated by BESS, by simulation, under the steady state, we have ω0 = ω1 = 0.0, ω2 = 20.0, ω3 = 50.0, resulting in d1 = 30.0, d2 = 0.0, and d3 = 0.0. The Gantt chart of Example 2 can be seen in Figure 9.
Example 3. 
For an SACT, SPWFP = (1, 1, 1, 1). This wafer flow pattern indicates that there are four steps to complete wafers in the tool. Steps 1–4 are served by PM1, PM2, PM3, and PM4, respectively. Then, after a raw wafer enters the tool, it should be sequentially delivered to PM1, PM2, PM3, and PM4 for processing. The processing time at Steps 1−4 is α1 = 80.0, α2 = 100.0, α3 = 85.0, and α4 = 90.0. The rotation time of the internal chamber of PMs is r = 5.0. The robot’s task time is λ = 3.0 and μ = 2.0. By Equations (1) and (4), we have =  ω 1 ru  =  ω 2 ru  =  ω 3 ru  =  ω 4 ru  =  ω 1 rl  =  ω 2 rl  =  ω 3 rl  =  ω 4 rl  = 0.0 because of r = 5.0 < 2μ + λ. Further, by Equations (9) and (10), we have φ1 = 100.0, Π1L = 118.0, Π2L = 138.0, Π3L = 123.0, and Π4L = 128.0. Then, the conditions given in Algorithm 2 and Lemma 2 are satisfied. Assume that PV = [4, 3, 2, 1]. Thus, an optimal schedule is obtained by Algorithm 2 by setting ω1 = ω4 = 0.0, ω0 = 20.0, ω2 = 15.0, and ω3 = 3.0. The system cycle time is Ct = 138.0. The Gantt chart of Example 3 can be seen in Figure 10.
In this example, Step 2 is the bottleneck, and it does not have the wafer delay time. Also, by the proposed method, the delay time at Steps 1 and 3 has been totally eliminated. At Step 4, there still exists the wafer delay time, which is 7.0. If the SACT is operated by BESS, by simulation, under the steady state, we have ω0 = ω1 = 0.0, ω2 = 15.0, ω3 = 10.0, and ω4 = 13.0, resulting in d1 = 20.0, d2 = d3 = d4 = 0.0. Due to PV = [4, 3, 2, 1], the wafer delay at Step 1 is most expected to be reduced. However, by BESS, the wafer delay time is 20.0. Also, the total wafer delay time by BESS is 13.0 times greater than that by the proposed method.
Example 4. 
For an SACT, SPWFP = (1, 2, 1). This wafer flow pattern is the same as the one in Example 1. In this example, the processing time at Steps 1–3 is α1 = 50.0, α2 = 120.0, and α3 = 65.0. The rotation time of the internal chamber of PMs is r = 5.0. The robot’s task time is λ = 3.0 and μ = 2.0. By Equations (1) and (4), we have =  ω 1 ru  =  ω 2 ru  =  ω 3 ru  =  ω 1 rl  =  ω 2 rl  =  ω 3 rl  = 0.0 because of r = 5.0 < 2μ + λ. Further, by Equations (9) and (10), we have φ1 = 80.0, Π1L = 88.0, Π2L = 79.0, and Π3L = 103.0. The conditions given in Algorithm 2 and Lemma 2 are satisfied. Assume that PV = [2, 4, 3, 1]. Thus, an optimal schedule is obtained by Algorithm 2 by setting ω0 = ω2 = ω3 = 0.0 and ω1 = 23.0. The system cycle time is Ct = 103.0. The Gantt chart of Example 4 can be seen in Figure 11.
In this example, Step 3 is the bottleneck, and it does not have the wafer delay time. Since Step 2 has the highest priority, all robot idle time is assigned to be waiting time ω1 = 23.0 by Algorithm 2, such that the wafer delay time at Step 2 is decreased to 25.0. Moreover, in Step 1, the delay time is 15.0, which cannot be eliminated. Thus, the total delay time at all steps is 40.0.
If the SACT is operated by BESS, by simulation, under the steady state, we have ω0 = ω1 = ω2 = 0.0 and ω3 = 23.0, resulting in d1 = 15.0, d2 = 48.0, and d3 = 0.0. Thus, the total wafer delay time reaches 63.0 by BESS. Therefore, by the proposed method, the total wafer delay time can be reduced by 36.5%. Notice that due to PV = [2, 4, 3, 1], the wafer delay at Step 2 is most expected to be reduced. By the proposed method, the wafer delay time at Step 2 is decreased to 25.0, while the wafer delay time is 48.0 by BESS. Therefore, the example shows that the proposed method can effectively reduce the wafer delay time according to the priorities of each step given in advance.
Example 5. 
For an SACT, SPWFP = (1, 1, 1). This wafer flow pattern is the same as the one in Example 2. In this example, the processing time at Steps 1–3 is α1 = 55.0, α2 = 67.0, and α3 = 62.0. The rotation time of the internal chamber of PMs is r = 10.0. The robot’s task time is λ = 6.0 and μ = 3.0. By Equations (1) and (4), we have  ω 1 ru  =  ω 2 ru  =  ω 3 ru = ω 1 rl  =  ω 2 rl  =  ω 3 rl  = 0 because of r = 10.0 < 2μ + λ. Further, by Equations (9) and (10), we have φ1 = 144.0, Π1L = 124.0, Π2L = 136.0, and Π3L = 131.0. The conditions given in Algorithm 3 and Lemma 3 are satisfied. Thus, an optimal schedule is obtained by Algorithm 3 by setting ω0 = ω1 = ω2 = ω3 = 0.0. The system cycle time is Ct = φ1 = 144.0. Also, in this case, there is no robot idle time assigned as waiting time for the elimination of wafer delays. The Gantt chart of Example 5 can be seen in Figure 12.

5. Conclusions

Based on the five cases, it is evident that wafer delay time has been reduced, which also demonstrated that our algorithm effectively reduces wafer delay time. The research results clearly showed that by controlling the scheduling of the robot waiting time and optimizing the rotation sequence of the internal processing chambers, the wafer delay time can be significantly reduced.
With two-space PMs, the rotation operations of the internal chambers of PMs may delay the robot’s task time. It implies that to schedule SACTs with two-space PMs, it should carefully schedule the robot task by considering the rotation operations of the internal chambers of PMs. Also, it is necessary to analyze how the wafer delay time is affected by the robot tasks and the rotation operations of the internal chambers of PMs. To do so, this work presents a two-wafer backward strategy under which the properties of the system are analyzed. It has been found that the wafer delay time can be reduced by carefully regulating the robot waiting time. Thus, efficient algorithms are established to determine the robot waiting time so that optimal schedules can be found and, at the same time, the total wafer delay time can be minimized. Finally, the effectiveness and efficiency of the proposed method are demonstrated by examples.
In semiconductor manufacturing, multi-cluster tools are widely adopted for wafer fabrication in physical vapor deposition processes. The future work can cope with the multi-cluster tool scheduling problem by considering multiple-space PMs.

Author Contributions

Conceptualization, C.Z., S.Z. (Siwei Zhang) and J.L.; methodology, C.Z., S.Z. (Siwei Zhang), S.Z. (Shan Zeng) and L.G.; software, S.Z. (Shan Zeng); validation, L.G.; formal analysis, C.Z., S.Z. (Shan Zeng) and L.G.; resources, J.L.; data curation, S.Z. (Siwei Zhang), L.G. and J.L.; writing—original draft preparation, C.Z.; writing—review and editing, L.G.; supervision, S.Z. (Siwei Zhang); project administration, S.Z. (Siwei Zhang) and J.L. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Science and Technology Development Fund (FDCT), Macau SAR (File Nos. 0015/2020/AMJ, 0018/2021/A1, 0083/2021/A2 and 0011/2023/RIA1), China.

Data Availability Statement

All data are contained within the article.

Conflicts of Interest

Author Jie Li was employed by the company IKAS Industries Company, Ltd. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

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Figure 1. (a) an SACT; (b) a DACT.
Figure 1. (a) an SACT; (b) a DACT.
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Figure 2. An SACT with multiple-space PMs.
Figure 2. An SACT with multiple-space PMs.
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Figure 3. A PN model of an SACT under the two-wafer backward strategy.
Figure 3. A PN model of an SACT under the two-wafer backward strategy.
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Figure 4. A place-visiting sequence demonstrates a robot task cycle.
Figure 4. A place-visiting sequence demonstrates a robot task cycle.
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Figure 5. The flowchart for Algorithm 1.
Figure 5. The flowchart for Algorithm 1.
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Figure 6. The flowchart for Algorithm 2.
Figure 6. The flowchart for Algorithm 2.
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Figure 7. The flowchart for Algorithm 3.
Figure 7. The flowchart for Algorithm 3.
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Figure 8. The Gantt chart for Example 1.
Figure 8. The Gantt chart for Example 1.
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Figure 9. The Gantt chart for Example 2.
Figure 9. The Gantt chart for Example 2.
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Figure 10. The Gantt chart for Example 3.
Figure 10. The Gantt chart for Example 3.
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Figure 11. The Gantt chart for Example 4.
Figure 11. The Gantt chart for Example 4.
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Figure 12. The Gantt chart for Example 5.
Figure 12. The Gantt chart for Example 5.
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Table 1. The actions of the robotic arm and their corresponding timings.
Table 1. The actions of the robotic arm and their corresponding timings.
SymbolActionsTime
UDiA robot unloading task at a PM of Step i, i ∈  N n + .λ
LDiA robot loading task at a PM of Step i, i ∈  N n + .λ
Mi,jA robot moving task from Step i to j, i ∈  N n + , j ∈  N n + .μ
  R i u The rotation activity of a PM at Step i after Ui is performed at the PM, i ∈  N n + .r
  R i l The rotation activity of a PM at Step i after Li is performed at the PM, i ∈  N n + .r
AiA robot task to wait for the completion of two wafers in a PM of Step i, i ∈  N n + .ωi
  A i ru A robot task to wait for the rotation of a PM before Ui2.   ω i ru
  A i rl A robot task to wait for the rotation of a PM before Li2   ω i rl
τi1The sojourn time of Wafer-i1 at a PM at Step i, i ∈  N n +  τi1αi
τi2The sojourn time of Wafer-i2 at a PM at Step i, i ∈  N n +  τi2αi
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MDPI and ACS Style

Zou, C.; Zhang, S.; Zeng, S.; Gu, L.; Li, J. Wafer Delay Minimization in Scheduling Single-Arm Cluster Tools with Two-Space Process Modules. Mathematics 2024, 12, 1783. https://doi.org/10.3390/math12121783

AMA Style

Zou C, Zhang S, Zeng S, Gu L, Li J. Wafer Delay Minimization in Scheduling Single-Arm Cluster Tools with Two-Space Process Modules. Mathematics. 2024; 12(12):1783. https://doi.org/10.3390/math12121783

Chicago/Turabian Style

Zou, Chengyu, Siwei Zhang, Shan Zeng, Lei Gu, and Jie Li. 2024. "Wafer Delay Minimization in Scheduling Single-Arm Cluster Tools with Two-Space Process Modules" Mathematics 12, no. 12: 1783. https://doi.org/10.3390/math12121783

APA Style

Zou, C., Zhang, S., Zeng, S., Gu, L., & Li, J. (2024). Wafer Delay Minimization in Scheduling Single-Arm Cluster Tools with Two-Space Process Modules. Mathematics, 12(12), 1783. https://doi.org/10.3390/math12121783

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