A Switched Capacitor Memristor Emulator Using Stochastic Computing

Due to the increased use of memristors and their many applications, the use of emulators has grown in parallel to avoid some of the difficulties presented by real devices, such as variability and reliability. In this paper, we present a memristive emulator designed using a switched capacitor (SC), that is, an analog component/block and a control part or block implemented using stochastic computing (SCo) and therefore fully digital. Our design is thus a mixed signal circuit. Memristor equations are implemented using stochastic computing to generate the control signals necessary to work with the controllable resistor implemented as a switched capacitor.


Introduction
Leon Chua defined the memristor theoretically in 1971 [1]. The term "memristor" is constructed from the words memory and resistor and completes the relationships provided by the capacitor, inductor and resistor between current, voltage, flux and charge. Leon Chua introduces, therefore, this fourth passive component to complete the set, proposing that the memristor is defined by a nonlinear relationship between charge and flux. However, it was not until 2008 that it could be implemented [2]. Since then, its use has been increasing and its fields of application have also increased. It is a promising but very recent device, which implies that there are many studies that must be carried out to understand well the operating mechanisms and develop new technologies to avoid some of the problems presented, such as the variability and life time.
It is because of the problems that real devices present that the development of memristive emulators is booming.
Emulators reproduce the operating characteristics of the memristor by eliminating the aforementioned problems, therefore allowing for the development of more complex and reliable systems [3]. The memristor behavior which is imitated can be an ideal memristor or actual device, depending on the implementation. If we are focused on their field of application, emulators have different characteristics, although there are two main lines of study: analog emulators and digital emulators.
Many works develop fully analog emulators; for example, in [4], a memristive system was implemented and results demonstrated that it was very easy to fabricate in academic laboratories through classical electrical components from circuit theory. In [5], an emulator is implemented with transistors, resistors and diodes, and it operates in passive mode. Other examples like [6,7] use amplifiers in their models. In general, analog systems need more power consumption. The volatility of the system is worse than in the digital case, but they present a good implementation of the variable resistance with which the emulator memristance is described.
On the other hand, digital memristor systems emulators can be implemented in FPGAs (or ASICS) [8][9][10]. Their main advantages are that they present short simulation times and better control of the behaviour of the emulator. However, their variable resistance implementation poses a problem. In digital emulators, it is much easier to define the model, but precision is lost (limited number of bits), and there is usually a need for more computational power than the analog equivalent. For a review of different state-of-the-art emulators, the interested reader can see, for instance, [3] or [11].
For many years, the scientific community has been greatly interested in developing different computer architectures. It seeks, among other things, to change the structure of serial calculations and perform operations in parallel. A high degree of parallelism allows for faster execution using less complex elements or using approximations even if precision is lost. Due to the large number of data and operations that must be carried out by current computer systems, the well-known Von Neumann architecture [12] is not a good choice to use due to its high consumption of time of computation and energy.
One of the alternatives, as mentioned above, is to use non-deterministic computing methods, including stochastic computing (SCo). Its main differentiating trait is that it uses random variables to represent quantities. Probabilistic logic was introduced by Von Neumann in 1956 [13], expanding the previous work of R.S. Pierce in 1952 [14]. However, it was not until the 1960s that progress in electronics and computing allowed for its actual implementation [15,16]. Nowadays, there are many proposals in the literature using this approach in different fields: image processing [17][18][19], data compression [20], arithmetic calculations [21,22], control [23], and A/D conversion [24], to mention just a few.
In this framework, the representation of data is performed in a probabilistic way using Boolean quantities that are switched in random way during a time. Numbers are represented as random (0,1) vectors. The average value of these vectors is correlated to the number represented [25]. These vectors are referred to as stochastic logic number (SLN). This representation makes it possible to reduce the area occupied, since complex functions occupying a large space such as multiplication can be reduced to a single logic gate with great savings in terms of power and area [26]. To create the SLN, a random number generator (RNG) is needed, and for the designers, it is a challenge to use the lowest number of these so as to not increase the area of the chip. The number of RNGs is related to the fact that the operations in SCo are different depending on the encoding of the number and if the signals are correlated or not (statistical dependent or not). To guarantee uncorrelated SLNs, different RNGs must be employed to generate each stochastic signal.
In this work, we design, simulate and implement a mixed-signal memristor emulator, improving the version presented in [27]. Specifically, in this paper, we improve the theoretical discussion, including the description of the stochastic blocks, and we also present some experimental results. The proposed emulator consists of two blocks, taking advantage of the best features of each design part. In the analog block, a switched capacitor is used to implement a variable resistor, and in the digital one, that is, the control block, we use stochastic computation. The simulation is done with Matlab to implement the functionality of both the analog block, similar to that used in [28], and of the control block. For the experimental implementation, a quadruple analog switch HCF4066FE and a DE0-Nano FPGA have been used. This paper is organized as follows: the next section describes the generalities of memristors, memristor emulators and stochastic logic operations; in the third section, the model is developed and simulated; the fourth section deals with the experimental implementation; and, finally, the last section discusses the work.

Memristor Mathematical Description
A memristor is a two-terminal device whose resistance (conductance) can change its value when a voltage or current signal is applied. In addition, the value of the resistance (conductance) of the device also depends on its past history and is named memristance (M) (memconductance (G)). The concept of the memristor was extended by Chua in 1976 to memristive systems to explain the behavior of observed systems [29], for instance, in nature. Nowadays the classification of memristors includes ideal, generic and extended memristor [30].
The most general class is the extended memristor, which includes the others. The dynamic of this class is described using internal variables that determine the internal state of the memristor; these variables, can be for example, temperature or geometrical parameters, depending on the system. The memristor can be voltage-or current-controlled, depending on the input source. On the other hand, in [31], Corinto et al. proposed a mathematical description in the charge flux domain instead of the voltage and current domain. We use for our emulator the equations describing a voltage-controlled extended memristor in the charge flux domain. These are: The memconductance (G), which can be nonlinear, is the inverse of the memristance of the device M, v is the voltage between its terminals, i is the current, φ is the flux (i.e., the first momentum of voltage), and x represents other possible state variables.
Finally, it is also important to mention that the memristors present some characteristic fingerprints distinguishing those of other dynamic systems [31,32]:

1.
As Leon Chua noted in [33]: "If it's NOT pinched, it's NOT a memristor". The i-v curve obtained when a periodic signal with zero DC component (voltage or current) is applied to the memristor shows a pinched (at the (v = 0, i = 0) point) hysteresis loop; 2.
The area of the hysteresis loop should tend to zero for higher frequencies, as noted in [31]. The behavior at low frequencies depends on the specifics of the memristor, and there may even exist a frequency where the loop area is maximum [3].
On the other hand, the emulator function must be to mimic the memristor behavior; this is to show it fingerprints. The emulator can be implemented in analog, digital or mixed formats. It is crucial that the circuit implements, among others, the internal state variables, (vector x) in Equations (1) and (2). These internal variables must be included as electrical variables in the emulator and are assumed to be isolated from a direct interaction with the outside. They are used, together with the electrical variables (i.e. voltage and flux), to calculate the value of the equivalent memconductance (G) or memristance (M).
Notice that we have implemented the ideal definition of a memristor, with a simple relationship between memristance and flux. Other models, even those oriented to the simulation of actual physical systems as, for instance, in [34][35][36], could also be implemented. The main difference of this case with the one presented here would be the implementation of the non-basic mathematical operations. This could be done using, for instance, the different circuits proposed in [37][38][39] for division and the associated square root calculation, or in [40] for arbitrary function approximation.

Stochastic Logic Operations
There are four methods that are used to encode numbers in SCo: unsigned classical stochastic encoding (UCSE), signed classical stochastic encoding (SCSE), unsigned extended stochastic encoding (UESE) and signed extended stochastic encoding (SESE) [41,42]. Implementation of different functions strongly depends on the chosen encoding. As an example, when using UCSE, an AND gate is used to implement the product of two inputs, while a XNOR gate performs that operation when using the SCSE encoding, as shown in Figure 1. Moreover, the same logical gate can perform different operations depending on whether the random signals generated are correlated or not. As an example, with USCE encoding, a two-inputs AND gate is used to implement a multiplication for uncorrelated inputs, while it provides the minimum value of the two inputs if they are correlated. In the present work, we will be using SCSE, and, thus, our numbers will lay in the real (−1..1) domain. Thus, multiplication requires the use of an XNOR gate. Performing an addition is slightly more complex, because numbers with a probability higher than one cannot be represented, and we may need to add 1 + 1 = 2. Thus, it is better to implement an alternate form as (x + y)/2, which at most will output a value of 1. This operation is usually implemented using a multiplexer, as shown in Figure 2a, where the p (0.5) means a signal with a probability of 0.5 to be '1' or '0'. This signal can be generated using one of the bits from the RNG, thus needing no additional circuitry. The same gate is used for the (0..1) and the (−1..1) domains. Other more complex operations (division [23], square roots [23], etc.) may also be found in the literature, but are not presented here for the sake of clarity. Finally, the conversion of a number encoded as a classical number can be translated to a stochastic representation using the schema presented in Figure 2.

Theoretical Design
As mentioned above, our system has been implemented in two parts [27,28]. First, we implemented an analog system including the switched capacitor module (SC), as shown in Figure 3, whose equivalent resistance R eq is described by Equation (4). In this case, both control external signals S 1 and S 2 are equal, with a lag of 180 deg. [43]. The second part is a digital module implementing the control part in stochastic logic, as will be discussed below. T and f s are the period and the frequency of the controlling signal S 1 and S 2 , D is the duty cycle with values between 0 and 1, C is the capacitance value and τ is the time constant, that is, R tot C where C is the capacitor and R tot is the total resistance of the circuit taking into account the parasitic ones.
For our design, in the charge flux domain, it is necessary to calculate the flux from the voltage of the terminals of the SC as a first step. Once this is done, then the relationships between flux and charge are used to obtain the duty cycle (D) that varies the equivalent resistance of the SC. The digital block is the responsible for all these steps.
For this purpose, a series of approximations shall be done to Equation (4). The conductance (G) (G = 1/R eq ) can be rewritten as: where x = DT/τ. The use of a first order Taylor expansion of tanh(x/2) allows us to get a simpler expression. For this, it is necessary to take into account that the decay time of the system is much longer than the control signal period. Thus, we can obtain a simpler equation describing the conductance G: It is important to notice that this last equation implies that conductance is linearly dependent on the duty cycle D.
To calculate the flux, the digital block converts each voltage terminal of the SC (v a and v b in Figure 3) to non-correlated random values. Then, the corresponding value v a − v b is accumulated into a counter, which acts as the integrator. Notice that since we are using stochastic computing, this up/down counter needs to count only one up (v a > v b ), one down (v a < v b ), or remain the same (v a = v b ). To implement the memristor device, it is necessary to use an equation to describe the relationship between flux and charge. In this work the simplest relation is used: where M is a constant. This equation does not include any internal variables. Applying the fourth derivative of the equation, the conductance is: Matching Equations (6) and (8), the relation between the duty cycle and flux is: K is therefore a constant value.
To control the analog block, it is the SC; therefore, the duty cycle (D) must be used. The duty cycle is calculated by the digital block from φ according to Equation (9) as a stochastic value. To use it, the average value of D is calculated to determine R eq with Equation (4).
The emulator block design scheme including the two parts of the design, analog and digital, is shown in Figure 4. The part corresponding to the digital block implemented in stochastic computing is shown as a circuit in Figure 5.

Simulation Results
In order to be considered as a memristor, the emulator must present two characteristic fingerprints [3,32,33]: (1) a pinched loop (2) whose area changes with frequency. Figure 6 presents the i − v of the emulator under inputs of different frequency using 16 bits for the stochastic representation. It is apparent from this figure that the curves are pinched at the origin and that the loop area changes with frequency. Thus, we can consider that the two fingerprints are present. Because of the way it is constructed, the emulator reaches a saturation for the conductance. This is due to the maximum value of D = 1, and can be clearly seen at low frequencies, where the maximum value of flux is reached faster. This may also be seen in Figure 7, where the behavior of the Q versus φ near the origin is quadratic, as can be expected from (7), but it is also seen that its behavior changes to linear after a maximum value for D = 1 is reached.
It has to be noted that there is a small noise present caused by the stochastic nature of the system, as discussed above. This noise nearly disappears in the saturation, since the counter is practically constant, even though a small ripple is present caused by the stochastic internal behavior. This noise is greatly reduced in the charge and flux domain (Figure 7, because of the integration. Finally, the current signal for different frequencies is shown in Figure 8. As can be seen there, the maximum conductance (related to the maximum value of the current) is lower for higher values of frequency, as expected.

Experimental Setup
In order to test the proposed circuit, we have implemented a setup similar to that of [28]. We have used a quadruple analog switch HCF4066FE driven by a DE0-Nano FPGA. The analog switch has a working voltage between 0.5 V to 22 V and can switch at a maximum frequency of 25 kHz when the power supply is 3.3 V. The FPGA generated the control signals S 1 and S 2 using 2 of its 3.3 V digital output pins. Additionally, we have also used a 1 kΩ shunt resistor, along with a 15 µF capacitor. The implemented circuit is shown in Figure 9. The conversion from analog to stochastic was performed by first converting from analog to digital using two of the on-board available A/D and then converting this digital value into stochastic, as described above. We have used 16 bits for the stochastic representation, and the needed random numbers were created using a public implementation of the Mersenne twister algorithm [44]. An AFG320 arbitrary signal generator was used to generate the input signal, while two oscilloscopes were used to monitor the full system. An oscilloscope monitored the control signals of the HCF4066FE, while the other oscilloscope was used to monitor the voltage through the shunt resistance of 1 kΩ to obtain the current and also the input voltage, defined as the difference between the two input terminals.

Experimental Results
The system has been tested using different input frequencies: 100, 200 and 400 Hz. The internal behaviour of the circuit is depicted in Figures 10 and 11, which depict, respectively, the control signals S 1 and S 2 in one of these cases and the waveform corresponding to the three least significant bits of the counter.  The temporal behavior of the current in these three cases is shown in Figure 12. The currents are clearly nonlinear because of memory: if they were nonlinear due to other effects, then they would be symmetrical, which they are not. In addition, they are showing a dependence on the frequency, as expected for a memristor.
100Hz.  The experimental I-V loops are depicted in Figure 13. On the left figure, the three experimental I-V curves for the corresponding frequencies in Figure 6 (simulations) appear, while the right picture shows an oscilloscope snapshot in the typical case of a 400 Hz driving sine voltage. It is apparent that, in all cases, the experimental fingerprint of a memristor, i.e., the pinched loop [33], is clearly demonstrated. This means that the device has a resistive behavior (it is pinched, which means no current when no voltage is applied), and that this resistance has a memory effect (there is a loop, which means that there are two possible values of the resistance and, hence, the current, for each voltage input value). Finally, it has to be noted that the area of the loop changes with frequency, with the higher area corresponding to higher frequencies. This is caused by the saturation of the internal counter that corresponds to the flux integral (Equation (3) and Figure 5), which leads to a linear behaviour once the maximum value is reached.

Discussion
As discussed above, the design and implementation of memristor emulators is an active research field. In this paper, we have made a contribution to this area by presenting the design, simulation, and experimental implementation of such an emulator. Our proposal is based on using switched capacitors to implement the variable resistor and on using stochastic computing to implement the control part.
The switched capacitor block has been implemented using standard off-the-shelf components with a maximum switching frequency of 25 kHz. The control signals at this frequency are generated inside the control block, which has been implemented into a DE0-nano FPGA. The FPGA reads the analog inputs (the input voltage of the analog block) using its built-in AD converters.
As a first step, we have shown using MATLAB simulation that the design is sound and can implement a system showing the expected fingerprints of a memristor: a closed loop, pinched at the origin. Finally, we have experimentally implemented the design. This actual implementation has been tested using sinusoidal waveforms of different frequencies, and it has behaved as expected. The system shows the memristor fingerprints with noise induced by the switching, as expected.
Thus, the proposed emulator has been shown to perform with its expected behavior, being a promising alternative to be implemented as an IP block into IC designs, since it is a very simple design requiring a lower number of digital gates than similar designs using conventional arithmetic implementations. This implementation would allow the increase of the limiting factor of the switching frequency at 25 kHz caused by the use of a discrete component, and would also proportionally increase the working frequency of the emulator. Funding: Some of the authors wish to acknowledge support from the DPI2017-86610-P and TEC2017-84877-R projects awarded by the MICINN, as well as the partial support by the FEDER program.

Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.