Monolithic Integrated High Frequency GaN DC-DC Buck Converters with High Power Density Controlled by Current Mode Logic Level Signal

: Integration is a key way to improve the switching frequency and power density for a DC-DC converter. A monolithic integrated GaN based DC-DC buck converter is realized by using a gate driver and a half-bridge power stage. The gate driver is composed of three stages (amplitude ampliﬁer stage, level shifting stage and resistive-load ampliﬁer stage) to amplify and modulate the driver control signal, i.e., CML (current mode logic) level of which the swing is from 1.1 to 1.8 V meaning that there is no need for an additional bu ﬀ er or preampliﬁer for the control signal. The gate driver can provide su ﬃ cient driving capability for the power stage and improve the power density e ﬃ ciently. The proposed GaN based DC-DC buck converter is implemented in the 0.25 µ m depletion mode GaN-on-SiC process with a chip area of 1.7 mm × 1.3 mm, which is capable of operating at high switching frequency up to 200 MHz and possesses high power density up to 1 W / mm 2 at 15 V output voltage. To the authors’ knowledge, this is the highest power density for GaN based DC-DC converter at the hundreds of megahertz range.


Introduction
The increasing requirements of power consumption, high power density and high operational frequency of modern applications have been appealing for converters with much smaller size and higher switching frequency. The demanding for a reduced converter volume is stimulated, especially, by the information technology applications where the rapid development of integrated circuit technology had aroused more compact systems with higher power dissipation [1]. A small volume means high power density which is equivalent to greater design freedom, lower installation cost and more system robustness. Traditional DC-DC converters are mostly implemented in the process of Si MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with extremely low R ON (on-state resistance) and high efficiency performance over hundreds of kilohertz [2][3][4][5][6][7] However, they can not operate at very high switching frequency with desirable power density due to the large parasitic capacitors [8]. Under such circumstances lots of efforts have been put in GaN based switching DC-DC converters [9,10] for higher operating frequency, breakdown voltage and power density performance comparing to the counterparts of Si devices [11,12].
For the GaN based switching DC-DC converter, depletion-mode devices usually have lower ON-resistance and smaller parasitic capacitance [13], which is more suitable for high frequency and high power density demanding converters. To further use those merits, it is necessary to realize full integration of the DC-DC converter containing the power switching stage and gate driver. Then the size of the converter chips as well as the parasitic capacitance coming from the devices or introduced by the external package can be dramatically decreased. With discrete devices, Miguel R et al. [9] illustrated a high efficiency demonstrator which can operate at 10-40 MHz switching frequency, Nicolas et al., reported a converter operating at 50 MHz with a preamplifier to amplify the control signal (after amplifying, the swing is 6.27 V) [14] and for a higher frequency range Ming-Jie et al. demonstrated a converter that can operate at 300 MHz with an additional buffer for a control clock signal [15] but with low power density, i.e., 4.16 × 10 −6 W/mm 2 . To realize the monolithic integrated GaN based DC-DC converter and improve operating frequency, Zhang et al. [10] used three circuit topologies at 100 MHz with a level shifter matching network to transmit the control signal (the swing is 5 V) generated by FPGA (Field Programmable Gate Array). Pilsoon et al. [16] reported a converter that can work at high switching frequency, i.e., 680 MHz with no need for a gate driver, but only with 0.24 W/mm 2 power density using the 0.25 µm GaN-on-SiC process. As enumerated, though the converters that can operate at hundreds of megahertz range have been realized no matter in integrated or discrete form, the gate control signal in some of them still need to be modified by additional buffer or a preamplifier and the power density is still very low at such a frequency range. This paper concentrates on the highly integrated GaN based DC-DC converter which can be controlled directly by the current mode logic (CML) level signal of which the swing is 0.7 V (from 1.1 to 1.8 V), operating at high switching frequency and possessing high power density. Two converter topologies with and without a bootstrapped capacitor structure are designed and analyzed. The driver integrated in the converter can amplify the CML level control signal (swing is 0.7 V) to a driving signal (swing is close to 25 V). The demonstrated GaN based DC-DC converter with a bootstrapped capacitor structure possesses higher performance comparing to the converter without bootstrapped capacitor in terms of efficiency and both of them exhibit 15 V of output voltage, 2.2 W of output power and 1 W/mm 2 of power density working at 200 MHz switching frequency. It is the first time that a GaN based DC-DC converter exhibits 1 W/mm 2 at hundreds of megahertz with the CML level control signal to the authors' knowledge.
This paper is organized as follows: Section 2 shows the working principal and simulated results of the driver and the integrated converters. Section 3 presents the experimental results of both converters. Conclusion and discussion are given in Section 4.

GaN Based Switching DC-DC Converter
As shown in Figure 1, the monolithic integrated GaN based switching DC-DC converter is composed of three parts: half-bridge switching power stage (transistors T HS and T LS ), gate drivers (the triangle parts) and inductive filter network (L R and C R ). The driver for T HS is a high side driver and the other one is a low side driver. In such a structure implemented with D-mode (normally on) GaN HEMT (High Electron Mobility Transistor), the design of the high side driver is quite a challenging issue. It is because the high side transistor T HS need a high driving voltage swing from−5 V (to turn it off) to the required output voltage (to turn it on) whereas a comparatively small voltage swing from −5 to 0 V is needed for the low side transistor T LS . This section demonstrated two approaches to achieve the difficult target with small swing control signal at a very high frequency and high power density. Electronics 2020, 9, x FOR PEER REVIEW

Driver Design
The schematic of the driver is illustrated in Figure 2 consisting of the first amplitude amplifier stage, the second level shifting stage and the third resistive-load amplifier stage. It can provide a suitable driving signal for THS (close to 25 V swing) and TLS to turn them on and off by amplifying and modulating the very small CML level control signal (0.7 V swing), which can solve the challenging issue of the switching DC-DC converter. The 1st and 2nd stage of both side driver have

Driver Design
The schematic of the driver is illustrated in Figure 2 consisting of the first amplitude amplifier stage, the second level shifting stage and the third resistive-load amplifier stage. It can provide a suitable driving signal for T HS (close to 25 V swing) and T LS to turn them on and off by amplifying and modulating the very small CML level control signal (0.7 V swing), which can solve the challenging issue of the switching DC-DC converter. The 1st and 2nd stage of both side driver have the completely identical topology, devices (no matter passive or active components) and bias voltage (VDD× or VSS×) as shown in Figure 2.

Driver Design
The schematic of the driver is illustrated in Figure 2 consisting of the first amplitude amplifier stage, the second level shifting stage and the third resistive-load amplifier stage. It can provide a suitable driving signal for THS (close to 25 V swing) and TLS to turn them on and off by amplifying and modulating the very small CML level control signal (0.7 V swing), which can solve the challenging issue of the switching DC-DC converter. The 1st and 2nd stage of both side driver have the completely identical topology, devices (no matter passive or active components) and bias voltage (VDD× or VSS×) as shown in Figure 2.  Figure 2. Schematic of the driver including a high side driver (VOUT3 to drive THS) and low side driver (VOUT4 to drive TLS).

1.8V
For the 1st stage, its function is to amplify the driver's CML level control signal (of which the amplitude is from 1.1 to 1.8 V) to a bigger swing (5 V). Additionally, for the 2nd stage, it will shift the pulse from the output of the 1st stage to a suitable level, which can offer enough driving ability to drive the third stage to be the ON state and OFF state. Additionally the third part of the driver is a resistive-load amplifier stage to amplify the signal from the output of the 2nd stage to drive the power stage. Compared to discrete converters which use bias tree to enlarge a driving signal in [14] and a hybrid gate driver in CMOS (Complementary Metal Oxide Semiconductor) [15], and integrated converters [10] with an external level shifter matching network, the proposed driver in this paper can be controlled directly by the CML level signal. The driver has less demand for a drivers' control signal and the 1st and 2nd stage can offer over a 4 V swing for the input of the 3rd stage. Subsequently T4 and T5 in the 3rd stage will turn on and off more thoroughly, which means the driver owns much more powerful driving capability. In such situation, the power stage will possess better time domain performance and higher power density. To the authors' knowledge, it is the first time to report the proposed three stages driver structure in the DC-DC converter. For the 1st stage, its function is to amplify the driver's CML level control signal (of which the amplitude is from 1.1 to 1.8 V) to a bigger swing (5 V). Additionally, for the 2nd stage, it will shift the pulse from the output of the 1st stage to a suitable level, which can offer enough driving ability to drive the third stage to be the ON state and OFF state. Additionally the third part of the driver is a resistive-load amplifier stage to amplify the signal from the output of the 2nd stage to drive the power stage. Compared to discrete converters which use bias tree to enlarge a driving signal in [14] and a hybrid gate driver in CMOS (Complementary Metal Oxide Semiconductor) [15], and integrated converters [10] with an external level shifter matching network, the proposed driver in this paper can be controlled directly by the CML level signal. The driver has less demand for a drivers' control signal and the 1st and 2nd stage can offer over a 4 V swing for the input of the 3rd stage. Subsequently T 4 and T 5 in the 3rd stage will turn on and off more thoroughly, which means the driver owns much more powerful driving capability. In such situation, the power stage will possess better time domain performance and higher power density. To the authors' knowledge, it is the first time to report the proposed three stages driver structure in the DC-DC converter.
A simplified diagram for the operation of the high side driver is shown in Figure 3 and the low side driver has the same structure and operation mode except for the inverted input signal so it has been hided due to the area limit. When V H is high(1.8 V), T 1 is ON of which the ON-state resistor is R T1, on and V OUT1 (output of the 1st stage for the high side driver) is close to V SS1 as shown in Figure 3a and V OUT1 (output of the 1st stage for the low side driver) is close to VDD1. For the second level shifting stage, transistor T 3 is equivalent to a current source(I T3 ) for the connection of its gate and Electronics 2020, 9, 1540 4 of 13 source which means the V GS of T 3 is zero so that T 3 will maintain the ON state and the bias current can be figured out by where W, L, µ n and C ox are the technology parameters. For the Schottky diodes D 1 -D 6 , each of them have the same voltage decrement, set to V D which is 2 V at 20 mA bias current, the total voltage decrement of the six diodes is 6 × VD. The magnitude of the voltage decrement can be controlled by adjusting the diameter of the diodes to get the proper V OUT2 (output of the 2nd stage) by RT1, on and VOUT1(output of the 1st stage for the high side driver) is close to VSS1 as shown in Figure 3a and 1 OUT V (output of the 1st stage for the low side driver) is close to VDD1. For the second level shifting stage, transistor T3 is equivalent to a current source(IT3) for the connection of its gate and source which means the VGS of T3 is zero so that T3 will maintain the ON state and the bias current can be figured out by ( ) where W, L , μn and Cox are the technology parameters. For the Schottky diodes D1-D6, each of them have the same voltage decrement, set to VD which is 2 V at 20 mA bias current, the total voltage decrement of the six diodes is 6×VD. The magnitude of the voltage decrement can be controlled by adjusting the diameter of the diodes to get the proper VOUT2 (output of the 2nd stage) by Additionally then, comparatively low VOUT of the 2nd stage will be transmitted to the left side of the third stage and control T4 to turn off, which make the VOUT3 (output of left side for the 3rd stage) output a high level voltage nearly approaching VDD2 (bias voltage of the left side for the 3rd stage). Simultaneously the low side driver accepts a low level signal (1.1 V) and outputs a low level voltage which is VOUT4 (output of right side for the 3rd stage) closing to VSS3 (common bias voltage of the 3rd stage). Vice versa, when VH is low (1.1 V) and VL is high (1.8 V) as shown in Figure 3b, VOUT3 will be close to VSS3 and VOUT4 will be close to GND.
The rise and fall time of the output waveform are optimized through adjusting the resistors of each stage. So for the 1st stage, the load resistor R1 will determine the rise time of VOUT1 (output of the 1st stage) thereby affecting the counterpart of VOUT for the converter. Figure 4a shows the simulated waveform of VOUT1 under conditions of different R1. Making a compromise between the frequency performance and power dissipation, we chose R1 equaling to 500 Ω. As for load resistors in the third differential stage, with the same standpoint like the 1st stage, we chose 500 Ω for R3 in the left side and 250 Ω for R4 in the other side. The simulated output waveforms of both side with different resistors are shown in Figure 4b,c. After confirming the value of all the resistors, the simulated optimized results for driver are shown in Figure 5 proving that the demonstrated gate driver can satisfy the demand for a high swing of the high side power transistor THS at 200 MHz, not to mention TLS. Additionally then, comparatively low V OUT of the 2nd stage will be transmitted to the left side of the third stage and control T 4 to turn off, which make the V OUT3 (output of left side for the 3rd stage) output a high level voltage nearly approaching V DD2 (bias voltage of the left side for the 3rd stage). Simultaneously the low side driver accepts a low level signal (1.1 V) and outputs a low level voltage which is V OUT4 (output of right side for the 3rd stage) closing to V SS3 (common bias voltage of the 3rd stage). Vice versa, when V H is low (1.1 V) and V L is high (1.8 V) as shown in Figure 3b, V OUT3 will be close to V SS3 and V OUT4 will be close to GND.
The rise and fall time of the output waveform are optimized through adjusting the resistors of each stage. So for the 1st stage, the load resistor R 1 will determine the rise time of V OUT1 (output of the 1st stage) thereby affecting the counterpart of V OUT for the converter. Figure 4a shows the simulated waveform of V OUT1 under conditions of different R 1 . Making a compromise between the frequency performance and power dissipation, we chose R 1 equaling to 500 Ω. As for load resistors in the third differential stage, with the same standpoint like the 1st stage, we chose 500 Ω for R 3 in the left side and 250 Ω for R 4 in the other side. The simulated output waveforms of both side with different resistors are shown in Figure 4b,c. After confirming the value of all the resistors, the simulated optimized results for driver are shown in Figure 5 proving that the demonstrated gate driver can satisfy the demand for a high swing of the high side power transistor T HS at 200 MHz, not to mention T LS .    nverter Design fter verifying the function and driving capability of the driver, the power stage was integr he driver in one chip to decrease the parasitic parameters. Figure 6 shows the schematic o lithic integrated GaN based DC-DC converter. Due to the area limit, this schematic just dr gh side driver and simplifies the 1st and 2nd stage of the low side driver with a rectangle. ridge power stage was composed of the high side transistor THS and the low side transistor ate of THS and TLS was connected to VOUT3 (output for the left side of the 3rd stage) and V

Converter Design
After verifying the function and driving capability of the driver, the power stage was integrated with the driver in one chip to decrease the parasitic parameters. Figure 6 shows the schematic of the monolithic integrated GaN based DC-DC converter. Due to the area limit, this schematic just draws the high side driver and simplifies the 1st and 2nd stage of the low side driver with a rectangle. The half-bridge power stage was composed of the high side transistor T HS and the low side transistor T LS . The gate of T HS and T LS was connected to V OUT3 (output for the left side of the 3rd stage) and Electronics 2020, 9, 1540 7 of 13 V OUT4 (output for the right side of the 3rd stage) respectively. When T HS once receives a high level of gate voltage, which comes fromV OUT3 closing to Vin (18 V), it will be the ON state, meanwhile the T LS receives a low gate voltage and turns off, eventually the output level will be high, at 15 V in this paper. To maintain the floating gate voltage of T HS when it is ON, V DD2 (18.5 V) was set to be slightly bigger than Vin (18 V). Vice versa, when V OUT3 is low and V OUT4 is high, the output voltage of the total circuit will be low to 0 V because the source of T LS is GND. Figure 7 shows the simulated waveform of V SW (black solid line). The result proved that the designed converter could transfer 18 V to 15 V with the CML level control signal at 200 MHz. However, the simulated V DD2 was near or bigger than Vin and the simulated power dissipation for the left side of the 3rd stage was 0.53 W resulting in the deterioration of the overall efficiency.
After verifying the function and driving capability of the driver, the power stage was integrated with the driver in one chip to decrease the parasitic parameters. Figure 6 shows the schematic of the monolithic integrated GaN based DC-DC converter. Due to the area limit, this schematic just draws the high side driver and simplifies the 1st and 2nd stage of the low side driver with a rectangle. The half-bridge power stage was composed of the high side transistor THS and the low side transistor TLS. The gate of THS and TLS was connected to VOUT3 (output for the left side of the 3rd stage) and VOUT4 (output for the right side of the 3rd stage) respectively. When THS once receives a high level of gate voltage, which comes fromVOUT3 closing to Vin (18 V), it will be the ON state, meanwhile the TLS receives a low gate voltage and turns off, eventually the output level will be high, at 15 V in this paper. To maintain the floating gate voltage of THS when it is ON, VDD2 (18.5 V) was set to be slightly bigger than Vin (18 V). Vice versa, when VOUT3 is low and VOUT4 is high, the output voltage of the total circuit will be low to 0 V because the source of TLS is GND. Figure 7 shows the simulated waveform of VSW (black solid line). The result proved that the designed converter could transfer 18 V to 15 V with the CML level control signal at 200 MHz. However, the simulated VDD2 was near or bigger than Vin and the simulated power dissipation for the left side of the 3rd stage was 0.53 W resulting in the deterioration of the overall efficiency.   So to reduce this part DC power dissipation, this paper proposed another topology with a bootstrapped capacitor as shown in Figure 6 (include the red bold line path). The red components (protect Schottky diode Dp and bootstrapped capacitor CB) and bold line form the so called bootstrapped path. The only difference in topology of the two types of converters is whether they So to reduce this part DC power dissipation, this paper proposed another topology with a bootstrapped capacitor as shown in Figure 6 (include the red bold line path). The red components (protect Schottky diode D p and bootstrapped capacitor C B ) and bold line form the so called bootstrapped path. The only difference in topology of the two types of converters is whether they have bootstrapped capacitor C B and the protecting diode Dp (the red bold line path) or not. When T LS is turned on, C B will be charged to V DD2 (which is 3 V in the simulated result of the bootstrap topology) and the output voltage level will be nearly zero. Then after T LS was turned off, V OUT of the converter increased so V B (the upper plate potential of C B ) increased too, to maintain the charge between the two plates of C B . Additionally different results of the output for the third stage (V OUT3 ) were given with different C B values, this paper eventually chose 100 pf for a better time domain and bootstrapped performance as depicted in Figure 8. The V DD2 of the converter with a bootstrapped capacitor (C B ) was much smaller (3 V) than the counterpart in the converter without a bootstrapped capacitor (18.5 V) in the simulated result. The simulated power dissipation for the left side of the 3rd stage was 0.12 W, which was much smaller than the counterpart in the converter without C B (0.53 W). With small V DD2 , the output of the left side for 3rd stage could still satisfy the demanding swing for T HS . The simulated output waveform of the switching node (V SW ) for the converter with bootstrapped capacitor is shown in Figure 7 at 200 MHz. Meanwhile in Figure 7 the output high level of the converter with C B was slightly bigger than the converter without C B . That is because the driver of the converter with C B had a much more powerful driving capability. Both of them had over 2.2 W output power at 200 MHz in the simulated results and can be driven simply by the CML level control signal. So to reduce this part DC power dissipation, this paper proposed another topology with a bootstrapped capacitor as shown in Figure 6 (include the red bold line path). The red components (protect Schottky diode Dp and bootstrapped capacitor CB) and bold line form the so called bootstrapped path. The only difference in topology of the two types of converters is whether they have bootstrapped capacitor CB and the protecting diode Dp (the red bold line path) or not. When TLS is turned on, CB will be charged to VDD2 (which is 3 V in the simulated result of the bootstrap topology) and the output voltage level will be nearly zero. Then after TLS was turned off, VOUT of the converter increased so VB (the upper plate potential of CB) increased too, to maintain the charge between the two plates of CB. Additionally different results of the output for the third stage (VOUT3) were given with different CB values, this paper eventually chose 100 pf for a better time domain and bootstrapped performance as depicted in Figure 8. The VDD2 of the converter with a bootstrapped capacitor (CB) was much smaller (3 V) than the counterpart in the converter without a bootstrapped capacitor (18.5 V) in the simulated result. The simulated power dissipation for the left side of the 3rd stage was 0.12 W, which was much smaller than the counterpart in the converter without CB (0.53 W). With small VDD2, the output of the left side for 3rd stage could still satisfy the demanding swing for THS. The simulated output waveform of the switching node (VSW) for the converter with bootstrapped capacitor is shown in Figure 7 at 200 MHz. Meanwhile in Figure 7 the output high level of the converter with CB was slightly bigger than the converter without CB. That is because the driver of the converter with CB had a much more powerful driving capability. Both of them had over 2.2 W output power at 200 MHz in the simulated results and can be driven simply by the CML level control signal.

Experiment Results
The designed GaN based DC-DC converter is realized in the process of 0.25 µm GaN-on-SiC and the detailed description of the process can refer to [17]. The epitaxial structure of the AlGaN/GaN HEMT consists of a 3in SiC substrate, a 2 µm GaN buffer, a 1nm AlN interlayer, a 23 nm Al 0.23 Ga 0.77 N barrier and a 2-nm GaN cap. The gate width of T 1 , T 4 , T 5 and T 2 , T 3 was 2 × 125 µm and 20 µm respectively. The radius of the Schottky diodes used for level shifting was 20 µm. For the power stage, the gate width of T HS and T LS was both 8 × 125 µm to meet the demanding for a low output capacitor and low R ON . The test of the converters was carried out by mounting the chips on PCB, which were connected through bonding wires. The CML level control signal (1.1-1.8 V) was generated by an Agilent 81250 Parallel Bit Error Ratio Tester(PBER) with a sampling rate of 10.6 Gbps. The DC power supply was supported by HP4142B and HP6654A and the output waveform was measured by a 50 Ω-high-speed Lecroy SDA 816Zi-A oscilloscope with a 40GS/s sampling rate in the time domain.
First, the separated gate driver was tested, and its output waveform of the left side for the 3rd stage is shown in Figure 9. The gate driver could offer a pulse that the voltage swing could be up to 24.1 V (from −6.4 to 17.7 V) under 1.25 MHz with 150 ns for rising time and 30.7 ns for average falling time. The rising time was determined by R 3 × C OUT3 and the falling time was determined by R ON × C OUT3 , where R 3 is the left side load resistor of the 3rd stage, R ON is the ON-state resistor of left transistor of the 3rd stage and C OUT3 is the equivalent output capacitor of the output node for the left side of the 3rd stage. Due to the large time constant, the separated driver can not be tested at higher frequency. However, the monolithic integrated converter could operate at 200 MHz resulting from the equivalent output resistance(R E ) in the V OUT3 node decreasing. Since when the driver is tested separately, its load resistor was 1 MΩ to simulate the gate of T HS leading to a large time constant (R 3 × C OUT 3, R E was equal to R 3 ). While for the integrated circuit, its load resistor was 50 Ω, which means the time constant was equal to R E × C OUT3 , which was much smaller than R 3 × C OUT3 (R E was the parallel of R 3 and oscilloscope resistor (50 Ω) here).
the gate width of THS and TLS was both 8 × 125 μm to meet the demanding for a low output capacitor and low RON. The test of the converters was carried out by mounting the chips on PCB, which were connected through bonding wires. The CML level control signal (1.1 -1.8 V) was generated by an Agilent 81250 Parallel Bit Error Ratio Tester(PBER) with a sampling rate of 10.6 Gbps. The DC power supply was supported by HP4142B and HP6654A and the output waveform was measured by a 50 Ω-high-speed Lecroy SDA 816Zi-A oscilloscope with a 40GS/s sampling rate in the time domain.
First, the separated gate driver was tested, and its output waveform of the left side for the 3rd stage is shown in Figure 9. The gate driver could offer a pulse that the voltage swing could be up to 24.1 V (from −6.4 to 17.7 V) under 1.25 MHz with 150 ns for rising time and 30.7 ns for average falling time. The rising time was determined by R3×COUT3 and the falling time was determined by RON×COUT3, where R3 is the left side load resistor of the 3rd stage, RON is the ON-state resistor of left transistor of the 3rd stage and COUT3 is the equivalent output capacitor of the output node for the left side of the 3rd stage. Due to the large time constant, the separated driver can not be tested at higher frequency. However, the monolithic integrated converter could operate at 200 MHz resulting from the equivalent output resistance(RE) in the VOUT3 node decreasing. Since when the driver is tested separately, its load resistor was 1 MΩ to simulate the gate of THS leading to a large time constant(R3×COUT3, RE was equal to R3). While for the integrated circuit, its load resistor was 50 Ω, which means the time constant was equal to RE×COUT3, which was much smaller than R3×COUT3 (RE was the parallel of R3 and oscilloscope resistor (50 Ω) here).  Figure 10 shows the prototypes for both converters. Additionally the comparison between the experimental output waveforms of two converters and the simulated output waveform of the converter with CB is given in Figure 11 at 200 MHz. Both of the two converters exhibited the highest experimental output level of 15 V. Comparing with the counterparts in [10] at 100 MHz, the waveform result of this paper was much smoother with less ripple at a higher frequency of 200 MHz. There is a phenomenon that should be explained that the edge of simulated and experimental waveforms is not coincident very well. Such a deviation is because the duty of the control signal generated by PBER was not literally 50% result from the coding mode of PBER. However, their qualitative behaviors are the same as shown in the black short-dash rectangle of Figure 11.  Figure 10 shows the prototypes for both converters. Additionally the comparison between the experimental output waveforms of two converters and the simulated output waveform of the converter with C B is given in Figure 11 at 200 MHz. Both of the two converters exhibited the highest experimental output level of 15 V. Comparing with the counterparts in [10] at 100 MHz, the waveform result of this paper was much smoother with less ripple at a higher frequency of 200 MHz. There is a phenomenon that should be explained that the edge of simulated and experimental waveforms is not coincident very well. Such a deviation is because the duty of the control signal generated by PBER was not literally 50% result from the coding mode of PBER. However, their qualitative behaviors are the same as shown in the black short-dash rectangle of Figure 11.
In Figure 12, the performance of efficiency and output power for two types of switching converters is depicted. The highest output power for the converter with a bootstrapped capacitor was 2.22 W, consequently its power density was 1 W/mm 2 and efficiency was 54.8% when Vin was 18 V. Apparently both converters had similar output power whereas the converter with C B had higher PAE (overall efficiency or power added efficiency) and DE (drain efficiency, i.e., power stage efficiency). It is because the use of the bootstrapped capacitors could dramatically decrease the demand for high V DD2 (from 18.5 V in a converter without C B to 3 V in a converter with C B ) to reduce the power consumption of the driver and increase PAE over 5%.Therefore, the converter with C B , which this paper proposed, had the merits in requiring lower driver power dissipation and possessing higher DE and PAE, as expected, than the counterparts of the converter without C B under the approximate output power and power density condition.  Simulated result for convertor wi C B Figure 11. Comparison between the experimental output waveforms (of a converter with a bootstrapped capacitor and converter without a bootstrapped capacitor) and simulated output waveform (of a converter with a bootstrapped capacitor).
In Figure 12, the performance of efficiency and output power for two types of switching converters is depicted. The highest output power for the converter with a bootstrapped capacitor was 2.22 W, consequently its power density was 1 W/mm 2 and efficiency was 54.8% when Vin was 18 V. Apparently both converters had similar output power whereas the converter with CB had higher PAE (overall efficiency or power added efficiency) and DE (drain efficiency, i.e., power stage efficiency). It is because the use of the bootstrapped capacitors could dramatically decrease the demand for high VDD2 (from 18.5 V in a converter without CB to 3 V in a converter with CB) to reduce the power consumption of the driver and increase PAE over 5%.Therefore, the converter with CB, which this paper proposed, had the merits in requiring lower driver power dissipation and possessing higher DE and PAE, as expected, than the counterparts of the converter without CB under the approximate output power and power density condition.   igure 12, the performance of efficiency and output power for two types of sw rs is depicted. The highest output power for the converter with a bootstrapped capaci onsequently its power density was 1 W/mm 2 and efficiency was 54.8% when Vin wa   Figure 12. Measured efficiency and output power with differential. Figure 13 demonstrates the power density performance comparison between the designed converter with a bootstrapped capacitor and the state-of-the-art buck converter. It was proven the proposed topology with a new driver and bootstrapped capacitor possessed the highest power density at a hundreds of megahertz range to the authors' knowledge. Table 1 shows the summary of the proposed circuit performance and a comparison with the previous DC-DC converters' results, illustrating that the designed converter of this work could be directly driven by a small control signal (CML: swing was 0.7 V) at a hundreds of megahertz range with the highest power density.   Figure 13 demonstrates the power density performance comparison between the designed converter with a bootstrapped capacitor and the state-of-the-art buck converter. It was proven the proposed topology with a new driver and bootstrapped capacitor possessed the highest power density at a hundreds of megahertz range to the authors' knowledge. Table 1 shows the summary of the proposed circuit performance and a comparison with the previous DC-DC converters' results, illustrating that the designed converter of this work could be directly driven by a small control signal (CML: swing was 0.7 V) at a hundreds of megahertz range with the highest power density.
Electronics 2020, 9, Figure 12. Measured efficiency and output power with differential. Figure 13 demonstrates the power density performance comparison between the designed converter with a bootstrapped capacitor and the state-of-the-art buck converter. It was proven the proposed topology with a new driver and bootstrapped capacitor possessed the highest power density at a hundreds of megahertz range to the authors' knowledge. Table 1 shows the summary of the proposed circuit performance and a comparison with the previous DC-DC converters' results, illustrating that the designed converter of this work could be directly driven by a small control signal (CML: swing was 0.7 V) at a hundreds of megahertz range with the highest power density. Comparison to SOA Figure 13. Comparison of this work to the state-of-the-art [9,10,15,16], [18][19][20][21][22] pulse signals at 200 MHz.  Figure 13. Comparison of this work to the state-of-the-art [9,10,15,16], [18][19][20][21][22] pulse signals at 200 MHz.

Conclusions
This paper demonstrated a monolithic integrated GaN based DC-DC buck converter, which can be directly controlled by the CML level signal of which the amplitude was from 1.1 to 1.8 V, with bootstrapped topology transferring 18 V to 15 V. The size of the chip was 1.7 mm × 1.3 mm of which the power density was 1 W/mm 2 and output power was 2.2 W with 54.8% power stage efficiency operating at 200 MHz. To the authors' knowledge, this was the highest power density for a GaN based DC-DC converter at a hundreds of megahertz range by using the CML level control signal.