MFMIS Negative Capacitance FinFET Design for Improving Drive Current

: The e ﬀ ect of remnant polarization ( P r ), coercive electric-ﬁeld ( E c ), and parasitic capacitance of baseline device on the drive current (I ON ) of a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) negative capacitance FinFET (NC FinFET) was investigated. The internal gate voltage in the MFMIS structure was simulated considering gate leakage current. Using technology computer aided design (TCAD) tool, the device characteristic of 7 nm FinFET was quantitatively estimated, for the purpose of modeling the baseline device of MFMIS NC FinFET. The need for appropriate parasitic capacitance to avoid performance degradation in MFMIS NC FinFET was presented through the internal gate voltage estimation. With an appropriate parasitic capacitance, the e ﬀ ect of P r and E c was investigated. In the case of E c engineering, it is inappropriate to improve the device performance for MFMIS NC FinFET without threshold voltage degradation. Rather than E c engineering, an adequate P r value for achieving high I ON in MFMIS NC FinFET is suggested.


Introduction
The negative capacitance field effect transistor (NCFET) was introduced as one of the steep switching devices [1]. The NCFET enables effectively lowering of the power supply voltage of conventional metal oxide semiconductor field effect transistor (MOSFET) because of its super steep switching feature, i.e., sub-60-mV/decade subthreshold swing at room temperature. Unlike the other steep switching devices (e.g., Tunnel FET [2] and nano-electro-mechanical (NEM) relay [3,4]), the NCFET requires an additional ferroelectric layer in its gate stack. Recent studies demonstrated some conspicuous characteristics of NCFET, e.g., improved subthreshold slope, hysteresis-free behavior, and improved DIBL (drain-induced barrier lowering) effect [5][6][7][8][9][10]. There are several factors which play an important role in determining the performance of NCFET. Those factors include electrical properties, such as coercive electric field (E c ), remnant polarization (P r ), and parasitic capacitance of baseline device without ferroelectric layer. E c and P r represent the electrical properties of the ferroelectric layer in NCFET. It is known that a hafnium-based ferroelectric material can have various values of E c and P r in a certain range, depending on fabrication conditions or dopants [11,12]. Therefore, the impact of E c , P r , and parasitic capacitance on NCFET performance was widely investigated [13,14]. Those studies have shown that the NCFET can improve its subthreshold slope and threshold voltage, by taking appropriate values of E c , P r , and parasitic capacitance. Additionally, the gate stack structure in NCFET affects the device performance of NCFET. As a gate stack structure for NCFET, a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure was suggested. It was expected that the intermediate metal layer in the MFMIS structure can act as an equipotential layer that alleviates multi-domain effects, so that it generates a higher voltage gain than in a metal-ferroelectric-insulator-semiconductor (MFIS) structure [15,16]. However, Khan et al. [17] Electronics 2020, 9, 1423 2 of 7 showed that, if there exists a leakage current in the MFMIS structure, it is impossible for the polarization of ferroelectric material to stably exist in the negative capacitance (NC) region (i.e., where dP/dV < 0). This is because the polarization of ferroelectric material slips toward either positive or negative P r , so that a stabilized voltage gain cannot be expected. There is little study of the impact of those parameters on the device performance of MFMIS NCFET (which is affected by the leakage of intermediate metal). To benefit the performance improvement in MFMIS NCFET, the impact of E c , P r , and parasitic capacitance should be investigated. In this work, the impact of E c , P r , and parasitic capacitance on MFMIS NC FinFET was investigated through the framework of Khan and 7 nm technology node fin-shaped field effect transistor (FinFET). In addition, we suggest how to design the MFMIS NC FinFET to obtain better device performance.

Simulation Method for MFMIS NC FinFET
The MFMIS structure for NCFET was used in this work (see Figure 1a). Due to the leakage current through the internal gate, the ferroelectric layer cannot stay in the negative capacitance region (i.e., negative slope region in polarization-vs.-electric field plot of ferroelectric material), and thereby, the MFMIS NCFET cannot be expected to benefit the stable voltage amplification of the ferroelectric layer. In order to take advantage of using the voltage amplification of the ferroelectric layer in MFMIS NCFET, the dynamic response should be considered. From the perspective of time-dependency, we have used the framework of [17] to estimate the voltage amplification in MFMIS NCFET. In reference [17], the metal-ferroelectric-metal-insulator-metal (MFMIM) structure was modeled as the series-connected circuit network (see Figure 1b). The ferroelectric and dielectric thin film can be modeled as the parallel connection of the capacitor and resistor, and the intermetal layer was modeled as the internal node because the intermetal layer acts as the equipotential surface between the ferroelectric and dielectric film. The polarization-vs.-electric-field behavior of ferroelectric material is analytically described with the Landau-Khalatnikov (LK) Equation (1) as below.
where T F indicates the thickness of ferroelectric layer, and the coefficients (i.e., α and β) are defined as below.
Electronics 2020, 9, x FOR PEER REVIEW 2 of 7 that, if there exists a leakage current in the MFMIS structure, it is impossible for the polarization of ferroelectric material to stably exist in the negative capacitance (NC) region (i.e., where dP/dV < 0). This is because the polarization of ferroelectric material slips toward either positive or negative Pr, so that a stabilized voltage gain cannot be expected. There is little study of the impact of those parameters on the device performance of MFMIS NCFET (which is affected by the leakage of intermediate metal). To benefit the performance improvement in MFMIS NCFET, the impact of Ec, Pr, and parasitic capacitance should be investigated. In this work, the impact of Ec, Pr, and parasitic capacitance on MFMIS NC FinFET was investigated through the framework of Khan and 7 nm technology node fin-shaped field effect transistor (FinFET). In addition, we suggest how to design the MFMIS NC FinFET to obtain better device performance.

Simulation Method for MFMIS NC FinFET
The MFMIS structure for NCFET was used in this work (see Figure 1a). Due to the leakage current through the internal gate, the ferroelectric layer cannot stay in the negative capacitance region (i.e., negative slope region in polarization-vs.-electric field plot of ferroelectric material), and thereby, the MFMIS NCFET cannot be expected to benefit the stable voltage amplification of the ferroelectric layer. In order to take advantage of using the voltage amplification of the ferroelectric layer in MFMIS NCFET, the dynamic response should be considered. From the perspective of time-dependency, we have used the framework of [17] to estimate the voltage amplification in MFMIS NCFET. In reference [17], the metal-ferroelectric-metal-insulator-metal (MFMIM) structure was modeled as the seriesconnected circuit network (see Figure 1b). The ferroelectric and dielectric thin film can be modeled as the parallel connection of the capacitor and resistor, and the intermetal layer was modeled as the internal node because the intermetal layer acts as the equipotential surface between the ferroelectric and dielectric film. The polarization-vs.-electric-field behavior of ferroelectric material is analytically described with the Landau-Khalatnikov (LK) Equation (1) as below.
where TF indicates the thickness of ferroelectric layer, and the coefficients (i.e., α and β) are defined as below.  Applying the Kirchhoff's current law at the internal metal of the series network, we can derive the equation below.
where R F , R D are computed as V app /(J L × A), where J L is the leakage current that is approximately 10 −2 A/cm 2 for an applied bias of 1 V [18]. The equation shows the amount of charge in the ferroelectric layer over time. Thus, applying a triangular pulse, the amount of charge in the ferroelectric layer can be estimated, and thereby, it turned out that the MFMIM structure can show the voltage amplification across the ferroelectric layer. Note that the equation is derived from the MFMIM structure, but it is applicable to MFMIS NCFET [19].
Although the MFMIS NCFET can use the negative slope region of ferroelectric layer, the performance degradation of the MFMIS NCFET was expected. The work function engineering was suggested to prevent the performance degradation as well as to enhance the on-state drive current of NCFET [19]. Using metal materials with two different work function values to wrap around the ferroelectric layer, the S-curves in polarization versus voltage plot can be shifted along the voltage axis. The voltage shift can put the ferroelectric into the negative capacitance state (i.e., a smaller amount of V G can put the ferroelectric into the negative capacitance state). In this simulation work, 0.2 V of V offset is applied through the work function engineering between two metal layers (see Figure 2a). It is noteworthy that the I D -vs.-V G and C G -vs.-V G of baseline FinFET without MFM layer are estimated using Sentaurus TCAD tool (see Figure 3). The FinFET is modeled in accordance with 7 nm technology of IRDS 2017 roadmap [20]. The physical device dimensions of the FinFET are shown in Table 1 Applying the Kirchhoff's current law at the internal metal of the series network, we can derive the equation below. , (3) where RF, RD are computed as Vapp/(JL × A), where JL is the leakage current that is approximately 10 −2 A/cm 2 for an applied bias of 1 V [18]. The equation shows the amount of charge in the ferroelectric layer over time. Thus, applying a triangular pulse, the amount of charge in the ferroelectric layer can be estimated, and thereby, it turned out that the MFMIM structure can show the voltage amplification across the ferroelectric layer. Note that the equation is derived from the MFMIM structure, but it is applicable to MFMIS NCFET [19].
Although the MFMIS NCFET can use the negative slope region of ferroelectric layer, the performance degradation of the MFMIS NCFET was expected. The work function engineering was suggested to prevent the performance degradation as well as to enhance the on-state drive current of NCFET [19]. Using metal materials with two different work function values to wrap around the ferroelectric layer, the S-curves in polarization versus voltage plot can be shifted along the voltage axis. The voltage shift can put the ferroelectric into the negative capacitance state (i.e., a smaller amount of VG can put the ferroelectric into the negative capacitance state). In this simulation work, 0.2 V of Voffset is applied through the work function engineering between two metal layers (see Figure  2a). It is noteworthy that the ID-vs.-VG and CG-vs.-VG of baseline FinFET without MFM layer are estimated using Sentaurus TCAD tool (see Figure 3). The FinFET is modeled in accordance with 7 nm technology of IRDS 2017 roadmap [20]. The physical device dimensions of the FinFET are shown in Table 1

Effect of Ec, Pr, and Parasitic Capacitance on MFMIS NC FinFET
Using (1) [12][13][14]. The S-curve of ferroelectric material (in which the work function is engineered) is shown in Figure 2a. We used the 100 MHz frequency because if the frequency of sweeping VG is faster than the "effective time constant" [17], the impact of the leakage current should be neglected.
The impact of varied Ec and Pr of ferroelectric material is shown in Figure 2c,d. As shown in the figures, the internal voltage decreased and was lower than the reference voltage over the whole time. The internal voltage decreases more with increasing Ec. In the case of decreasing Pr, the internal voltage increases but is still lower than the reference voltage over the whole time. The reason for the internal voltage lowering comes from the fact that CG in the baseline FinFET increases at about 0.3 V (see Figure 3b) due to the inversion layer, and thereby, the internal amplification deteriorates. In this case, an appropriate parasitic capacitance can alleviate the internal voltage lowering, and therefore, it induces a proper voltage amplification in MFMIS structure (see Figure 2b). Total device capacitance (CTOT) can be calculated as (CG + Cpara). In the case of 100 aF of parasitic capacitance, VINT of ≈1.2 V can be implemented by applying a VG of 1 V. By applying 100 aF of parasitic capacitance to obtain a proper voltage amplification, the impact of Ec and Pr was investigated again. First, increasing Ec makes the amount of voltage amplification (at 1 V of reference voltage) become higher (see Figure  4a). However, at a low reference voltage, the lowering of internal voltage becomes severe. This is because a higher Ec needs additional voltage to put ferroelectric material into the negative slope region. In the case of higher Ec, the lowering of internal voltage can be compensated using different metal (which makes Voffset more than 0.2 V) [8].
When Pr is increased, the reference voltage (at which the internal voltage is amplified) is pushed to a higher voltage (see Figure 4b). Low Pr (i.e., 5 μC/cm 2 ) can derive the voltage amplification at a much lower reference voltage. However, the internal voltage at a high reference voltage will be degraded. Additionally, even if Pr becomes lower, it is hard to expect performance enhancement at

Effect of E c , P r , and Parasitic Capacitance on MFMIS NC FinFET
Using (1) 100 MHz 1 V triangular pulses, (2) the parameter of hafnium oxide ferroelectric material, and (3) C G -vs.-V G of baseline device, we can find out the voltage-vs.-time characteristic of MFMIS NC FinFET. Note that E c and P r used for the S-curve in Figure 2a was 0.7 MV/cm and 10 µC/cm 2 , respectively [12][13][14]. The S-curve of ferroelectric material (in which the work function is engineered) is shown in Figure 2a. We used the 100 MHz frequency because if the frequency of sweeping V G is faster than the "effective time constant" [17], the impact of the leakage current should be neglected.
The impact of varied E c and P r of ferroelectric material is shown in Figure 2c,d. As shown in the figures, the internal voltage decreased and was lower than the reference voltage over the whole time. The internal voltage decreases more with increasing E c . In the case of decreasing P r , the internal voltage increases but is still lower than the reference voltage over the whole time. The reason for the internal voltage lowering comes from the fact that C G in the baseline FinFET increases at about 0.3 V (see Figure 3b) due to the inversion layer, and thereby, the internal amplification deteriorates. In this case, an appropriate parasitic capacitance can alleviate the internal voltage lowering, and therefore, it induces a proper voltage amplification in MFMIS structure (see Figure 2b). Total device capacitance (C TOT ) can be calculated as (C G + C para ). In the case of 100 aF of parasitic capacitance, V INT of ≈1.2 V can be implemented by applying a V G of 1 V. By applying 100 aF of parasitic capacitance to obtain a proper voltage amplification, the impact of E c and P r was investigated again. First, increasing E c makes the amount of voltage amplification (at 1 V of reference voltage) become higher (see Figure 4a). However, at a low reference voltage, the lowering of internal voltage becomes severe. This is because a higher E c needs additional voltage to put ferroelectric material into the negative slope region. In the case of higher E c , the lowering of internal voltage can be compensated using different metal (which makes V offset more than 0.2 V) [8].
conditions, ID-vs.-VG of NC FinFETs were estimated (see Figure 4c,d). In the ID-vs.-VG of NC FinFETs, the on-state drive current (ION) and threshold voltage (VT) were extracted (see Figure 5). Note that VT was extracted at the constant current of 100 nA/um. Higher Ec enables the MFMIS NC FinFET to achieve the highest ION, but, at the same time, it increases VT significantly. If Pr is in-between 5 μC/cm 2 and 10 μC/cm 2 , ION and VT have a trade-off relationship to each other. However, the trade-off is not found in the case of 15 μC/cm 2 . Even using a low Pr in MFMIS NC FinFET, a significant improvement in VT is hard to expect.   When P r is increased, the reference voltage (at which the internal voltage is amplified) is pushed to a higher voltage (see Figure 4b). Low P r (i.e., 5 µC/cm 2 ) can derive the voltage amplification at a much lower reference voltage. However, the internal voltage at a high reference voltage will be degraded. Additionally, even if P r becomes lower, it is hard to expect performance enhancement at the deep subthreshold region. In the case of high P r (i.e., 15 µC/cm 2 ), the internal voltage loses the voltage amplification in all regions of the reference voltages. Using the internal voltages of various conditions, I D -vs.-V G of NC FinFETs were estimated (see Figure 4c,d). In the I D -vs.-V G of NC FinFETs, the on-state drive current (I ON ) and threshold voltage (V T ) were extracted (see Figure 5). Note that V T was extracted at the constant current of 100 nA/um. Higher E c enables the MFMIS NC FinFET to achieve the highest I ON , but, at the same time, it increases V T significantly. If Pr is in-between 5 µC/cm 2 and 10 µC/cm 2 , I ON and V T have a trade-off relationship to each other. However, the trade-off is not found in the case of 15 µC/cm 2 . Even using a low P r in MFMIS NC FinFET, a significant improvement in V T is hard to expect.  Figure 4c,d). In the ID-vs.-VG of NC FinFETs, the on-state drive current (ION) and threshold voltage (VT) were extracted (see Figure 5). Note that VT was extracted at the constant current of 100 nA/um. Higher Ec enables the MFMIS NC FinFET to achieve the highest ION, but, at the same time, it increases VT significantly. If Pr is in-between 5 μC/cm 2 and 10 μC/cm 2 , ION and VT have a trade-off relationship to each other. However, the trade-off is not found in the case of 15 μC/cm 2 . Even using a low Pr in MFMIS NC FinFET, a significant improvement in VT is hard to expect.

Conclusions
The impact of E c , P r , and parasitic capacitance on the performance of MFMIS NC FinFET was investigated. To find out the voltage of intermediate metal in the MFMIS structure, Landau-Khalatnikov model with the gate leakage current was used. Investigating the effect of parasitic capacitance on the MFMIS structure, the parasitic capacitance can be the key knob to control the internal voltage. With 100 aF of parasitic capacitance, E c and P r in ferroelectric material were varied between 5-15 µC/cm 2 and 0.7-1.2 MV/cm, respectively. In order to design MFMIS NC FinFET to achieve high drive current, E c of 1.2 MV/cm can induce the highest drive current (i.e., 1.5 times higher drive current than in baseline device). However, the threshold voltage of the NC FinFET was increased (by ≈0.12 V) than that of baseline device. On the other hand, the NC FinFET with an appropriate value of P r (i.e., 10 µC/cm 2 ) can achieve 1.4 times higher drive current than baseline device with little V T degradation.