Ultra-Low-Voltage Inverter-Based Operational Transconductance Ampliﬁers with Voltage Gain Enhancement by Improved Composite Transistors

: This paper proposes topological enhancements to increase voltage gain of ultra-low-voltage (ULV) inverter-based OTAs. The two proposed improvements rely on adoption of composite transistors and forward-body-biasing. The impact of the proposed techniques on performance ﬁgures is demonstrated through simulations of two OTAs. The ﬁrst OTA achieves a 39 dB voltage gain, with a power consumption of 600 pW and an active area of 447 µm 2 . The latter allies the forward-body-bias approach with the beneﬁt of the independently biased composite transistors. By combining both solutions, voltage gain is raised to 51 dB, consuming less power (500 pW) at the cost of an increased area of 727 µm 2 . The validation has been performed through post-layout simulations with the Cadence Analog Design Environment and the TSMC 180 nm design kit, with the supply voltage ranging from 0.3 V to 0.6 V.


Introduction
The increasing demand for electronic devices supplied by energy-harvesting power sources bring about the need for integrated circuits (ICs) able to properly operate at ultra-low-voltage supply and with ultra-low-power consumption [1][2][3][4][5][6].
In this context, the Operational Transconductance Amplifiers (OTAs) are the building blocks of any front-end and signal processing chain that are traditionally unsuitable to operate at very low voltage fulfilling performance like a rail-to-rail input/output voltage swing and high transconductance-gain that are also independent by process, supply voltage, and temperature variations [7]. To face such challenges, several OTAs have been proposed targeting ultra-low-voltage (ULV) supply and Ultra-Low-Power consumption. The input and output voltage swings of such OTAs are severely limited because of their conventional gate-driven differential pair (DP). On the other hand, bulk-driven input DPs OTAs [8][9][10][11] exhibit increased input range linearity at the cost of bandwidth, power efficiency, and finite DC input impedance [12].
In this framework, the composite transistors [19], such as rectangular arrays [20] and trapezoidal arrays [21], can be used to increase the voltage gain of inverter-based OTAs at the cost of area.
Moreover, improved composite transistors with forward-body-bias offer additional features to increase the voltage gain [22]. This paper describes how inverter-based OTAs can benefit from forward-body-biasing to implement common-mode input voltage rejection [21] in single-ended OTAs, balance the charge mobility asymmetry of PMOS and NMOS transistors with parallel and series transistor arrays [19] to save area, and adapt improved composite transistors [22] to enhance voltage-gain.
In Section 2, an elementary composite transistor made of two N-type MOS is considered and how the gain can benefit from an independent bias of their bulk terminals is discussed. Then, in Section 3, two inverter-based OTAs with common-mode rejection forward-body-bias circuits are described. The first is made of with parallel PMOS transistors arrays and NMOS series arrays for the pull-up and the pull-down networks, targeting the lowest area for the described approach. The second is a version of the first OTA which uses adapted improved composite transistors to achieve a greater voltage-gain. In Section 4, the characteristics of such two OTAs are verified and compared through post-layout simulations with the 180 nm technology process. Finally, in Section 5, conclusions are drawn.

Composite Transistor with an Improved Forward-Body-Bias
Implementing inverter-based OTAs with composite transistors allows designers to exploit the gain-area trade-off. Figure 1a represents an elementary composite N-type transistor M N made of two series transistors M N,2 and M N,1 . Considering that M N,1 and M N,2 have the same length, the equivalent transistor aspect ratio S eq is defined by (1) [19]: where Such use of composite transistors improves voltage gain by increasing the k factor [21], which is the ratio of the transistors M N,2 and M N,1 aspect ratios S N,2 and S N,1 . The equivalent transistor channel length L eq and the Early Voltage V A increase proportionally to k; however, the equivalent transistor total area and input capacitance also increase accordingly.
By using the UICM (Unified Current Control Model) all-region transistor model [23] approximation to the weak inversion transistor operation, the transistor drain current I D can be calculated as follows: (3) where V GB , V SB , and V DB are respectively the the gate-to-bulk, source-to-bulk, and drain-to-bulk voltages, V T is the threshold voltage, n is the slope factor, φ t is the thermal voltage, I S is the normalization current, I SH is the sheet normalization current, S is the transistor aspect ratio, µ is the charge mobility, and C ox is the gate oxide capacitance per area. Considering that I D = I DN,1 = I DN,2 and V X = V DN,1 = V SN,2 , that M N,1 operates in the linear region, M N,2 operates in the saturation region, and both transistors operate in weak inversion, the composite transistor drain current I D can be calculated as shown in (5) and (6): By fixing the size of M N,1 , the drain current I D can be changed by varying the width of the transistor M N,2 , and assuming the body-bias of the of the two series transistors M N,1 and M N,2 in Figure 1a tied at the same voltage, so that V G = V D = V B1 = V B2 = 0.25 V, the drain current I D of the composite transistor is proportional to the equivalent transistor aspect ratio, as described in (7) and shown in Figure 1b: A similar current increase can be reached keeping the size of the two series transistors M N,2 and M N,1 equal (k = 1) and biasing the two transistors independently in Figure 1a [22]. Assuming Figure 2a shows how the drain current I D can be increased by means of a difference of the body-bias voltage ∆V B = V B2 − V B1 . Notice that, in this later case, two series transistors M N,2 and M N,1 in Figure 1a have equal size (k = 1) so that the drain current I D can be expressed as: where represents a correction factor for the current drain I D definition due to the difference between the body-bias of the series transistors M N,2 and M N,1 , assuming the transistors are operating in weak inversion, as can be highlighted comparing (7) with (8). Figure 2b shows how β changes with the difference of the body-bias voltage ∆V B = V B2 − V B1 , which agrees with the approximation defined by (9) for a slope factor n ≈ 1.29 and a thermal voltage φ t ≈ 26 mV.  In addition, the equivalent transistor output resistance r o , the inverse of the output conductance g o , defined by is a function of the Early voltage V A and the drain current I D , considering that the transistor M N,2 operates in the saturation region. The Early voltage is defined by a technology parameter V E and the transistor channel length L. Figure 3c shows that V A increases almost proportionally with k and β, which means that, by this definition, the equivalent transistor channel length L eq increases accordingly. Figure 3d shows the equivalent transistor small-signal intrinsic voltage gain, which is defined as A V = g m r o . As shown in Figure 3a-d, the small-signal parameters vary almost exactly as a function of k or β, which proves that an improved composite transistor differential forward-body-bias voltage variation is equivalent to a composite transistor physical parameter variation.
In the next section, the above-mentioned differential forward-body-bias, is applied to two novel inverter-based OTAs with composite transistors. Figure 4 shows the compact and extended circuit view of the conventional inverter-based, pseudo-differential, single-ended OTA with a forward-body-bias, which is basically the half-circuit of the fully-differential Bulk Nauta OTA proposed in [21]. In order to compensate the charge mobility difference between PMOS and NMOS transistors, the inverter PMOS aspect ratio S P must be greater than the NMOS S N . In this particular design, S P must be approximately four times greater than S N . One way to do that is to keep both PMOS and NMOS transistor lengths L constant and choose a PMOS width W P four times wider than W N . In this design, the inverter is made of PMOS parallel transistor arrays and NMOS series transistor arrays, which saves 20% of the total area.

Inverter-Based OTAs with an Improved Forward Body-Bias
In particular, the equivalent transistors shown in Figure 4a, the PMOS M PA , M PB , and the NMOS M NA , M NB are respectively parallel and series rectangular transistor arrays represented as the single unit transistors in Figure 4b. The red and blue dashed lines highlight such an equivalence.
In the following, all unit transistors that make up the composite transistors have the same aspect ratio S u . Assuming that the aspect ratios of M NA,1 and M NA,2 are equal, so that the equivalent aspect ratio of the N-type rectangular transistor array is and its equivalent active area is Similarly, every P-type rectangular transistor array M P is made of two parallel unit transistors of the same aspect ratio S u . Thus, it has an equivalent aspect ratio that is equal to and an equivalent active area equal to The two branches of this OTA (named OTA-A in the following) are made of P-type (M PA , M PB a) and N-type (M NA , M NB ) transistors whose bulk terminals are all connected to the node X (see Figure 4a). This way, both the P-and N-type transistors M P and M N bulk terminals of the two branches of the OTA-A are biased at V X ≈ V DD /2 = 0.15 V for typical process parameters.
As the fully differential Bulk Nauta OTA [21], this topology has a limited common-mode rejection and requires additional area required for the guard rings needed to isolate the substrate, so that the overall area is larger than the area of two conventional inverters only. In addition, since the NMOS transistors are independently forward-body-biased, a triple well CMOS process is required.
Based on this topology, a version of the former OTA using improved composite transistors to further increase the voltage gain is proposed, as shown in Figure 5. Similarly to Figure 4a,b, Figure 5a,b represent the compact and extended circuit view of the proposed improved version of the former circuit in Figure 4, where the pull-up and pull-down network are made of improved composite transistors, and each transistor array is equivalently represented by single unit transistors.
In the proposed OTA-B, a modified version of improved composite transistor from [22] is used to independently bias the body of the composite transistors with a differential bulk terminal voltage ∆V B . Instead of being tied to the input nodes of the inverters, as in [22], the bulk terminals of the transistors M PA-B,2 and M NA-B,2 are tied respectively to the diode-connected transistors M NC and M PC , so that their voltages are respectively almost equal to zero or to the supply voltage, but the parasitic substrate current is limited [21].
Then, the bulks of the transistors M PA-B,1 and M NA-B,1 are tied to the node X, which voltage is On this basis, each improved composite transistor that defines the pull-up and pull-down network of the OTA-B has a forward-body-bias differential voltage ∆V B ≈ V DD /2 = 0.15 V, which is the aim of the design.
Notice that these transistors (M PC and M NC ) are not required when using a FD-SOI CMOS technology process [24] as this technology offers isolated transistors with a built-in insulator between the substrate and the transistor channel. Moreover, there is no parasitic substrate current by using forward-body-biasing in FD-SOI technologies.
The width W of each unit transistor, both in the OTA-A and OTA-B, is set on the basis of the minimum sizing requirement of the isolated n-well and p-well. Based on this, all the unit transistors, both PMOS and NMOS, in OTA-A and OTA-B (see Figures 4b and 5b) have an identical aspect ratio equal to W L The layouts of the OTA-A and OTA-B are shown in Figure 6a,b, respectively. These figures depict how systematic mismatch reduction layout techniques, such as common centroid and dummy transistors, were employed in both OTAs. The name of the unit transistor are placed on top of each instance in the layout.

Simulation Results
The performance of both OTA-A and OTA-B, designed in TSMC 180 nm CMOS technology, operating at 27 • C, 0.3 V supply voltage, has been validated by using an open-loop and a non-inverting buffer OTA test-bench circuits with a 10 pF capacitive load C L . Circuits are respectively shown in Figure 7a,b. These two test-benches are aimed to characterize input and output voltage swings, and output voltage linearity of OTAs.   Figure 8b depicts the exponential increment of the current consumption with the voltage supply. Notice that the OTAs are self-biased, thus no extra power consumption related to additional voltage/current reference current has to be considered. The reported results refer to an input voltage equal to V DD /2 where the voltage gain assumes the maximum value. Moreover, the supply voltage affects the OTAs' gains as a consequence of the reverse transistor current and channel length modulation [23]. For these reasons, Figure 9a

Unity-Gain Buffer Analysis
As with the output voltage swing limitations observed in open-loop DC simulations (as in Figure 7a), the non-inverting buffer simulations (as in Figure 7) also reveal the limits of input voltage swing, which are shown in Figure 12. In particular, Figure 12a shows how the output voltage saturation is a consequence of the voltage gain from the input IN+ to node X. As can be seen, V X ≈ − A VX (V I N+ − V DD /2) + V DD /2 and A VX ≈ 1/(n − 1) for OTA-A, where A VX is the voltage gain between V X and V I N+ . This means that the positive input voltage range is limited to approximately V DD /2 ± (n − 1)V DD /2. This effect is explained in more detail [21] for the OTA-A fully differential counterpart, the Bulk Nauta OTA. The OTA-B has a slightly shorter input range, since one of the composite transistor bulk terminals are biased by the voltage supply instead of V X and does not contribute to common-mode voltage rejection.
The same limitations, from the point of view of time-domain, are shown in Figure 13a for a rail-to-rail input sine-wave. The corresponding total harmonic distortion (THD) is displayed in Figure 13b. A total harmonic distortion of 1% is achieved for input ranges of 70 mV and 35 mV in OTA-A and OTA-B, respectively.  Table 1 summarizes the mean µ and the standard variation σ from 1000 Monte Carlo simulation runs. Process and mismatch variations are analyzed individually and combined. Results show that gain-bandwidth product GBW, total current I DD , and power consumption are greatly affected by the process variability. This also results from not using current references for biasing the OTAs. The power efficiency Figure [25] or by increasing the transistor arrays' sizes [20]. Table 2 summarizes the corner simulation results. As expected, the greatest deviations from typical corner results are GBW and power for SS (Slow-Slow) and FF (Fast-Fast) corners, and the intrinsic input offset voltage for SF (Slow-Fast) and FS (Fast-Slow) corners.

Performance Comparison
The proposed OTAs are gate input-driven, single-ended, and single-stage and therefore offer compact layouts and power efficiency. The characteristics are summarized and compared with the state of the art in Table 3. The proposed OTA-A is a single-ended version of the fully-differential bulk-nauta OTA presented in [21] that uses conventional composite transistors to increase its voltage gain. Thus, OTA-A would offer similar performance with 2× less area and power consumption.  Technology  180  130  130  180  180  180  180  130  65  65  180  180  180  nm  Input  GD  GD  GD  GD  GD  GD  BD  BD  BD  BD  BD  GD  GD  Bulk-driven OTAs, like those proposed in [8][9][10][11]18], are intrinsically more linear and have a larger input voltage range than its gate-driven OTAs counterparts. However, those OTAs deliver a lower transconductance for a given power consumption as can be highlighted from their Figure of Merit (FoM). In addition, bulk-driven OTAs have finite DC input impedance, which could affect previous gain stages. The proposed OTA linearity is limited by the input-voltage excursion, as explained in the previous sections. The THD of both OTA-A and OTA-B are comparable to the other gate-driven inverter-based OTAs shown in the table and their FoMs are the second best after [25], which use extra digital-assisted circuitry.
Multiple-stage OTAs show higher voltage gains at the cost of area and power consumption. Additionally, they need frequency stability circuits to work properly with negative feedback circuits, which costs even more area and power. The OTAs proposed in [9][10][11]18] are multiple stage OTAs whose first stages are bulk-driven OTAs and the subsequent stages are gate-driven OTAs, which combines the linearity and input range of the bulk-driven OTAs and the voltage gain of gate-driven OTAs. The proposed OTAs have a greater voltage gain than all single-stage OTAs, with the exception of the OTA proposed in [21], which uses larger composite transistors and operates at a higher supply voltage. Most of the presented multiple-stage OTAs have a greater voltage-gain, but their voltage gain over the number of stages are below those of the proposed OTAs.

Conclusions
This paper introduces two inverter-based OTA topologies to increase the voltage gain without reducing output voltage swing and with a minor linearity degradation for ultra-low-voltage supplies. Proposed OTAs exploit two topological solutions consist of using rectangular arrays for PMOS and NMOS charge mobility balancing and forward-body biasing for common-mode rejection. For analyzing the contribution of each solution individually, OTA-A has been designed as a conventional inverter-based single-end OTA whose equivalent pull-up and pull-down networks are made of rectangular transistor arrays to achieve the smallest area possible. On the other hand, the OTA-B design allies the properties of such rectangular transistors to the improved composite transistor with independent body-bias.
The bulk terminals of the two rectangular transistor arrays which compose the improved composite transistor (pull-up and pull-down network of each branch of the OTA-B) are tied to different voltages. This provides an enhancement of 11 dB on voltage gain for a supply voltage equal to V DD = 0.3 V, which is equivalent to the voltage gain enhancement of a conventional composite transistor with 2.5× area increase.
Compared with other state-of-art OTAs in similar operation conditions, the proposed OTAs have the largest voltage gain by the number of amplifier gain stages (39 and 51 dB), smallest die-area (472 and 727 µm 2 ), and is among the most power-efficient (447 and 443 V −1 FoM). The improved self-cascode technique applied to composite transistors can be extended to other inverter-based topologies such as multiple-stage and fully-differential OTAs. Moreover, the same technique can exploit the FD-SOI technologies ability of providing forward-body-bias at higher supply voltages.

Abbreviations
The following abbreviations are used in this manuscript: