Mismatch Insensitive Voltage Level Shifter Based on Two Feedback Loops

: This paper presents a voltage level shifter (VLS) based on two feedback loops. The complementary feedback signals in the high voltage domain are re-used to assist voltage conversion and the complementary phase in the low voltage domain is not required. Unlike the conventional VLS, which depends on the pull-up network and pull-down network to achieve level shift, the transitions of both high-to-low and low-to-high of the proposed VLS are undertaken by two di ﬀ erent feedback loops, respectively. Implemented in a standard 180 nm CMOS process, post-layout Monte Carlo (MC) simulations from 4000 points under mismatch variation show that the dynamic power (DP) and the propagation delay (PD) of the proposed VLS are 105.3 nW and 2.0 ns, respectively, at an input voltage V IN = 0.4 V with input frequency f in = 0.1 MHz. Meanwhile, the excellent normalized standard deviation of DP and PD is obtained with the proposed scheme. The temperature range for normal operation is from − 20 ◦ C to 85 ◦ C.


Introduction
With the development of integration technology, aggressive supply voltage (VDD) scaling is one of the main streams to reduce dynamic power consumption, short-circuit power dissipation, and leakage current for digital circuits and systems. However, for RF and analog circuit, a low voltage supply may deteriorate their performance, such as the bandwidth, the intrinsic gain, and linearity [1]. In order to obtain a satisfying tradeoff, the multi-supply voltage domain (MSVD) technique [2,3] is becoming a popular method in today's system-on-chip (SoC), as shown in Figure 1. For MSVD systems, VLSs are indispensable and employed to convert the logic level in a low supply voltage (V DDL ) to the logical level in a high supply voltage (V DDH ), as shown in Figure 1.
Conventional voltage level shifters (VLSs) can be categorized into two main types: the differential cascade voltage switch (DCVS)-based architecture [4][5][6][7] and the current mirror (CM)-based architecture [3,[8][9][10][11][12][13][14], as shown in Figure 2. For the DCVS-based architecture, indicated in Figure 2a, a cross-coupled pair constituting by MP1 and MP2 as a pull-up network enables the nodes Q1 and Q2 to switch faster. Thus, the standby power is close to zero owing to the complementary pull-up and pull-down network. However, the major drawback is the strong contention between the two networks during the switching period. When the input voltage V IN and V DDL reduces to less than the threshold voltage of transistors, the strength of the pull-up network remains unchanged, while the strength of the pull-down network constituted by MN1 and MN2 is aggressively declined owing to the reduction of the voltage difference between the gate and the source of the pull-down network. Although the Conventional voltage level shifters (VLSs) can be categorized into two main types: the differential cascade voltage switch (DCVS)-based architecture [4][5][6][7] and the current mirror (CM)-based architecture [3,[8][9][10][11][12][13][14], as shown in Figure 2. For the DCVS-based architecture, indicated in Figure 2a, a cross-coupled pair constituting by MP1 and MP2 as a pull-up network enables the nodes Q1 and Q2 to switch faster. Thus, the standby power is close to zero owing to the complementary pull-up and pull-down network. However, the major drawback is the strong contention between the two networks during the switching period. When the input voltage VIN and VDDL reduces to less than the threshold voltage of transistors, the strength of the pull-up network remains unchanged, while the strength of the pull-down network constituted by MN1 and MN2 is aggressively declined owing to the reduction of the voltage difference between the gate and the source of the pull-down network. Although the strength of the pull-down network can be enhanced by upsizing the pull-down transistors (MN1 and MN2), it will deteriorate the propagation delay (PD) and dynamic power (DP) as the sizing ratio can be extremely large [8,9]. For the CM-based architecture, as shown in Figure 2b, the cross-coupled pair is replaced by a basic current mirror, thus the strength of the pull-up network is weaken for wide range voltage conversion and lower contention between pull-up and pull-down networks is obtained. However, the major drawback of the CM-based architecture is the large static current flowing through MP1 and MN1.  Conventional voltage level shifters (VLSs) can be categorized into two main types: the differential cascade voltage switch (DCVS)-based architecture [4][5][6][7] and the current mirror (CM)-based architecture [3,[8][9][10][11][12][13][14], as shown in Figure 2. For the DCVS-based architecture, indicated in Figure 2a, a cross-coupled pair constituting by MP1 and MP2 as a pull-up network enables the nodes Q1 and Q2 to switch faster. Thus, the standby power is close to zero owing to the complementary pull-up and pull-down network. However, the major drawback is the strong contention between the two networks during the switching period. When the input voltage VIN and VDDL reduces to less than the threshold voltage of transistors, the strength of the pull-up network remains unchanged, while the strength of the pull-down network constituted by MN1 and MN2 is aggressively declined owing to the reduction of the voltage difference between the gate and the source of the pull-down network. Although the strength of the pull-down network can be enhanced by upsizing the pull-down transistors (MN1 and MN2), it will deteriorate the propagation delay (PD) and dynamic power (DP) as the sizing ratio can be extremely large [8,9]. For the CM-based architecture, as shown in Figure 2b, the cross-coupled pair is replaced by a basic current mirror, thus the strength of the pull-up network is weaken for wide range voltage conversion and lower contention between pull-up and pull-down networks is obtained. However, the major drawback of the CM-based architecture is the large static current flowing through MP1 and MN1. Both of the above architectures achieve the voltage shift based on the strength between the pull-up network and pull-down network. Thus, the complementary phase of VIN in the low voltage domain is inevitable. In this paper, a novel VLS without the complementary phase in the low voltage Both of the above architectures achieve the voltage shift based on the strength between the pull-up network and pull-down network. Thus, the complementary phase of V IN in the low voltage domain is inevitable. In this paper, a novel VLS without the complementary phase in the low voltage domain is proposed. The conversion of the logic level from the low voltage domain to the high voltage domain is achieved by two feedback loops.
The rest of the paper is organized as follows. Section 2 introduces the proposed circuit scheme, including the detailed operations. Section 3 presents the post-layout simulation results and comparison with prior arts. Finally, the conclusion is drawn in Section 4.

Proposed Circuit Scheme
The complementary phase in high voltage domain is re-used to assist the voltage level shift in the low voltage domain. As shown in Figure 3a, two complementary feedback signals from the high voltage domain are injected into the low voltage domain. The corresponding transistor-level scheme is presented in Figure 3b, where V IN controls the gate of MN1, which can pull down the node A when V IN is high. MP5 acts as a current-limit resistor. MP2, MN2, MP3, and MN3 form two cascaded inverters, INV1 and INV2. C L represents the load capacitor. Thus, the complementary phases are generated in the high voltage domain, which are re-used to assist the operation of VLS. Owing to the feedback signal from node C, MP1, INV1, and INV2 are connected like a three-stage ring oscillator. MP4 and INV1 form a positive feedback in order to achieve the high-to-low transition.
domain is proposed. The conversion of the logic level from the low voltage domain to the high voltage domain is achieved by two feedback loops.
The rest of the paper is organized as follows. Section 2 introduces the proposed circuit scheme, including the detailed operations. Section 3 presents the post-layout simulation results and comparison with prior arts. Finally, the conclusion is drawn in Section 4.

Proposed Circuit Scheme
The complementary phase in high voltage domain is re-used to assist the voltage level shift in the low voltage domain. As shown in Figure 3a, two complementary feedback signals from the high voltage domain are injected into the low voltage domain. The corresponding transistor-level scheme is presented in Figure 3b, where VIN controls the gate of MN1, which can pull down the node A when VIN is high. MP5 acts as a current-limit resistor. MP2, MN2, MP3, and MN3 form two cascaded inverters, INV1 and INV2. CL represents the load capacitor. Thus, the complementary phases are generated in the high voltage domain, which are re-used to assist the operation of VLS. Owing to the feedback signal from node C, MP1, INV1, and INV2 are connected like a three-stage ring oscillator. MP4 and INV1 form a positive feedback in order to achieve the high-to-low transition.  The detailed operations for the low-to-high transition and the high-to-low transition are presented in Figure 4a,b, respectively. As shown in Figure 4a, for the initial moment, the voltage of the node A is high, which is larger than the switching threshold of INV1. The voltage of node B is low in the high voltage domain. When VIN is low-to-high, MN1 is on and the parasitic capacitors in the node A are discharged at this moment. As the MOS MP4 is small enough, finally, the node A is pulled down to GND. The voltage of node B is converted to high in the high voltage domain. Thus, the high level in the low voltage domain is shifted into the high voltage domain at node B.
As for the high-to-low transition, shown in Figure 4b, at the initial moment, the voltage of node A is low and the voltage of the node B is high. When VIN is high-to-low, MN1 and MP1 are off. Node A starts to rise up though the leakage path VDDH-MP5-MP1-MN1-GND. Once the voltage of node A reaches the switching threshold of INV1, MN2 is on. The voltage of node B will be pulled down to GND by MN2 in the high voltage domain and the voltage of node A will be aggressively lifted up to The detailed operations for the low-to-high transition and the high-to-low transition are presented in Figure 4a,b, respectively. As shown in Figure 4a, for the initial moment, the voltage of the node A is high, which is larger than the switching threshold of INV1. The voltage of node B is low in the high voltage domain. When V IN is low-to-high, MN1 is on and the parasitic capacitors in the node A are discharged at this moment. As the MOS MP4 is small enough, finally, the node A is pulled down to GND. The voltage of node B is converted to high in the high voltage domain. Thus, the high level in the low voltage domain is shifted into the high voltage domain at node B.
As for the high-to-low transition, shown in Figure 4b, at the initial moment, the voltage of node A is low and the voltage of the node B is high. When V IN is high-to-low, MN1 and MP1 are off. Node A starts to rise up though the leakage path V DDH -MP5-MP1-MN1-GND. Once the voltage of node A reaches the switching threshold of INV1, MN2 is on. The voltage of node B will be pulled down to GND by MN2 in the high voltage domain and the voltage of node A will be aggressively lifted up to V DDH by the positive feedback loop. This positive feedback accelerates the voltage setting of node A. Thus, the low level in the low voltage domain is shifted into the high voltage domain at node B.
On the basis of the above analysis, it is clear that the proposed VLS conducts the level shift by the assistance of the feedback signals from the high voltage domain. The complementary phases in the  Properly designing the size for MN1, MP1, MP4, and MP5 can guarantee the normal operation of the proposed VLS at five process corners (TT, SS, FF, SNFP, and FNSP) under −20 °C to 85 °C. In order to ensure the normal operation under VDDL = 0.3 V, the medium threshold voltage transistor is chosen as MN1 to enhance the current injection efficiency at low input voltage. The size of the transistors used for the proposed VLS is listed in Table 1.  Properly designing the size for MN1, MP1, MP4, and MP5 can guarantee the normal operation of the proposed VLS at five process corners (TT, SS, FF, SNFP, and FNSP) under −20 • C to 85 • C. In order to ensure the normal operation under V DDL = 0.3 V, the medium threshold voltage transistor is chosen as MN1 to enhance the current injection efficiency at low input voltage. The size of the transistors used for the proposed VLS is listed in Table 1.

Simulation Results
In order to verify the performance of the proposed VLS, it was implemented in a standard 180 nm CMOS process and the physical layout is shown in Figure 5, where each transistor is enclosed by guard rings. It consumes an area of 25 µm × 15 µm. Owing to the introduction of guard rings, the layout of Electronics 2020, 9, 1391 5 of 10 the proposed VLS consumes more area than in [4,11,14], but it features more reliability. Meanwhile, as the area of a system is usually dominated by other core circuits, the area increase of the proposed VLS is almost negligible.
The Cadence Spectre simulator is used for the post-layout verification. The parasitic parameters are extracted by Calibre xRC (Mentor Graphics Corporation, Wilsonville, AL, USA). The extraction netlist includes the parasitic capacitors, the parasitic resistors, and the parasitic diodes in the physical layout. It is noteworthy that the loading condition is assumed as an inverter at the output.
Electronics 2020, 9, x FOR PEER REVIEW 5 of 10 In order to verify the performance of the proposed VLS, it was implemented in a standard 180 nm CMOS process and the physical layout is shown in Figure 5, where each transistor is enclosed by guard rings. It consumes an area of 25 μm × 15 μm. Owing to the introduction of guard rings, the layout of the proposed VLS consumes more area than in [4,11,14], but it features more reliability. Meanwhile, as the area of a system is usually dominated by other core circuits, the area increase of the proposed VLS is almost negligible.
The Cadence Spectre simulator is used for the post-layout verification. The parasitic parameters are extracted by Calibre xRC (Mentor Graphics Corporation, Wilsonville, AL, USA). The extraction netlist includes the parasitic capacitors, the parasitic resistors, and the parasitic diodes in the physical layout. It is noteworthy that the loading condition is assumed as an inverter at the output. The simulated performance of the proposed VLS in terms of static power consumption, DP, and PD is presented. As shown in Figure 6, the static power consumption is illustrated including five process corners. The static power consumption is less than 1 nW at the TT corner under 27 °C when VDDL = 0 V and the process corner FF features the highest static power, as shown in Figure 6a. Figure  6b presents the static power consumption when VDDL = 0.3 V. Comparing Figure 6a with Figure 6b, it is obvious that the static power consumption increases with the increase of temperature and the static power under VDDL = 0.3 V is much larger. This is because the static power is contributed by the leakage current. With the increase of temperature, the threshold of transistors becomes smaller, thus larger static power is observed under both VDDL = 0 V and VDDL = 0.3 V. The reason larger static power is observed under VDDL = 0.3 V is that resistance between VDDH and ground becomes smaller when MN1 and MP1 are on. Figure 6c shows the static power under different VDDL at 27 °C. Once MN1 and MP1 are on, larger VDDL hardly influences the static power. The simulated performance of the proposed VLS in terms of static power consumption, DP, and PD is presented. As shown in Figure 6, the static power consumption is illustrated including five process corners. The static power consumption is less than 1 nW at the TT corner under 27 • C when V DDL = 0 V and the process corner FF features the highest static power, as shown in Figure 6a. Figure 6b presents the static power consumption when V DDL = 0.3 V. Comparing Figure 6a with Figure 6b, it is obvious that the static power consumption increases with the increase of temperature and the static power under V DDL = 0.3 V is much larger. This is because the static power is contributed by the leakage current. With the increase of temperature, the threshold of transistors becomes smaller, thus larger static power is observed under both V DDL = 0 V and V DDL = 0.3 V. The reason larger static power is observed under V DDL = 0.3 V is that resistance between V DDH and ground becomes smaller when MN1 and MP1 are on. Figure 6c shows the static power under different V DDL at 27 • C. Once MN1 and MP1 are on, larger V DDL hardly influences the static power. Figure 7 shows the simulated transient behavior of proposed VLS under different V DDH with f in = 0.1 MHz. As high V DDH means large power consumption and low V DDH may cause performance deterioration, V DDH = 1 V is chosen as the typical operation mode, as indicated in Figure 1. As shown in Figure 7a, for the rise transient, more time is required in order to reach higher V DDH . For the fall transient, a large delay occurs, as shown in Figure 7b. This is because the charging current contributed by the leakage current at node A is much smaller when both MN1 and MP1 are off, as indicated in Figure 4b. This can be mitigated by higher V DDH . However, when the input frequency is lower than 0.1 MHz, such as the audio application, the fall delay causes little damage to the input signal. When the input frequency is much higher than 0.1 MHz, such as 10 MHz, the proposed scheme fails. For the case of 1 MHz, the proposed scheme works well for most cases except for the change in duty cycle. This issue can be overcome with the duty cycle calibration circuit if 50% duty cycle is required.
static power under VDDL = 0.3 V is much larger. This is because the static power is contributed by the leakage current. With the increase of temperature, the threshold of transistors becomes smaller, thus larger static power is observed under both VDDL = 0 V and VDDL = 0.3 V. The reason larger static power is observed under VDDL = 0.3 V is that resistance between VDDH and ground becomes smaller when MN1 and MP1 are on. Figure 6c shows the static power under different VDDL at 27 °C. Once MN1 and MP1 are on, larger VDDL hardly influences the static power.  Figure 7 shows the simulated transient behavior of proposed VLS under different VDDH with fin = 0.1 MHz. As high VDDH means large power consumption and low VDDH may cause performance deterioration, VDDH = 1 V is chosen as the typical operation mode, as indicated in Figure 1. As shown in Figure 7a, for the rise transient, more time is required in order to reach higher VDDH. For the fall transient, a large delay occurs, as shown in Figure 7b. This is because the charging current contributed by the leakage current at node A is much smaller when both MN1 and MP1 are off, as indicated in Figure 4b. This can be mitigated by higher VDDH. However, when the input frequency is lower than 0.1 MHz, such as the audio application, the fall delay causes little damage to the input signal. When the input frequency is much higher than 0.1 MHz, such as 10 MHz, the proposed scheme fails. For the case of 1 MHz, the proposed scheme works well for most cases except for the change in duty cycle. This issue can be overcome with the duty cycle calibration circuit if 50% duty cycle is required.  Figure 7 shows the simulated transient behavior of proposed VLS under different VDDH with fin = 0.1 MHz. As high VDDH means large power consumption and low VDDH may cause performance deterioration, VDDH = 1 V is chosen as the typical operation mode, as indicated in Figure 1. As shown in Figure 7a, for the rise transient, more time is required in order to reach higher VDDH. For the fall transient, a large delay occurs, as shown in Figure 7b. This is because the charging current contributed by the leakage current at node A is much smaller when both MN1 and MP1 are off, as indicated in Figure 4b. This can be mitigated by higher VDDH. However, when the input frequency is lower than 0.1 MHz, such as the audio application, the fall delay causes little damage to the input signal. When the input frequency is much higher than 0.1 MHz, such as 10 MHz, the proposed scheme fails. For the case of 1 MHz, the proposed scheme works well for most cases except for the change in duty cycle. This issue can be overcome with the duty cycle calibration circuit if 50% duty cycle is required.  Figure 8 illustrates the performance of the proposed VLS versus VDDL in terms of DP and PD, including five process corners. Figure 8a shows that the process corners have a direct influence on DP, while VDDL has no effect on DP as DP is a threshold-dependent performance metric. Figure 8b indicates that both VDDL and process corners have little influence on PD when VDDL is above 0.4 V.  Figure 8 illustrates the performance of the proposed VLS versus V DDL in terms of DP and PD, including five process corners. Figure 8a shows that the process corners have a direct influence on Electronics 2020, 9, 1391 7 of 10 DP, while V DDL has no effect on DP as DP is a threshold-dependent performance metric. Figure 8b indicates that both V DDL and process corners have little influence on PD when V DDL is above 0.4 V.  Figure 9 shows the performance of the proposed VLS versus temperature in terms of the DP and PD, including five process corners. Figure 9a indicates that DP is linearly proportional to the increase of temperature over the range from −20 °C to 85 °C. PD declines in inverse proportion to temperature, as shown in Figure 9b. In order to verify the robustness of the proposed VLS to mismatch, Monte Carlo (MC) simulation is conducted. In the setup form of MC simulation, the statistical variation includes three choices: process, mismatch, and both. The term 'process' means that only the process variation is considered. The corresponding statistical sigma σprocess is 1/3. The term 'mismatch' means that only the mismatch variation is considered. The corresponding statistical sigma σmismatch is 1/1, which indicates the mismatch variation follows the standard normal distribution. The term 'both' indicates the above two variations are considered in the MC simulation. In order to evaluate the performance of the proposed VLS, the MC simulations were conducted under 'mismatch'. Figure 10 shows the post-layout simulated MC results for 4000 points to evaluate DP of the proposed VLS under different VDDL with mismatch variation. The simulation is conducted under fin = 0.1 MHz and 1 MHz, respectively. As shown in Figure 10a, the mean DP (μDP_0.1 MHz) and the standard deviation (σDP_0.1 MHz) for 0.1 MHz at VDDL = 0.3 V are 104 nW and 2.97 nW, respectively. The results for μDP_1 MHz and σDP_1 MHz when fin is 1 MHz are shown in Figure 10b, which are 565 nW and 29.15 nW,  Figure 9 shows the performance of the proposed VLS versus temperature in terms of the DP and PD, including five process corners. Figure 9a indicates that DP is linearly proportional to the increase of temperature over the range from −20 • C to 85 • C. PD declines in inverse proportion to temperature, as shown in Figure 9b.  Figure 9 shows the performance of the proposed VLS versus temperature in terms of the DP and PD, including five process corners. Figure 9a indicates that DP is linearly proportional to the increase of temperature over the range from −20 °C to 85 °C. PD declines in inverse proportion to temperature, as shown in Figure 9b. In order to verify the robustness of the proposed VLS to mismatch, Monte Carlo (MC) simulation is conducted. In the setup form of MC simulation, the statistical variation includes three choices: process, mismatch, and both. The term 'process' means that only the process variation is considered. The corresponding statistical sigma σprocess is 1/3. The term 'mismatch' means that only the mismatch variation is considered. The corresponding statistical sigma σmismatch is 1/1, which indicates the mismatch variation follows the standard normal distribution. The term 'both' indicates the above two variations are considered in the MC simulation. In order to evaluate the performance of the proposed VLS, the MC simulations were conducted under 'mismatch'. Figure 10 shows the post-layout simulated MC results for 4000 points to evaluate DP of the proposed VLS under different VDDL with mismatch variation. The simulation is conducted under fin = 0.1 MHz and 1 MHz, respectively. As shown in Figure 10a, the mean DP (μDP_0.1 MHz) and the standard deviation (σDP_0.1 MHz) for 0.1 MHz at VDDL = 0.3 V are 104 nW and 2.97 nW, respectively. The results for μDP_1 MHz and σDP_1 MHz when fin is 1 MHz are shown in Figure 10b, which are 565 nW and 29.15 nW, In order to verify the robustness of the proposed VLS to mismatch, Monte Carlo (MC) simulation is conducted. In the setup form of MC simulation, the statistical variation includes three choices: process, mismatch, and both. The term 'process' means that only the process variation is considered. The corresponding statistical sigma σ process is 1/3. The term 'mismatch' means that only the mismatch variation is considered. The corresponding statistical sigma σ mismatch is 1/1, which indicates the mismatch variation follows the standard normal distribution. The term 'both' indicates the above two variations are considered in the MC simulation. In order to evaluate the performance of the proposed VLS, the MC simulations were conducted under 'mismatch'. Figure 10 shows the post-layout simulated MC results for 4000 points to evaluate DP of the proposed VLS under different V DDL with mismatch variation. The simulation is conducted under Electronics 2020, 9,1391 8 of 10 f in = 0.1 MHz and 1 MHz, respectively. As shown in Figure 10a, the mean DP (µ DP_0.1 MHz ) and the standard deviation (σ DP_0.1 MHz ) for 0.1 MHz at V DDL = 0.3 V are 104 nW and 2.97 nW, respectively. The results for µ DP_1 MHz and σ DP_1 MHz when f in is 1 MHz are shown in Figure 10b, which are 565 nW and 29.15 nW, respectively, although five points fail in the simulation owing to the larger fall delay. Figure 10c shows the results for µ DP_0. respectively, although five points fail in the simulation owing to the larger fall delay. Figure 10c shows the results for μDP_0.      Table 2 tabulates the performance comparison of the proposed VLS with the prior designs. The following figure of merit termed power-delay product (PDP) is used to evaluating the performance of all works proposed in literature, as shown in (1): As indicated in Table 2, the performance comparison is presented. Because the area of the proposed VLS is larger than other works, it achieves the minimal normalized standard deviation (σ/μ) of DP and PD. The corresponding σDP/μDP and σPD/μPD for fin = 0.1 MHz and VDDL = 0.4 V are 0.02 and 0.028, respectively. Compared with [3], when VDDL is 0.4 MHz and fin is 1 MHz, although DP of the proposed scheme is larger, a competitive PDP is obtained by excellent PD. As there is no circuit powered by VDDL in the proposed VLS, DP is almost irrelevant to VDDL and is mainly decided by fin and VDDH. Meanwhile, because the delay is mainly contributed by the capacitance and the resistance of corresponding nodes, PD is almost irrelevant to fin.  3 Only mismatch is considered.  Table 2 tabulates the performance comparison of the proposed VLS with the prior designs. The following figure of merit termed power-delay product (PDP) is used to evaluating the performance of all works proposed in literature, as shown in (1): As indicated in Table 2, the performance comparison is presented. Because the area of the proposed VLS is larger than other works, it achieves the minimal normalized standard deviation (σ/µ) of DP and PD. The corresponding σ DP /µ DP and σ PD /µ PD for f in = 0.1 MHz and V DDL = 0.4 V are 0.02 and 0.028, respectively. Compared with [3], when V DDL is 0.4 MHz and f in is 1 MHz, although DP of the proposed scheme is larger, a competitive PDP is obtained by excellent PD. As there is no circuit powered by V DDL in the proposed VLS, DP is almost irrelevant to V DDL and is mainly decided by f in and V DDH . Meanwhile, because the delay is mainly contributed by the capacitance and the resistance of corresponding nodes, PD is almost irrelevant to f in . Table 2. Performance comparison. DP, dynamic power; PD, propagation delay; DCVS, differential cascade voltage switch; CM, current mirror; PDP, power-delay product.

Conclusions
A VLS based on two feedback loops is reported. The complementary phase in the high voltage domain is re-used to assist the voltage conversion and no complementary phase is required in the low voltage domain. The results indicate that considerably lower PDP and minimum PD can be obtained with the proposed VLS. It features potential application in audio application for its excellent PDP. It can ensure normal operation from −20 • C to 85 • C under five different corners at f in = 0.1 MHZ.
Author Contributions: Z.X., Z.W., and J.W. organized this work. The idea was proposed by Z.X. The pre-simulation was conducted by Z.X. The layout and post-simulation were achieved by Z.W. The manuscript was written and edited by Z.X. The funding was provided by J.W., J.W. also supervised and provided guidelines through the whole process of this work. All authors have read and agreed to the published version of the manuscript.

Conflicts of Interest:
The authors declare no conflict of interest.