An Energy-E ﬃ cient Integration of a Digital Modulator and a Class-D Ampliﬁer

: Energy consumption is always a key feature in devices powered by electric accumulators. The power ampliﬁer is the most energy-demanding module in mobile devices, portable appliances, static transceivers


Introduction
With the increasing demand for mobility, more devices incorporating digital wireless communication systems are being operated by electric accumulators (batteries), e.g., human surveillance to crops monitoring, and aerial drones to autonomous underwater vehicles (AUVs).Preserving an accumulator's energy is of paramount importance in difficult-to-access areas, which is also the case in underwater communication systems.If the system incorporates a communication transceiver, the most energy-consuming element is the power amplifier that follows the modulator.Designers have conceived different technologies for power amplification, which are denominated into classes and denoted by capital letters: Class A, B, AB, and D. Class-D amplifiers are the most efficient in terms of power, with values on the order of 90% in practical designs [1], and are preferred in applications where autonomy is essential.
A traditional class-D amplifier consists of an analog modulator of a digital carrier followed by a switch circuit that drives the current from a DC power supply.This current passes to the load through a filter that retrieves the baseband signal.Due to their complexity, class-D amplifiers are not appropriate for small signals, but in power applications, they are the best choice because of their low losses.Obviously, the power delivered to the load is sensitive to the voltage of the DC source, and the switch has to be able to drive high current.In many of their applications, class-D amplifiers are used at high fidelity (hi-fi, 20 Hz-20 kHz) frequencies and the retrieving filter is a low-pass filter (LPF).If the amplifier is intended to be at the output stage of an ultrasonic communication system, a band-pass filter (BPF) is incorporated.
Usually, a PW-modulator is available at the input stage of a class-D amplifier.The frequency of the digital carrier of the PW-modulator must be greater than the highest frequency of the analog input signal, typically ten times.However, again, if the amplifier is part of a digital communication system, the analog input signal to the amplifier will be the output signal of a digital modulator that could be a phase-shift keying (PSK) or a frequency-shift keying (FSK) modulator.That is, the digital signal at the input of the communication transmitter will modulate an analog carrier, modulate again a digital carrier at a much higher frequency, and finally be restored to the digital modulated signal.
In our proposed design, integration of a PW-modulator of a class-D amplifier and BPF provides (a) signal amplification, (b) filtering, and (c) generation of a PSK-modulated output.The digital signal applied at the input of the class-D amplifier directly drives the power switch.This novelty in the design prevents the need of modulation before amplification, which makes the proposed design energy efficient as well as inexpensive.Finally, a BPF is used instead of a LPF at the output of the class-D amplifier to obtain an amplified PSK-modulated signal.This complex modulation is performed on a real-time basis using the ability of the class-D amplifier to provide high-efficiency in order to prolong battery life [2].
The remaining article is structured as follows.Section 2 briefly explains the state-of-the-art.Section 3 provides the theoretical background.Section 4 discusses the block diagram of the integrated system.Section 5 presents the experimental setup and results.Finally, Section 6 has the concluding remarks.

State-of-the-Art
In the past few years, several class-D amplifier designs and modulation schemes have been presented, and some of them are briefly discussed in the following section.
The class-D amplifier [3] is based on a digital pulse-width modulator.It receives digital input data and uses a digital loop filter to reduce distortion and mitigate the need of an analog-to-digital converter.The system is designed for low output power up to 1.2 W, and to keep away from the necessities of additional filtering, a sigma-delta modulator is used.The proposed system is designed using complementary metal-oxide-semiconductor (CMOS) technology and has been tested to drive a load of an 8 Ω speaker with a signal-to-noise ratio (SNR) of 99.9 dB with 91% efficiency.
A class-D amplifier based on the delta-sigma modulator with uniform pulse-width modulation is presented in [4].The major design blocks are an interpolation filter, digital delta-sigma modulator, uniform pulse-width modulator, driver circuitry, and power stage.A 1-bit, 6th-order noise shaping modulator with a uniform pulse-width modulator quantizer is used along with the pole moving technique to balance the modulator and make the noise transfer function more determined.The system has been simulated with a 1 kHz sine wave, and a 120 dB SNR has been achieved.
In [5], a high-power pulse-width modulation model based on the class-D amplifier is discussed.To eliminate the effect of 3rd and 5th harmonics, the proposed triple-pulse model is designed by adding two narrow pulses with an equivalent comparative to the original single pulse.Initially, the model is verified by simulations, and then a platform is designed with underwater acoustic transducers submerged in a water tank to test the functionality of the system.From the experiments, it was found that the proposed amplifier consumes low power, which reduces 41% of the 3rd and 5th harmonic energy [5].
A class-D amplifier using pulse-width modulation is designed in [6].The system consists of modulation, and power and filter stages.In this research, two modulation techniques: (a) Pulse-width modulation and (b) pulse density modulation, are used.The system has been verified by PSpice simulations to test the total harmonic distortion using both modulation techniques with a 1 kHz test tone and switching frequency in the range of 300-800 kHz.From the simulations, it was found that the total harmonic distortion of the pulse density modulation is less at higher frequencies.
A low-voltage class-D amplifier design is presented in [7].The objective of the research is to propose a class-D amplifier for audio applications with minimum distortion.The analysis is performed using a pulse density modulation (PDM) technique for different test tone frequency ranges from 0.7 to 5 kHz with three amplitudes, 0.5, 0.8, and 1.0 V, using the carrier frequency range of 500-2000 kHz.From the results, it was found that the total harmonic distortion is a function of both amplitude and frequency of the test tone.For the highest switching frequency, i.e., 2000 kHz, and at the smallest amplitude of the input signal, the lowest value of total harmonic distortion was achieved at less than 1%.

Theoretical Background
PW-modulations can be classified according to several criteria.The first is pulse values, which can be symmetric or asymmetric.The former means V L = 0 V and the later means V L = −V H , where V L and V H are, respectively, the low and high levels of the output voltage.The symmetric case is slightly more complex to generate from the circuit point of view, and its frequency spectrum has a much lower DC component and larger fundamental and harmonic components.However, other than that, it has little influence on the frequency spectrum of the modulated signal.
A second criterion is related to the fact that the input is a continuous signal but the output signal is a train of pulses, which means that the input signal has been somehow sampled at certain instants.The way sampling is performed also has an impact on the frequency spectrum.There are two options, the so-called uniform sampling, when it is synchronous with the system clock, or the natural sampling, which happens when simple circuits are used to modulate the pulses, i.e., when sampling is achieved by a simple comparator circuit and is not synchronous with the system clock.The basic block diagram of a PW-modulator is shown in Figure 1 [8].Of course, the average sampling frequency over a long period of time is the frequency of the system clock.
Electronics 2020, 9, x FOR PEER REVIEW 3 of 12 performed using a pulse density modulation (PDM) technique for different test tone frequency ranges from 0.7 to 5 kHz with three amplitudes, 0.5, 0.8, and 1.0 V, using the carrier frequency range of 500-2000 kHz.From the results, it was found that the total harmonic distortion is a function of both amplitude and frequency of the test tone.For the highest switching frequency, i.e., 2000 kHz, and at the smallest amplitude of the input signal, the lowest value of total harmonic distortion was achieved at less than 1%.

Theoretical Background
PW-modulations can be classified according to several criteria.The first is pulse values, which can be symmetric or asymmetric.The former means  = 0 V and the later means  = − , where  and  are, respectively, the low and high levels of the output voltage.The symmetric case is slightly more complex to generate from the circuit point of view, and its frequency spectrum has a much lower DC component and larger fundamental and harmonic components.However, other than that, it has little influence on the frequency spectrum of the modulated signal.
A second criterion is related to the fact that the input is a continuous signal but the output signal is a train of pulses, which means that the input signal has been somehow sampled at certain instants.The way sampling is performed also has an impact on the frequency spectrum.There are two options, the so-called uniform sampling, when it is synchronous with the system clock, or the natural sampling, which happens when simple circuits are used to modulate the pulses, i.e., when sampling is achieved by a simple comparator circuit and is not synchronous with the system clock.The basic block diagram of a PW-modulator is shown in Figure 1 [8].Of course, the average sampling frequency over a long period of time is the frequency of the system clock.The third criterion is related to how the sample modulates the output pulses.The samples can determine the positions of either the leading edges, the trailing edges, or both.In the double-edge case, the position of both edges can be symmetrically determined by a single sample or each of them can be determined by two consecutive samples.
Song and Sarwate determined the frequency spectra of different possible PW-modulations [9].A brief summary of their work is presented here, for the sake of completeness.Let us assume the following conditions: (i) Symmetric pulse amplitudes are −1 and 1 V. (ii) The input signal () is frequency-limited, the module of its maximum amplitude is 1 V, and it has no DC component.(iii) The modulation index is 100% and the idle duty cycle is 50%.(iv) The pulse repetition frequency  (better than sampling frequency in natural sampling) is at least  times the maximum frequency of the input signal.Under these conditions, the Fourier expansions of the natural sampling of the PW-modulated signals are [9]: The third criterion is related to how the sample modulates the output pulses.The samples can determine the positions of either the leading edges, the trailing edges, or both.In the double-edge case, the position of both edges can be symmetrically determined by a single sample or each of them can be determined by two consecutive samples.
Song and Sarwate determined the frequency spectra of different possible PW-modulations [9].A brief summary of their work is presented here, for the sake of completeness.Let us assume the following conditions: (i) Symmetric pulse amplitudes are −1 and 1 V. (ii) The input signal x(t) is frequency-limited, the module of its maximum amplitude is 1 V, and it has no DC component.(iii) The modulation index is 100% and the idle duty cycle is 50%.(iv) The pulse repetition frequency f c (better than sampling frequency in natural sampling) is at least π times the maximum frequency of the input signal.Under these conditions, the Fourier expansions of the natural sampling of the PW-modulated signals are [9]: where the subscripts TE, LE, and DE stand, respectively, for the trailing-edge, leading-edge, and double-edge (asymmetric version).If the trigonometric identities, are used, every term in the summations of ( 1)-( 3) becomes TE, k odd : TE, k even : LE, k odd : LE, k even : DE, k odd : DE, k even : When the six terms in ( 6)-( 11) are observed, it is clear that all three PWM versions will include the frequency spectrum of x(t) in their base band, and, as a consequence, all of them can be used in class-D amplifiers.However, we want to now bring attention to the harmonic contents.Double-edge-modulated signals have harmonic components that are amplitude-modulated by x(t), while single-edge modulations have harmonic components modulated both in amplitude and phase.This remark leads to the idea of using a harmonic component to generate a simple modulation of x(t).

Preferred Modulation
Angular modulation schemes such as FSK and PSK are more robust than linear techniques such as amplitude shift keying (ASK) or on-off keying (OOK) [10] while maintaining simplicity.Quadrature amplitude modulation (QAM) modulation has an increased spectral efficiency, but transceivers are more complicated and more power needs to be transmitted to achieve a similar bit-error rate (BER) [11].Among its resources, the software-defined radio (SDR) includes direct digital synthesis (DDS), which provides sinusoidal signals with arbitrary frequency or phase [12][13][14].This makes PSK a good choice for wireless links where power is a limited resource.
A switching-circuit phase modulator is shown in Figure 2 [10].Actually, the signal at the output of the comparator block of Figure 2 is the rising edge PWM of v in , with a carrier frequency of 2 f c .The Flip-Flop circuit divides the number of pulses between the two.

Integrated System
The block diagram of the class-D amplifier is shown in Figure 3.The first block in the diagram is a PW-modulator.The switching block consists of two metal-oxide semiconductor field-effect transistor (MOSFET) and the corresponding gate drivers.If the three diagrams in Figures 1-3 are compared, we realize that if the low-pass filter is replaced by a band-pass filter, the high-power output signal will be the carrier modulated in phase by  .To improve power efficiency of the wireless communication system, a question arises: As the class-D amplifier already contains a modulator, is it possible to directly drive the PW-modulator with a signal that, when band-pass filtered, becomes the PSK modulation of the digital input?The idea is shown schematically in Figure 4 [15].Obviously, the coder blocks in the upper and lower parts of Figure 4 will have to be different.The coder and the PW-modulator blocks of the lower part of Figure 4 have already been developed [16].They can be implemented either with a microcontroller or a digital signal processor (DSP) unit with the architecture of Figure 5.The frequency of the clock input is N times larger than the sampling frequency.Additionally in [17], it has been used to directly feed the switching circuit of the class-D power amplifier in audio applications.The question now is how to obtain the FSKmodulated signal.At this point, we realize that by using a rectangular carrier, we can easily obtain a PSK output instead of an FSK.

Integrated System
The block diagram of the class-D amplifier is shown in Figure 3.The first block in the diagram is a PW-modulator.The switching block consists of two metal-oxide semiconductor field-effect transistor (MOSFET) and the corresponding gate drivers.If the three diagrams in Figures 1-3 are compared, we realize that if the low-pass filter is replaced by a band-pass filter, the high-power output signal will be the carrier modulated in phase by v in .To improve power efficiency of the wireless communication system, a question arises: As the class-D amplifier already contains a modulator, is it possible to directly drive the PW-modulator with a signal that, when band-pass filtered, becomes the PSK modulation of the digital input?The idea is shown schematically in Figure 4 [15].Obviously, the coder blocks in the upper and lower parts of Figure 4 will have to be different.

Integrated System
The block diagram of the class-D amplifier is shown in Figure 3.The first block in the diagram is a PW-modulator.The switching block consists of two metal-oxide semiconductor field-effect transistor (MOSFET) and the corresponding gate drivers.If the three diagrams in Figures 1-3 are compared, we realize that if the low-pass filter is replaced by a band-pass filter, the high-power output signal will be the carrier modulated in phase by  .To improve power efficiency of the wireless communication system, a question arises: As the class-D amplifier already contains a modulator, is it possible to directly drive the PW-modulator with a signal that, when band-pass filtered, becomes the PSK modulation of the digital input?The idea is shown schematically in Figure 4 [15].Obviously, the coder blocks in the upper and lower parts of Figure 4 will have to be different.The coder and the PW-modulator blocks of the lower part of Figure 4 have already been developed [16].They can be implemented either with a microcontroller or a digital signal processor (DSP) unit with the architecture of Figure 5.The frequency of the clock input is N times larger than the sampling frequency.Additionally in [17], it has been used to directly feed the switching circuit of the class-D power amplifier in audio applications.The question now is how to obtain the FSKmodulated signal.At this point, we realize that by using a rectangular carrier, we can easily obtain a PSK output instead of an FSK.

Integrated System
The block diagram of the class-D amplifier is shown in Figure 3.The first block in the diagram is a PW-modulator.The switching block consists of two metal-oxide semiconductor field-effect transistor (MOSFET) and the corresponding gate drivers.If the three diagrams in Figures 1-3 are compared, we realize that if the low-pass filter is replaced by a band-pass filter, the high-power output signal will be the carrier modulated in phase by  .To improve power efficiency of the wireless communication system, a question arises: As the class-D amplifier already contains a modulator, is it possible to directly drive the PW-modulator with a signal that, when band-pass filtered, becomes the PSK modulation of the digital input?The idea is shown schematically in Figure 4 [15].Obviously, the coder blocks in the upper and lower parts of Figure 4 will have to be different.The coder and the PW-modulator blocks of the lower part of Figure 4 have already been developed [16].They can be implemented either with a microcontroller or a digital signal processor (DSP) unit with the architecture of Figure 5.The frequency of the clock input is N times larger than the sampling frequency.Additionally in [17], it has been used to directly feed the switching circuit of the class-D power amplifier in audio applications.The question now is how to obtain the FSKmodulated signal.At this point, we realize that by using a rectangular carrier, we can easily obtain a PSK output instead of an FSK.The coder and the PW-modulator blocks of the lower part of Figure 4 have already been developed [16].They can be implemented either with a microcontroller or a digital signal processor (DSP) unit with the architecture of Figure 5.The frequency of the clock input is N times larger than the sampling frequency.Additionally in [17], it has been used to directly feed the switching circuit of the class-D power amplifier in audio applications.The question now is how to obtain the FSK-modulated signal.At this point, we realize that by using a rectangular carrier, we can easily obtain a PSK output instead of an FSK.The proposed integrated PSK modulator is sketched in Figure 6.The input data bits are converted to a bipolar voltage signal that eventually multiplies a square bipolar carrier, changing its phase according to the input bit.The square signal then drives the power bridge of the class-D amplifier, whose output goes through a band-pass filter centered at the frequency of the bipolar carrier, to obtain a PSK-modulated signal.

Simulation
The PSK modulator using the PWM and a band-pass filter, as shown in the lower part of Figure 4, has been simulated with the help of Matlab.The coder simply converts bits into a symmetrical normalized voltage signal (±1 V).The output band-pass filter is tuned to the carrier frequency of the PW-modulator.Figure 7 shows the input signal, the carrier, and the modulated PSK signal at the filter output.Figure 8 shows the power spectrum at the input of the band-pass filter.For the simulations, the following numbers have been used: (±1.5 V) sawtooth carrier signal,  = 19.8kHz; bit duration time,  = 0.5 ms.The length of the simulation was 1000 bits, randomly generated.Only five bits are shown below, for the sake of clarity, but the whole simulation provided correct results.The proposed integrated PSK modulator is sketched in Figure 6.The input data bits are converted to a bipolar voltage signal that eventually multiplies a square bipolar carrier, changing its phase according to the input bit.The square signal then drives the power bridge of the class-D amplifier, whose output goes through a band-pass filter centered at the frequency of the bipolar carrier, to obtain a PSK-modulated signal.The proposed integrated PSK modulator is sketched in Figure 6.The input data bits are converted to a bipolar voltage signal that eventually multiplies a square bipolar carrier, changing its phase according to the input bit.The square signal then drives the power bridge of the class-D amplifier, whose output goes through a band-pass filter centered at the frequency of the bipolar carrier, to obtain a PSK-modulated signal.

Simulation
The PSK modulator using the PWM and a band-pass filter, as shown in the lower part of Figure 4, has been simulated with the help of Matlab.The coder simply converts bits into a symmetrical normalized voltage signal (±1 V).The output band-pass filter is tuned to the carrier frequency of the PW-modulator.Figure 7 shows the input signal, the carrier, and the modulated PSK signal at the filter output.Figure 8 shows the power spectrum at the input of the band-pass filter.For the simulations, the following numbers have been used: (±1.5 V) sawtooth carrier signal,  = 19.8kHz; bit duration time,  = 0.5 ms.The length of the simulation was 1000 bits, randomly generated.Only five bits are shown below, for the sake of clarity, but the whole simulation provided correct results.

Simulation
The PSK modulator using the PWM and a band-pass filter, as shown in the lower part of Figure 4, has been simulated with the help of Matlab.The coder simply converts bits into a symmetrical normalized voltage signal (±1 V).The output band-pass filter is tuned to the carrier frequency of the PW-modulator.Figure 7 shows the input signal, the carrier, and the modulated PSK signal at the filter output.Figure 8 shows the power spectrum at the input of the band-pass filter.For the simulations, the following numbers have been used: (±1.5 V) sawtooth carrier signal, f c = 19.8kHz; bit duration time, T s = 0.5 ms.The length of the simulation was 1000 bits, randomly generated.Only five bits are shown below, for the sake of clarity, but the whole simulation provided correct results.The proposed integrated PSK modulator is sketched in Figure 6.The input data bits are converted to a bipolar voltage signal that eventually multiplies a square bipolar carrier, changing its phase according to the input bit.The square signal then drives the power bridge of the class-D amplifier, whose output goes through a band-pass filter centered at the frequency of the bipolar carrier, to obtain a PSK-modulated signal.

Simulation
The PSK modulator using the PWM and a band-pass filter, as shown in the lower part of Figure 4, has been simulated with the help of Matlab.The coder simply converts bits into a symmetrical normalized voltage signal (±1 V).The output band-pass filter is tuned to the carrier frequency of the PW-modulator.Figure 7 shows the input signal, the carrier, and the modulated PSK signal at the filter output.Figure 8 shows the power spectrum at the input of the band-pass filter.For the simulations, the following numbers have been used: (±1.5 V) sawtooth carrier signal,  = 19.8kHz; bit duration time,  = 0.5 ms.The length of the simulation was 1000 bits, randomly generated.Only five bits are shown below, for the sake of clarity, but the whole simulation provided correct results.Figure 8 shows the normalized spectrum of the modulated signal at the output of the band-pass filter of the lower part of Figure 4.A MATLAB built-in PSK demodulator ("pmdemod") has been used to verify that the modulation process was correct.Figure 9 shows the same five bits shown in Figures 7 and 8 after using "pmdemod."To be doubly sure of the validity of the concept, the circuit in the lower part of Figure 4 has been designed and simulated also with the help of SIMULINK, as shown in Figure 10.A binary input signal with the bit duration time  = 0.5 ms is applied to the input of the unipolar-to-bipolar block that converts it into a symmetrical normalized voltage signal (±1 V).This signal is compared to the sawtooth carrier frequency  = 19.8kHz to obtain a PW-modulated signal.The signal is then converted into bipolar and a gain of 30 is provided to represent the amplification through the power stage as per the functionality of the class-D amplifier.The band-pass filter tuned to the carrier frequency of the PW-modulator output blocks undesired frequency components and provides a PSKmodulated output.A scope and spectrum analyzer are used to measure the output in time and frequency domains.Figure 8 shows the normalized spectrum of the modulated signal at the output of the band-pass filter of the lower part of Figure 4.A MATLAB built-in PSK demodulator ("pmdemod") has been used to verify that the modulation process was correct.Figure 9 shows the same five bits shown in Figures 7  and 8 after using "pmdemod".
Electronics 2020, 9, x FOR PEER REVIEW 7 of 12 Figure 8 shows the normalized spectrum of the modulated signal at the output of the band-pass filter of the lower part of Figure 4.A MATLAB built-in PSK demodulator ("pmdemod") has been used to verify that the modulation process was correct.Figure 9 shows the same five bits shown in Figures 7 and 8 after using "pmdemod."To be doubly sure of the validity of the concept, the circuit in the lower part of Figure 4 has been designed and simulated also with the help of SIMULINK, as shown in Figure 10.A binary input signal with the bit duration time  = 0.5 ms is applied to the input of the unipolar-to-bipolar block that converts it into a symmetrical normalized voltage signal (±1 V).This signal is compared to the sawtooth carrier frequency  = 19.8kHz to obtain a PW-modulated signal.The signal is then converted into bipolar and a gain of 30 is provided to represent the amplification through the power stage as per the functionality of the class-D amplifier.The band-pass filter tuned to the carrier frequency of the PW-modulator output blocks undesired frequency components and provides a PSKmodulated output.A scope and spectrum analyzer are used to measure the output in time and frequency domains.To be doubly sure of the validity of the concept, the circuit in the lower part of Figure 4 has been designed and simulated also with the help of SIMULINK, as shown in Figure 10.A binary input signal with the bit duration time T s = 0.5 ms is applied to the input of the unipolar-to-bipolar block that converts it into a symmetrical normalized voltage signal (±1 V).This signal is compared to the sawtooth carrier frequency f c = 19.8kHz to obtain a PW-modulated signal.The signal is then converted into bipolar and a gain of 30 is provided to represent the amplification through the power stage as per the functionality of the class-D amplifier.The band-pass filter tuned to the carrier frequency of the PW-modulator output blocks undesired frequency components and provides a PSK-modulated output.A scope and spectrum analyzer are used to measure the output in time and frequency domains.Figure 12 shows the overall power spectrum of the proposed model.As is evident, the fundamental frequency component of the system will have maximum amplitude; it can be observed that at 19.8 kHz, the third and fifth harmonics are visible at around 59 and 99 kHz, respectively.A band-pass filter tuned at the carrier frequency has been used to eliminate unwanted frequency components and to obtain a binary phase-shift keying (BPSK)-modulated output.Figure 12 shows the overall power spectrum of the proposed model.As is evident, the fundamental frequency component of the system will have maximum amplitude; it can be observed that at 19.8 kHz, the third and fifth harmonics are visible at around 59 and 99 kHz, respectively.A band-pass filter tuned at the carrier frequency has been used to eliminate unwanted frequency components and to obtain a binary phase-shift keying (BPSK)-modulated output.Figure 12 shows the overall power spectrum of the proposed model.As is evident, the fundamental frequency component of the system will have maximum amplitude; it can be observed that at 19.8 kHz, the third and fifth harmonics are visible at around 59 and 99 kHz, respectively.A band-pass filter tuned at the carrier frequency has been used to eliminate unwanted frequency components and to obtain a binary phase-shift keying (BPSK)-modulated output.

Prototype
To fully demonstrate the concept, a circuit has been designed in interactive software Multisim [18] that not only provides powerful simulation and analysis, but is also used for the printed circuit board (PCB) design.A schematic of the proposed circuit prototype is shown in Figure 13.The circuit can be divided into five major blocks for better comprehension.On the left side, the 555 timer IC generates a sawtooth waveform of  = 19.8kHz to be used as a carrier, and the OPAMP LM358 shown at the bottom adjusts the gain and offset of the waveform.The second block is the comparator where a binary input signal is applied to the + input of the IC LM393, while the carrier is connected to the − input.The output of the comparator is a pulse width-modulated (PWM) signal.The third block is the driver circuitry and works as a buffer and designed using IC LM358 to prevent the loading effect and to drive the fourth block, i.e., IRLZ44N Power MOSFET transistors.The amplified signal is fed into the fifth block, i.e., the second-order band-pass passive LC filter circuit removes unwanted signal components and provides an amplified PSK-modulated signal at the output.

Results
Figure 14 shows the waveform acquired from testing the prototype circuit, which is similar to the waveform as obtained in Figure 11 from the simulation.The horizontal axis represents the time

Prototype
To fully demonstrate the concept, a circuit has been designed in interactive software Multisim [18] that not only provides powerful simulation and analysis, but is also used for the printed circuit board (PCB) design.A schematic of the proposed circuit prototype is shown in Figure 13.The circuit can be divided into five major blocks for better comprehension.On the left side, the 555 timer IC generates a sawtooth waveform of f c = 19.8kHz to be used as a carrier, and the OPAMP LM358 shown at the bottom adjusts the gain and offset of the waveform.The second block is the comparator where a binary input signal is applied to the +ve input of the IC LM393, while the carrier is connected to the −ve input.The output of the comparator is a pulse width-modulated (PWM) signal.The third block is the driver circuitry and works as a buffer and designed using IC LM358 to prevent the loading effect and to drive the fourth block, i.e., IRLZ44N Power MOSFET transistors.The amplified signal is fed into the fifth block, i.e., the second-order band-pass passive LC filter circuit removes unwanted signal components and provides an amplified PSK-modulated signal at the output.

Prototype
To fully demonstrate the concept, a circuit has been designed in interactive software Multisim [18] that not only provides powerful simulation and analysis, but is also used for the printed circuit board (PCB) design.A schematic of the proposed circuit prototype is shown in Figure 13.The circuit can be divided into five major blocks for better comprehension.On the left side, the 555 timer IC generates a sawtooth waveform of  = 19.8kHz to be used as a carrier, and the OPAMP LM358 shown at the bottom adjusts the gain and offset of the waveform.The second block is the comparator where a binary input signal is applied to the + input of the IC LM393, while the carrier is connected to the − input.The output of the comparator is a pulse width-modulated (PWM) signal.The third block is the driver circuitry and works as a buffer and designed using IC LM358 to prevent the loading effect and to drive the fourth block, i.e., IRLZ44N Power MOSFET transistors.The amplified signal is fed into the fifth block, i.e., the second-order band-pass passive LC filter circuit removes unwanted signal components and provides an amplified PSK-modulated signal at the output.

Results
Figure 14 shows the waveform acquired from testing the prototype circuit, which is similar to the waveform as obtained in Figure 11 from the simulation.The horizontal axis represents the time

Results
Figure 14 shows the waveform acquired from testing the prototype circuit, which is similar to the waveform as obtained in Figure 11 from the simulation.The horizontal axis represents the time in seconds, while the amplitude is shown on the vertical axis in volts.The sawtooth waveform shown in green represents the carrier, i.e., the −ve input of the comparator IC LM393, while the binary input signal is shown in red applied to the +ve input of the comparator.The PWM output of the comparator is shown in blue and passes to the buffers to drive the power MOSFET transistors.Finally, the filter output, i.e., amplified PSK-modulated signal, is shown in purple.
Electronics 2020, 9, x FOR PEER REVIEW 10 of 12 in seconds, while the amplitude is shown on the vertical axis in volts.The sawtooth waveform shown in green represents the carrier, i.e., the − input of the comparator IC LM393, while the binary input signal is shown in red applied to the + input of the comparator.The PWM output of the comparator is shown in blue and passes to the buffers to drive the power MOSFET transistors.Finally, the filter output, i.e., amplified PSK-modulated signal, is shown in purple.

Discussion
A qualitative comparison with the state-of-the-art is presented in Table 1.The input signal type in most of the is analog, while our proposed amplifier design accepts a digital signal of 1 V.We have tested our design on a 2 kHz input frequency range compared to 1 kHz in many cases and 5 kHz in [6].The switching frequency used in the state-of-the-art is in the range of 200-2000 kHz, while in our case, it is much lower, i.e., 19.8 kHz, which is a plus point.Mostly, PWM or, in some cases, PDM is used inside the class-D amplifier followed by an LPF.We used BPF that not only filters but provides PSK modulation without using any modulator block.This unique feature is the novelty of our design that reduces the cost as we did not use any modulator, as well as increases the power efficiency of the overall system.The proposed design can deliver up to 6 W under a controlled environment at room temperature.Output type Amplified Amplified Amplified Amplified Amplified Amplified PSK

Discussion
A qualitative comparison with the state-of-the-art is presented in Table 1.The input signal type in most of the designs is analog, while our proposed amplifier design accepts a digital signal of 1 V.We have tested our design on a 2 kHz input frequency range compared to 1 kHz in many cases and 5 kHz in [6].The switching frequency used in the state-of-the-art is in the range of 200-2000 kHz, while in our case, it is much lower, i.e., 19.8 kHz, which is a plus point.Mostly, PWM or, in some cases, PDM is used inside the class-D amplifier followed by an LPF.We used BPF that not only filters but provides PSK modulation without using any modulator block.This unique feature is the novelty of our design that reduces the cost as we did not use any modulator, as well as increases the power efficiency of the overall system.The proposed design can deliver up to 6 W under a controlled environment at room temperature.

Conclusions
In this paper, the integration of the modulator of a transmitter and PW-modulator of a class-D amplifier is presented to improve the energy efficiency of the system.The concept stems from the idea of the class-D amplifier where a power switching block is driven by a digital carrier modulated by the signal of interest.A band-pass filter is then used to obtain an amplified PSK output.The concept can be of vital importance in the ultrasound band used in applications related to underwater acoustic

Figure 3 .
Figure 3. Block diagram of a half-bridge class-D power amplifier.

Figure 4 .
Figure 4. Block diagram of a PSK modulator that drives a class-D power amplifier [15].

Figure 3 .
Figure 3. Block diagram of a half-bridge class-D power amplifier.

Figure 4 .
Figure 4. Block diagram of a PSK modulator that drives a class-D power amplifier [15].

Figure 3 . 12 Figure 2 .
Figure 3. Block diagram of a half-bridge class-D power amplifier.

Figure 3 .
Figure 3. Block diagram of a half-bridge class-D power amplifier.

Figure 4 .
Figure 4. Block diagram of a PSK modulator that drives a class-D power amplifier [15].

Figure 4 .
Figure 4. Block diagram of a PSK modulator that drives a class-D power amplifier [15].

Figure 7 .
Figure 7. Input signal, carrier, and modulated PSK signal at the filter output of Figure 4.

Figure 7 .
Figure 7. Input signal, carrier, and modulated PSK signal at the filter output of Figure 4.

Figure 7 .
Figure 7. Input signal, carrier, and modulated PSK signal at the filter output of Figure 4.Figure 7. Input signal, carrier, and modulated PSK signal at the filter output of Figure 4.

Figure 7 .
Figure 7. Input signal, carrier, and modulated PSK signal at the filter output of Figure 4.Figure 7. Input signal, carrier, and modulated PSK signal at the filter output of Figure 4.

Figure 8 .
Figure 8. Normalized spectrum of the modulated signal at the filter output of Figure 4.

Figure 9 .
Figure 9. Demodulated signal, to verify the whole process.

Figure 8 .
Figure 8. Normalized spectrum of the modulated signal at the filter output of Figure 4.

Figure 8 .
Figure 8. Normalized spectrum of the modulated signal at the filter output of Figure 4.

Figure 9 .
Figure 9. Demodulated signal, to verify the whole process.

Figure 9 .
Figure 9. Demodulated signal, to verify the whole process.

Figure 11
Figure11shows the results obtained from the Simulink model in the time domain using the scope.In this figure, the binary input signal has been shown with a red color in the top part of the figure.In the same figure, the sawtooth waveform that acts as a carrier signal has been shown with a green color.The middle part of the figure is the PW-modulated signal that has been converted to a bipolar signal and is shown in blue at channel 2 of the scope.Finally, the amplified and filtered PSKmodulated output received from the band-pass filter has been shown with a purple color in the bottom part of the figure.

Figure 11 .
Figure 11.Simulation results of proposed model.

Figure 11
Figure11shows the results obtained from the Simulink model in the time domain using the scope.In this figure, the binary input signal has been shown with a red color in the top part of the figure.In the same figure, the sawtooth waveform that acts as a carrier signal has been shown with a green color.The middle part of the figure is the PW-modulated signal that has been converted to a bipolar signal and is shown in blue at channel 2 of the scope.Finally, the amplified and filtered PSK-modulated output received from the band-pass filter has been shown with a purple color in the bottom part of the figure.

Figure 11
Figure11shows the results obtained from the Simulink model in the time domain using the scope.In this figure, the binary input signal has been shown with a red color in the top part of the figure.In the same figure, the sawtooth waveform that acts as a carrier signal has been shown with a green color.The middle part of the figure is the PW-modulated signal that has been converted to a bipolar signal and is shown in blue at channel 2 of the scope.Finally, the amplified and filtered PSKmodulated output received from the band-pass filter has been shown with a purple color in the bottom part of the figure.

Figure 11 .
Figure 11.Simulation results of proposed model.

Figure 11 .
Figure 11.Simulation results of proposed model.

Figure 12 .
Figure 12.Power spectrum of proposed model.

Figure 13 .
Figure 13. Circuit diagram of proposed design.

Figure 12 .
Figure 12.Power spectrum of proposed model.

Figure 13 .
Figure 13. Circuit diagram of proposed design.

Figure 13 .
Figure 13. Circuit diagram of proposed design.

Figure 14 .
Figure 14.Waveform of the proposed circuit.

Figure 14 .
Figure 14.Waveform of the proposed circuit.

Table 1 .
Comparison with state-of-the-art.

Table 1 .
Comparison with state-of-the-art.