Characterization of Self-Heating Process in GaN-Based HEMTs

Thermal characterization of modern microwave power transistors such as high electron-mobility transistors based on gallium nitride (GaN-based HEMTs) is a critical challenge for the development of high-performance new generation wireless communication systems (LTE-A, 5G) and advanced radars (active electronically scanned array (AESA)). This is especially true for systems operating with variable-envelope signals where accurate determination of self-heating effects resulting from strong- and fast-changing power dissipated inside transistor is crucial. In this work, we have developed an advanced measurement system based on DeltaVGS method with implemented software enabling accurate determination of device channel temperature and thermal resistance. The methodology accounts for MIL-STD-750-3 standard but takes into account appropriate specific bias and timing conditions. Three types of GaN-based HEMTs were taken into consideration, namely commercially available GaN-on-SiC (CGH27015F and TGF2023-2-01) and GaN-on-Si (NPT2022) devices, as well as model GaN-on-GaN HEMT (T8). Their characteristics of thermal impedance, thermal time constants and thermal equivalent circuits were presented. Knowledge of thermal equivalent circuits and electro–thermal models can lead to improved design of GaN HEMT high-power amplifiers with account of instantaneous temperature variations for systems using variable-envelope signals. It can also expand their range of application.


Introduction
It is now commonly accepted that high electron-mobility transistors based on gallium nitride (GaN HEMT) are the best choice for high-frequency and high-power devices, such as high-power amplifiers (HPAs) used in new generation radars, including active electronically scanned array (AESA), and modern wireless communication systems, i.e., LTE-A and 5G radios [1][2][3][4]. Due to the large complexity of signals applied in modern radars and new radios, power amplifiers have to meet stringent requirements concerning not only their linearity, output power level and efficiency but also appropriate heat management [5]. This is because both kinds of mentioned systems are operated by variable-envelope signals.
In AESA radar pulses, the signals are not only frequency-modulated but can be also modulated both in phase and amplitude [6,7]. The same concerns high-speed wireless networks which use quadrature amplitude modulation (QAM) with a large peak-to-average power ratio (PAPR). For instance, the PARP

Electrical Characterization of Thermal Properties
In general terms we follow the well-known DeltaVGS measurement technique at the constant current of forward-biased gate-to-source diode in MESFET or HEMT (MIL-STD-750D-3 standard, method 3104) [15,16]. However, our approach is different from the previous ones by specific bias and timing conditions of the transistor during the measurements.
The knowledge of thermal impedance Zth(t) allows calculating the channel temperature Tj(t) for any shape of dissipated power Pd(t) as follows [17]: where: Tj(t)-channel temperature response; T0-ambient temperature (heatsink); Z ' th(t)-time derivative of Zth(t); Pd (t)-dissipated power.
The thermal impedance Zth(t) of different elements is often modeled, through the electro-thermal analogy, by lumped electrical equivalent circuit which contains a number of thermal resistances Rth and thermal capacitances Cth connected in an appropriate way. Typically, in simplified terms, the thermal equivalent circuit consists of several parallel Rth-Cth circuits connected in series [18]. Each of the low-pass circuits Rthi-Cthi corresponds to a thermal time constant τi in an exponential approximation of thermal impedance Zth(t) characteristic. Such a lumped electrical model can be used to calculate the channel temperature using one of popular circuit simulators like ADS or SPICE. That approach is very convenient, because the temperature of active area of transistors can be simulated using the tool applied anyway for analysis of electrical parameters.
As previously mentioned the developed system of thermal impedance Zth(t) measurement was inspired by the method 3104 from MIL-STD-750D-3 standard which uses the effect of the voltage drop ΔVGS(t) at a forward-biased junction as a sensor of the temperature. Furthermore, the temperature values of the gate-source diode and the transistor channel are identical. The basic formula for that measurement technique was derived from the Schottky's diode equation and is expressed as follows: where: Electronics 2020, 9, x FOR PEER REVIEW 3 of 15

Electrical Characterization of Thermal Properties
In general terms we follow the well-known DeltaVGS measurement technique at the constant current of forward-biased gate-to-source diode in MESFET or HEMT (MIL-STD-750D-3 standard, method 3104) [15,16]. However, our approach is different from the previous ones by specific bias and timing conditions of the transistor during the measurements.
The knowledge of thermal impedance Zth(t) allows calculating the channel temperature Tj(t) for any shape of dissipated power Pd(t) as follows [17]: where: Tj(t)-channel temperature response; T0-ambient temperature (heatsink); Z ' th(t)-time derivative of Zth(t); Pd (t)-dissipated power.
The thermal impedance Zth(t) of different elements is often modeled, through the electro-thermal analogy, by lumped electrical equivalent circuit which contains a number of thermal resistances Rth and thermal capacitances Cth connected in an appropriate way. Typically, in simplified terms, the thermal equivalent circuit consists of several parallel Rth-Cth circuits connected in series [18]. Each of the low-pass circuits Rthi-Cthi corresponds to a thermal time constant τi in an exponential approximation of thermal impedance Zth(t) characteristic. Such a lumped electrical model can be used to calculate the channel temperature using one of popular circuit simulators like ADS or SPICE. That approach is very convenient, because the temperature of active area of transistors can be simulated using the tool applied anyway for analysis of electrical parameters.
As previously mentioned the developed system of thermal impedance Zth(t) measurement was inspired by the method 3104 from MIL-STD-750D-3 standard which uses the effect of the voltage drop ΔVGS(t) at a forward-biased junction as a sensor of the temperature. Furthermore, the temperature values of the gate-source diode and the transistor channel are identical. The basic formula for that measurement technique was derived from the Schottky's diode equation and is expressed as follows: where:

Electrical Characterization of Thermal Properties
In general terms we follow the well-known DeltaVGS measurement technique at the constant current of forward-biased gate-to-source diode in MESFET or HEMT (MIL-STD-750D-3 standard, method 3104) [15,16]. However, our approach is different from the previous ones by specific bias and timing conditions of the transistor during the measurements.
The knowledge of thermal impedance Zth(t) allows calculating the channel temperature Tj(t) for any shape of dissipated power Pd(t) as follows [17]: where: Tj(t)-channel temperature response; T0-ambient temperature (heatsink); Z ' th(t)-time derivative of Zth(t); Pd (t)-dissipated power.
The thermal impedance Zth(t) of different elements is often modeled, through the electro-thermal analogy, by lumped electrical equivalent circuit which contains a number of thermal resistances Rth and thermal capacitances Cth connected in an appropriate way. Typically, in simplified terms, the thermal equivalent circuit consists of several parallel Rth-Cth circuits connected in series [18]. Each of the low-pass circuits Rthi-Cthi corresponds to a thermal time constant τi in an exponential approximation of thermal impedance Zth(t) characteristic. Such a lumped electrical model can be used to calculate the channel temperature using one of popular circuit simulators like ADS or SPICE. That approach is very convenient, because the temperature of active area of transistors can be simulated using the tool applied anyway for analysis of electrical parameters.
As previously mentioned the developed system of thermal impedance Zth(t) measurement was inspired by the method 3104 from MIL-STD-750D-3 standard which uses the effect of the voltage drop ΔVGS(t) at a forward-biased junction as a sensor of the temperature. Furthermore, the temperature values of the gate-source diode and the transistor channel are identical. The basic formula for that measurement technique was derived from the Schottky's diode equation and is expressed as follows: where: Electronics 2020, 9, x FOR PEER REVIEW 3 of 15

Electrical Characterization of Thermal Properties
In general terms we follow the well-known DeltaVGS measurement technique at the constant current of forward-biased gate-to-source diode in MESFET or HEMT (MIL-STD-750D-3 standard, method 3104) [15,16]. However, our approach is different from the previous ones by specific bias and timing conditions of the transistor during the measurements.
The knowledge of thermal impedance Zth(t) allows calculating the channel temperature Tj(t) for any shape of dissipated power Pd(t) as follows [17]: where: Tj(t)-channel temperature response; T0-ambient temperature (heatsink); Z ' th(t)-time derivative of Zth(t); Pd (t)-dissipated power.
The thermal impedance Zth(t) of different elements is often modeled, through the electro-thermal analogy, by lumped electrical equivalent circuit which contains a number of thermal resistances Rth and thermal capacitances Cth connected in an appropriate way. Typically, in simplified terms, the thermal equivalent circuit consists of several parallel Rth-Cth circuits connected in series [18]. Each of the low-pass circuits Rthi-Cthi corresponds to a thermal time constant τi in an exponential approximation of thermal impedance Zth(t) characteristic. Such a lumped electrical model can be used to calculate the channel temperature using one of popular circuit simulators like ADS or SPICE. That approach is very convenient, because the temperature of active area of transistors can be simulated using the tool applied anyway for analysis of electrical parameters.
As previously mentioned the developed system of thermal impedance Zth(t) measurement was inspired by the method 3104 from MIL-STD-750D-3 standard which uses the effect of the voltage drop ΔVGS(t) at a forward-biased junction as a sensor of the temperature. Furthermore, the temperature values of the gate-source diode and the transistor channel are identical. The basic formula for that measurement technique was derived from the Schottky's diode equation and is expressed as follows: where:

Electrical Characterization of Thermal Properties
In general terms we follow the well-known DeltaV GS measurement technique at the constant current of forward-biased gate-to-source diode in MESFET or HEMT (MIL-STD-750D-3 standard, method 3104) [15,16]. However, our approach is different from the previous ones by specific bias and timing conditions of the transistor during the measurements.
The knowledge of thermal impedance Z th (t) allows calculating the channel temperature T j (t) for any shape of dissipated power P d (t) as follows [17]: where: T j (t)-channel temperature response; T 0 -ambient temperature (heatsink); Z th (t)-time derivative of Z th (t); P d (t)-dissipated power.
The thermal impedance Z th (t) of different elements is often modeled, through the electro-thermal analogy, by lumped electrical equivalent circuit which contains a number of thermal resistances R th and thermal capacitances C th connected in an appropriate way. Typically, in simplified terms, the thermal equivalent circuit consists of several parallel R th -C th circuits connected in series [18]. Each of the low-pass circuits R thi -C thi corresponds to a thermal time constant τ i in an exponential approximation of thermal impedance Z th (t) characteristic. Such a lumped electrical model can be used to calculate the channel temperature using one of popular circuit simulators like ADS or SPICE. That approach is very convenient, because the temperature of active area of transistors can be simulated using the tool applied anyway for analysis of electrical parameters.
As previously mentioned the developed system of thermal impedance Z th (t) measurement was inspired by the method 3104 from MIL-STD-750D-3 standard which uses the effect of the voltage drop ∆V GS (t) at a forward-biased junction as a sensor of the temperature. Furthermore, the temperature values of the gate-source diode and the transistor channel are identical. The basic formula for that measurement technique was derived from the Schottky's diode equation and is expressed as follows: At the constant gate current I G , the voltage drop ∆V GS across the source-gate junction decreases almost linearly with the rise of temperature and is given by: where: K-constant.
The Z th (t) measurement procedure consists of the following steps: • preparation of a test board with connected transistor marked as DUT in Figure 2b.
Examples of test boards for packaged transistors and chips measurements are presented in Figure 1a,b, respectively. The test board consists of a printed board circuits (PCB) placed on a thick metal base plate (usually made of copper) which should be characterized by high thermal inertia. The transistor bottom is thermally connected to this plate. The temperature at the bottom of the transistor (T 0 ) must be constant during the V GS (t) recording. Otherwise the T 0 temperature changes must be taken into account in the last step of the procedure i.e., thermal impedance Z th (t) calculation. The transistor can be biased in active state in heating phase of the V GS (t) recording procedure. Since the GaN HEMTs are generally potentially unstable the stabilizing circuits are required on the PCB to protect the transistor against damage.

IG-junction forward current;
A-effective Richardson constant; W-the junction surface; q-charge of the electron; k-Boltzmann constant; n-ideality factor; Vb-built-in barrier voltage.
At the constant gate current IG, the voltage drop ΔVGS across the source-gate junction decreases almost linearly with the rise of temperature and is given by: The Zth(t) measurement procedure consists of the following steps: • preparation of a test board with connected transistor marked as DUT in Figure 2b.
Examples of test boards for packaged transistors and chips measurements are presented in Figure 1a,b, respectively. The test board consists of a printed board circuits (PCB) placed on a thick metal base plate (usually made of copper) which should be characterized by high thermal inertia. The transistor bottom is thermally connected to this plate. The temperature at the bottom of the transistor (T0) must be constant during the VGS(t) recording. Otherwise the T0 temperature changes must be taken into account in the last step of the procedure i.e., thermal impedance Zth(t) calculation. The transistor can be biased in active state in heating phase of the VGS(t) recording procedure. Since the GaN HEMTs are generally potentially unstable the stabilizing circuits are required on the PCB to protect the transistor against damage. The simplified block diagram of the proposed Zth(t) measurement system with the timing diagram of VGS(t) recording procedure is shown in Figure 2. In the methods based on the MIL-STD-750D-3 standard the gate-to-source diode is forward-biased all the time and the operating point of the transistor during the heating phase is placed in "on" region of the DC I-V output characteristic i.e., with relatively low VDS DC voltage (VDS ≤ Vknee) and high ID drain current. In that conditions the power dissipated in transistors is significantly lower and hence the Rth value is also smaller than in the case of normal transistor operation in transmitter's amplifier when RF signal is amplified i.e., the   The simplified block diagram of the proposed Z th (t) measurement system with the timing diagram of V GS (t) recording procedure is shown in Figure 2. In the methods based on the MIL-STD-750D-3 standard the gate-to-source diode is forward-biased all the time and the operating point of the transistor Electronics 2020, 9, 1305 5 of 15 during the heating phase is placed in "on" region of the DC I-V output characteristic i.e., with relatively low V DS DC voltage (V DS ≤ V knee ) and high I D drain current. In that conditions the power dissipated in transistors is significantly lower and hence the R th value is also smaller than in the case of normal transistor operation in transmitter's amplifier when RF signal is amplified i.e., the average value of the drain current is higher than at the quiescent operating point (without RF power, as in classes AB, B and C). Therefore, in our thermal measurements, the operating point of the tested transistor is selected so that it corresponds to the expected maximum power from the amplifier, especially when typical V DS bias voltage for power GaN HEMTs is over a 28 V to 50 V voltage range.
average value of the drain current is higher than at the quiescent operating point (without RF power, as in classes AB, B and C). Therefore, in our thermal measurements, the operating point of the tested transistor is selected so that it corresponds to the expected maximum power from the amplifier, especially when typical VDS bias voltage for power GaN HEMTs is over a 28 V to 50 V voltage range.
Information on the influence of VDS voltage on thermal resistance Rth is scarce and ambiguous. From one side strong thermal resistance Rth changes versus VDS voltage for GaAs MESFET transistors (the constant level of power was dissipated in transistors during the tests) was observed [15]. On the other hand weak dependence of Zth(t) or Rth for GaAs (no more than 10%) [19] and GaN (no more 6%) [20,21] transistors for VDS change was demonstrated. As reported in [22][23][24], the Zth(t) changes mainly follow dependence of thermal conductivity of GaN HEMT layers on temperature.
Our test setup ( Figure 2) was designed to be very flexible, and it allows setting wide range VDS bias voltages and ID current during the heating phase. It includes extra K2, K3 switches and controlled VGS0 voltage source. The VGS0 setting range is −6-0 V and VDS from 0 V to +50 V. The control range of current source IG is 0.1-10 mA. The proposed VGS(t) recording procedure (Figure 2c) is also different from the method based on MIL-STD-750D-3 standard.   Information on the influence of V DS voltage on thermal resistance R th is scarce and ambiguous. From one side strong thermal resistance R th changes versus V DS voltage for GaAs MESFET transistors (the constant level of power was dissipated in transistors during the tests) was observed [15]. On the other hand weak dependence of Z th (t) or R th for GaAs (no more than 10%) [19] and GaN (no more Electronics 2020, 9, 1305 6 of 15 6%) [20,21] transistors for V DS change was demonstrated. As reported in [22][23][24], the Z th (t) changes mainly follow dependence of thermal conductivity of GaN HEMT layers on temperature.
Our test setup (Figure 2) was designed to be very flexible, and it allows setting wide range V DS bias voltages and I D current during the heating phase. It includes extra K 2 , K 3 switches and controlled V GS0 voltage source. The V GS0 setting range is −6-0 V and V DS from 0 V to +50 V. The control range of current source I G is 0.1-10 mA. The proposed V GS (t) recording procedure (Figure 2c) is also different from the method based on MIL-STD-750D-3 standard.
At the beginning the keys are set up in the following positions: K 1 , K 3 position "1", K 2 position "0" and the transistor is biased at the chosen operating point and heated by DC power dissipated therein. After the heating pulse the keys K 1 , K 2 and K 3 are switched to the positions 0 and 1, respectively. This is the start of V GS (t) sampling during the cooling phase of the DUT. The forward gate current remains constant and it equal to I G after the heating time while the drain-source voltage source V DS circuit is open i.e., drain current is 0. The switching time of K 1 , K 2 and K 3 keys is less than 10 ns but in practice, the total switching time between heating end and the start of recording phase t D is less than 100 ns. In the commercially available measurement systems that time is close to 5 µs [25]. The t D time depends on input capacitance C gs of transistor and I G value. Therefore, gate current I G value should be as high as possible. The forward gate current is limited by the maximum allowed level specified for the transistor. Furthermore, time delay is also determined by bias and stabilization circuits. In MIL-STD-750D standard the V GS voltage is only measured in two-time moments: before heating and as quick as possible after heating. These two V GS values allow calculating only the thermal resistance R th . This is the main purpose of MIL-STD-750D-3 standard as it is clearly indicated in description. Therefore, this method is aimed at the testing transistors in packages, especially die attachment quality [15].
As shown in Figure 2a, the V GS (t) sampling is performed by means the recording block and digital part of the system. The recording time t REC as well as the sampling frequency f s can be changed. At the beginning of the recoding phase f s achieves 100 MHz and after 1 s drops to 10 Hz. The recording is continued up to the moment when the lack is significant changes of V GS (t). The maximum recording time of V GS (t) is 90 s. This ploy enables significantly reducing the amount of V GS (t) recorded data. The V GS (t) and Z th (t) characteristics are similar to the response of low pass filter. Therefore, there is no need to record of V GS (t) samples with the maximum sampling frequency up to end of measurement procedure.
After V GS (t) recording, the calibration is needed to calculate K factor values. The DUT is placed in a thermal test chamber and the V GS voltages across the forward-biased gate-to-source Schottky junction for a number of different temperatures are stationary measured. The I G value is constant and the same as during in V GS (t) recording. The concept of K factor measurement is presented in Figure 3. and K3 keys is less than 10 ns but in practice, the total switching time between heating end and the start of recording phase tD is less than 100 ns. In the commercially available measurement systems that time is close to 5 µs [25]. The tD time depends on input capacitance Cgs of transistor and IG value. Therefore, gate current IG value should be as high as possible. The forward gate current is limited by the maximum allowed level specified for the transistor. Furthermore, time delay is also determined by bias and stabilization circuits. In MIL-STD-750D standard the VGS voltage is only measured in two-time moments: before heating and as quick as possible after heating. These two VGS values allow calculating only the thermal resistance Rth. This is the main purpose of MIL-STD-750D-3 standard as it is clearly indicated in description. Therefore, this method is aimed at the testing transistors in packages, especially die attachment quality [15].
As shown in Figure 2a, the VGS(t) sampling is performed by means the recording block and digital part of the system. The recording time tREC as well as the sampling frequency fs can be changed. At the beginning of the recoding phase fs achieves 100 MHz and after 1 s drops to 10 Hz. The recording is continued up to the moment when the lack is significant changes of VGS(t). The maximum recording time of VGS(t) is 90 s. This ploy enables significantly reducing the amount of VGS(t) recorded data. The VGS(t) and Zth(t) characteristics are similar to the response of low pass filter. Therefore, there is no need to record of VGS(t) samples with the maximum sampling frequency up to end of measurement procedure.
After VGS(t) recording, the calibration is needed to calculate K factor values. The DUT is placed in a thermal test chamber and the VGS voltages across the forward-biased gate-to-source Schottky junction for a number of different temperatures are stationary measured. The IG value is constant and the same as during in VGS(t) recording. The concept of K factor measurement is presented in Figure 3. The last step of the measurement procedure is channel temperature Tj(t) and thermal impedance calculation Zth(t). The channel temperature Tj(t) of transistor is given by following formula: As shown in Figure 2c the VGS(t) is acquired during the transistor cooling. Under these conditions, as shown in Figure 2c, the thermal impedance Zth(t) can be calculated as follows:  The last step of the measurement procedure is channel temperature T j (t) and thermal impedance calculation Z th (t). The channel temperature T j (t) of transistor is given by following formula: As shown in Figure 2c the V GS (t) is acquired during the transistor cooling. Under these conditions, as shown in Figure 2c, the thermal impedance Z th (t) can be calculated as follows: where: T j (0)-calculated channel temperature at the beginning of the V GS (t) recording; P DC -dissipated power in transistor during heating phase.
The Z th (t) measurement system consists of the hardware (microcontroller and FPGA), firmware and PC software. The FPGA block controls the K 1 -K 3 switches, acquires and stores the V GS (t) data from A/D converter. The communication between hardware and PC is realized by microcontroller (MCU) using USB standard. The V GS (t) data from FPGA is transferred to PC via MCU. The MCU controls the components of the recording block and the V GSO , V DS voltage sources. All parameters of V GS (t) recording procedure (Figure 2b,c) can be set using PC software. The PC software also allows pre-processing of the received data, calculation of Z th (t) impedance and finally visualization of the results. The graphical user interface of the PC software is presented in Figure 4a. The Z th (t) measurement results can be exported to text file in *.csf format. The PC software has been written in Java using the Eclipse environment. The photo of hardware of the Z th (t) measurement system is shown in Figure 4b. The Zth(t) measurement system consists of the hardware (microcontroller and FPGA), firmware and PC software. The FPGA block controls the K1-K3 switches, acquires and stores the VGS(t) data from A/D converter. The communication between hardware and PC is realized by microcontroller (MCU) using USB standard. The VGS(t) data from FPGA is transferred to PC via MCU. The MCU controls the components of the recording block and the VGSO, VDS voltage sources. All parameters of VGS(t) recording procedure (Figure 2b,c) can be set using PC software. The PC software also allows pre-processing of the received data, calculation of Zth(t) impedance and finally visualization of the results. The graphical user interface of the PC software is presented in Figure 4a. The Zth(t) measurement results can be exported to text file in *.csf format. The PC software has been written in Java using the Eclipse environment. The photo of hardware of the Zth(t) measurement system is shown in Figure 4b.

Results
The Zth(t) and Tj(t) of CGH27015 and T8 are presented in Figure 5a-d, respectively. The GaN-on-SiC HEMT CGH27015F was mounted in the test board shown in Figure 1a. During the heating phase the CGH27015F was biased as follows: VDS = 28 V (PD = 14 W) and VDS = 15 V (PD = 7 W) at the same current ID = ~0.5 A.

Results
The Z th (t) and T j (t) of CGH27015 and T8 are presented in Figure 5a Figure 6 were performed under modified conditions i.e., the same power level was dissipated inside dies during heating phase of measurement procedure. In this phase, dissipated power level inside T8 was PD = 0.75 W and voltage VDS = 5 V, 10 V, 15 V, 20 V and 28 V (Figure 6a,b). The Zth(t) and the Tj(t) of TGF2023-2-01 are shown in Figure 6c. In this case the dissipated power level was PD = 2.5 W and the VDS = 5 V, 10 V, 15 V, 20 V and 28 V.    Figure 6 were performed under modified conditions i.e., the same power level was dissipated inside dies during heating phase of measurement procedure. In this phase, dissipated power level inside T8 was P D = 0.75 W and voltage V DS = 5 V, 10 V, 15 V, 20 V and 28 V (Figure 6a,b). The Z th (t) and the T j (t) of TGF2023-2-01 are shown in Figure 6c. In this case the dissipated power level was P D = 2.5 W and the V DS = 5 V, 10 V, 15 V, 20 V and 28 V.
The Z th (t) changes (T8) shown in Figure 5c, when different power levels were dissipated in GaN HEMTs, are bigger in comparison to Z th (t) changes indicated in Figure 6c for the same power dissipated in transistors and different drain-to-source voltages. The impact of Ga-on-Si HEMT NPT2022 voltage V DS on the Z th (t) characteristics, as shown Figure 7a, is slightly larger to similar Z th (t) characteristics of GaN-on-SiC HEMT TGF2023-2-01 ( Figure 6a). Generally, obtained results confirm the lack of significant dependence of impedance Z th (t) on GaN HEMT bias voltage. The Zth(t) changes (T8) shown in Figure 5c, when different power levels were dissipated in GaN HEMTs, are bigger in comparison to Zth(t) changes indicated in Figure 6c for the same power dissipated in transistors and different drain-to-source voltages. The impact of Ga-on-Si HEMT NPT2022 voltage VDS on the Zth(t) characteristics, as shown Figure 7a, is slightly larger to similar Zth(t) characteristics of GaN-on-SiC HEMT TGF2023-2-01 ( Figure 6a). Generally, obtained results confirm the lack of significant dependence of impedance Zth(t) on GaN HEMT bias voltage. The "tank" and "filter" configurations of Rth-Cth thermal model are considered [18]. These configurations are also known as Cauer and Foster. Both models are capable to quite accurately fit the thermal impedance Zth(t) characteristics. The "tank" circuit consists of a chain of parallel circuits Rth-Cth which is simple to mathematical description. We have developed the automatic routine of "tank" model fitting in Mathcad software. The input data for this software are the Zth(t) measurement results stored in text format file (*.csf). For assumed number of Rth-Cth cells, the software allows calculating maximum error of fitting curve.
The thermal "tank" models of selected HEMTs were calculated at following bias points: CGH27015F-VDS = 28 V, ID = 0.5 A, T8-VDS = 28 V, ID = 72 mA, TGF2023-2-01-VDS = 28 V, ID = 90 mA, NPT2022-VDS = 48 V, ID = 1.5 A. These operating points correspond to output power levels close to the maximum for each transistor. The Zth(t) characteristics were fitted to measurements with the The "tank" and "filter" configurations of R th -C th thermal model are considered [18]. These configurations are also known as Cauer and Foster. Both models are capable to quite accurately fit the thermal impedance Z th (t) characteristics. The "tank" circuit consists of a chain of parallel circuits R th -C th which is simple to mathematical description. We have developed the automatic routine of "tank" model fitting in Mathcad software. The input data for this software are the Z th (t) measurement results stored in text format file (*.csf). For assumed number of R th -C th cells, the software allows calculating maximum error of fitting curve.
The thermal "tank" models of selected HEMTs were calculated at following bias points: CGH27015F-V DS = 28 V, I D = 0.5 A, T8-V DS = 28 V, I D = 72 mA, TGF2023-2-01-V DS = 28 V, I D = 90 mA, NPT2022-V DS = 48 V, I D = 1.5 A. These operating points correspond to output power levels close to the maximum for each transistor. The Z th (t) characteristics were fitted to measurements with the error lower than 1% and are shown in Figure 8. As shown in Figure 8, the thermal models of packaged devices CGH27015F and NPT2022 are more complicated than T8 and TGF2023-2-01 die models. The last thermal cell in CGH27015F and NPT2022 models correspond to flange (or package) and thermal attachment to the cooling plate. Thermal time constants referred to individual epi-layers of GaN HEMT and depend on the sizes and material properties. However, it is rather impossible to identify in such a way physical properties of GaN-based epi-layers as the 3-D thermal problem has been reduced to the equivalent of a lumped element.
To verify thermal impedance measurements the transistor T8 was thermal modeled using 3dimensional equation of heat conduction which is solved by means of FDTD method [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. The T8 die modeled GaN HEMT structure and the assumed heat model flow are shown in Figure 9a,b, respectively. The heating area was located under the top transistor metallization, marked "red" in  As shown in Figure 8, the thermal models of packaged devices CGH27015F and NPT2022 are more complicated than T8 and TGF2023-2-01 die models. The last thermal cell in CGH27015F and NPT2022 models correspond to flange (or package) and thermal attachment to the cooling plate. Thermal time constants referred to individual epi-layers of GaN HEMT and depend on the sizes and material properties. However, it is rather impossible to identify in such a way physical properties of GaN-based epi-layers as the 3-D thermal problem has been reduced to the equivalent of a lumped element.
To verify thermal impedance measurements the transistor T8 was thermal modeled using 3-dimensional equation of heat conduction which is solved by means of FDTD method [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. The T8 die modeled GaN HEMT structure and the assumed heat model flow are shown in Figure 9a,b, respectively. The heating area was located under the top transistor metallization, marked "red" in Figure 9. The constant heat density across all heating areas was assumed. The thermal parameters of transistor materials were constant and temperature independent too. Their values are shown in the transistor heat model flow. To reduce the simulation time the adoptive mesh was applied. The minimal mesh size was 1 µm and it was at the top of thermal structure. The calculations were performed in MATLAB. Due to the very time-consuming calculations the thermal plate size was reduced. The simulation of T8 thermal impedance Z th (t) take about 24 h on PC equipped with i7 Intel processor and 16 GB RAM. The simulations and measurements of thermal impedance Z th (t) of GaN HEMT T8 are shown in Figure 10. As shown in Figure 10, the Zth(t) calculations and measurements are consistent. The highest difference is at the beginning of Zth(t) characteristic and it is probably caused by the too large mesh of 1µm. The HEMT heating area thickness across vertical direction is much smaller.
Good compliance of the thermal measurements with the manufacturer's data was also achieved. For example, the thermal resistance measurement of CGH27015F is Zth(t→∞) = 7 °C/W (Figure 5a) while Rth value given in the datasheet is 8 °C/W in the section "absolute maximum ratings" [27]. Rth values given by manufacturers are usually the "worst case" across the production.  As shown in Figure 10, the Z th (t) calculations and measurements are consistent. The highest difference is at the beginning of Z th (t) characteristic and it is probably caused by the too large mesh of 1µm. The HEMT heating area thickness across vertical direction is much smaller.
Good compliance of the thermal measurements with the manufacturer's data was also achieved. For example, the thermal resistance measurement of CGH27015F is Z th (t→∞) = 7 • C/W (Figure 5a) while R th value given in the datasheet is 8 • C/W in the section "absolute maximum ratings" [27]. R th values given by manufacturers are usually the "worst case" across the production. difference is at the beginning of Zth(t) characteristic and it is probably caused by the too large mesh of 1µm. The HEMT heating area thickness across vertical direction is much smaller.
Good compliance of the thermal measurements with the manufacturer's data was also achieved. For example, the thermal resistance measurement of CGH27015F is Zth(t→∞) = 7 °C/W (Figure 5a) while Rth value given in the datasheet is 8 °C/W in the section "absolute maximum ratings" [27]. Rth values given by manufacturers are usually the "worst case" across the production. Analyzing thermal characteristics (Figures 5 and 7) and thermal models shown in Figure 8a,d of packaged transistors CGH27015F and NPT2022 a significant difference in thermal resistance of GaN HEMTs on SiC and Si substrates may be observed. Considering only semiconductor structure (without flange) of both HEMTs with scaling factor ca. 5 (as output power ratio with correction for size of chip and package) GaN-on-Si HEMT NPT2022 R th exceeds 9 while for GaN-on-SiC HEMT R th is approx. 4.5 • C/W. This fact has been confirmed during measurements of the L-band 100 W amplifier with NPT2022 under pulse and CW (continuous wave) operation conditions. In case CW amplifier excitation, far below maximal output power obtained at the pulse operation, both output power and gain dropped sharply [28]. Moreover, the case temperature increased rapidly above recommended value by manufacturer. To correctly compare thermal properties of GaN-on-SiC HEMT (Quorvo TGF2023-2-01) and GaN-on-GaN (T8 HEMT) their size ought to be normalized, i.e., the size of TGF2023-2-01 scaled down to the size of T8 structure. Taking into consideration that GF2023-2-01 is ten-gates structure of 0.3 µm length and 1.25 mm width while T8 HEMT is two-gates of 0.8 µm length and 500 µm width and that the thickness of SiC substrate stands for 90% of the total thickness of GF2023-2-01 HEMT while T8 consists of lattice-matched GaN-based structure one would expect two times higher thermal resistance of GaN-on-GaN HEMT while in reality it is only 30% higher. The reason for that is boundary-effect leading to additional thermal boundary resistance at the interface of SiC substrate and GaN-based epi-structure in GaN-on-SiC HEMT [29,30].

Conclusions
Novel approach to characterizing self-heating process in GaN-based HEMTs has been proposed. It relies on measuring thermal impedance Z th (t) basing on MIL-STD-750D-3 standard and followed by solving 3-D heat conduction equation by means of FDTD. The thermal impedance Z th (t) of the GaN HEMT is calculated from the gate-to-source voltage measurements of the forward biased diode during cooling time after the heating pulse. A characteristic feature of our method is that during the heating phase the HEMT is biased at the operating point in which it will operate during its normal use in the transmitter's amplifiers of modern radar and wireless communication systems. Furthermore, the time delay between the heating end and the start of monitoring of V GS samples is less than 100 ns while the commercial measurement systems typically have delays as long as 5 µs. The Z th (t) characteristics enable the thermal time constants to be calculated.
The above procedures have been successfully applied to characterization of various commercial GaN HEMTs, namely CGH27015F (Wolfspeed) and TGF2023-2-01 (Qorvo) on SiC substrate, and NPT2022 (MACOM) on Si substrate as well as with T8 laboratory GaN-on-Ammono GaN HEMT.
The value of thermal resistance R th values calculated using thermal measurements for commercially available GaN-on-SiC HEMTS are consistent with manufacturer's data. The impact of material substrate on thermal features of GaN-based transistors is clearly visible. Specifically, GaN-on-Si HEMTs show much worse thermal parameters than GaN-on-SiC. The thermal characteristics of dies i.e., TGF2023-2-01 and T8 are very similar.
The main advantage of the proposed approach is that it allows taking into account the self-heating effect of transistors during design of microwave devices. That kind of knowledge can be very important in the design of high-power amplifiers for systems using variable-envelope signals such as LTE-A and 5G radios. In addition, our method enables the thermal time constants referred to the individual GaN HEMT layers to be identified. The obtained multi-section thermal equivalent circuit of transistor and resulting thermal model may be included in GaN HEMT electrical models which are implemented in popular RF and microwave simulators. Since the GaN HEMT consists of several layers, each with different thermal properties, our measurements allow evaluating heat flow across the structure as well as determining an attachment quality die to flange or package. This is especially important when designing amplifiers with transistor chips or transistors in housing for soldering on printed board circuits (PCB).