Area-E ﬃ cient Di ﬀ erential Fault Tolerance Encoding for Finite State Machines

: A di ﬀ erential fault tolerance encoding is presented for ﬁnite state machines (FSMs) to improve their area e ﬃ ciency. As the manufacturing technology for semiconductors continues to scale down, the probability of the occurrence of unexpected faults in integrated circuits has been increasing. Because an FSM controls an entire digital circuit, the faults in FSMs should be carefully addressed. Whereas the previous encoding applies a fault tolerance scheme to all the states in an FSM, the proposed encoding applies a fault tolerance scheme to only speciﬁc states depending on their importance. Compared with the previous complete fault tolerance encoding, the proposed encoding provides a comparable failure probability with a small hardware by applying the fault tolerance scheme di ﬀ erently to each state. The proposed method improves the area e ﬃ ciency by 36.1%, 43.8%, 49.2%, and 74.6% compared with that by the non-fault tolerance, previous hardware redundancy, information redundancy, and time redundancy methods, respectively. Consequently, the proposed method can provide a ﬂexible solution by applying the fault tolerance di ﬀ erently depending on the importance of the states.


Introduction
The finite state machine (FSM) is a popular technique used to model the complex operations of a general device. With the inputs provided, a device can be systematically controlled following the transition from the current state to the next state based on an FSM. Two types of FSMs are widely used, namely Mealy [1] and Moore [2] machines. Moore [2] machines determine the outputs according to only the current state, whereas Mealy [1] machines determine the output according to both the current state and current inputs. Due to the intuitive description of Mealy [1] and Moore [2] machines, FSMs are widely adopted in various operational models [3][4][5]. In particular, modern digital circuits generally employ FSMs to build control paths that control the data path efficiently [6,7]. Furthermore, FSMs should be carefully dealt with because even a minute variation in them could completely alter the overall operation of the digital circuits [6,7].
As the manufacturing technology for semiconductors continues to scale down, designing high-performance hardware with a smaller size, high throughput, and low power consumption has become an easy task for circuit designers. However, the probability of the occurrence of unexpected faults inevitably increases in integrated circuits [8,9]. Because it is impossible to eliminate unexpected faults completely, the faults should be carefully considered, beginning with the design stage to the manufacturing stage [10]. In general, faults are categorized into event upset and event transient, depending on the fault location. Event upset represents the type of fault that flips the stored bit in storage due to an energetic particle hit, and event transient represents the type of fault that generates a temporary pulse in the output of a logic gate by colliding an energetic particle with a logic gate [10,11].
Temporary event upset and event transient, known respectively as single event upset (SEU) [12,13] and single event transient (SET) [14,15], constitute the majority of the various types of faults in modern integrated chips [8,16].
To mitigate this problem, we propose a novel area-efficient and fault-tolerant encoding for FSMs. First, the proposed method divides the states into critical and non-critical states depending on the importance of the states. Then, different fault tolerances are imparted into the two sets of states. Strong fault tolerances are supported on critical states, and weak fault tolerances are supported on non-critical states. According to experimental results, the proposed method can provide a flexible area-efficient solution by applying the fault tolerance differently depending on the importance of the states. The remainder of this paper is organized as follows. Section 2 describes the background of the FSMs and the previous fault tolerant techniques. Section 3 explains the proposed discriminative encoding that provides different fault tolerances on states depending on the importance of the states. Section 4 discusses the experimental results using ISCAS'91 benchmarks, followed by concluding remarks in Section 5.

Finite State Machine
Generally, the first step in designing an FSM is to define the operation of the digital circuits as a finite number of states. Once the states are defined, each state describes the transition and the output according to the input. To design an FSM concisely, Mealy and Moore machines are widely used; the difference between these machines lies in the factors that affect the output. Mealy machines determine the output depending on both the current state and current inputs, and Moore machines determine the output depending on only the current state. Generally, Mealy machines demand fewer states with complex output logics, whereas Moore machines demand a large number of states with simple output logics. Because this research focuses on fault-tolerant encoding rather than the FSM structure, for a concise elucidation, we provide explanations based on a Mealy machine with complex output logics. It is noticeable that the proposed method can be applied to Moore machines without the loss of generality.
We adopt a dk17 FSM as an example, which is obtained from the widely used ISCAS'91 FSM benchmark, to explain the conventional and fault-tolerant FSM encoding throughout the manuscript. Figure 1 and Table 1 show the state transition graph and state transition table, respectively, for a  dk17 FSM obtained from the ISCAS'91 FSM benchmark; the graph and the table provide intuitive information about the FSM. The FSM consists of eight states, represented as S i (0 ≤ i ≤ 7), with a two-bit input I and three-bit output O ( Figure 1 and Table 1). The next state S j and output O are determined based on current state S i and input I. For example, when current S 0 receives input I = 01, the next state becomes S 3 and the output is computed as O = 010. Because S i is a symbol, it is necessary to represent state S i as a binary number to implement hardware, which is termed as state encoding. In general, binary encoding is widely used to assign the binary number of i to the ith (Table 1). Because the encoding affects the overall performance of the FSM, it should be designed carefully [16]. Figure 2 depicts a typical block diagram of the FSMs, which consists of a state register, next state logic, and output logic [17,18]. The n-bit state register stores the current state when the binary state encoding is applied, where n denotes the log of the total number of states [19]. The next state logic and output logic are responsible for calculating the next state and output, given the current state and input [17]. It is noticeable that the two logics are implemented with all combinational logics. Due to the simple structure of the FSM (Figure 2), FSMs are widely used to design the control paths in modern digital systems.  2 depicts a typical block diagram of the FSMs, which consists of a state register, next state logic, and output logic [17,18]. The n-bit state register stores the current state when the binary state encoding is applied, where n denotes the log of the total number of states [19]. The next state logic and output logic are responsible for calculating the next state and output, given the current state and input [17]. It is noticeable that the two logics are implemented with all combinational logics. Due to the simple structure of the FSM (Figure 2), FSMs are widely used to design the control paths in modern digital systems.

Fault-Tolerant Techniques
Because of the nanoscales used in the manufacturing of semiconductors, the increase in the number of malicious faults, such as event upsets, is inevitable in the existing integrated chips [8,9]. To mitigate this problem, these faults should be carefully dealt with, beginning from the design stage to the manufacturing stage. As mentioned earlier, the redundancy technique is a very popular method that can be implemented right from the design stage to improve the fault tolerance. The redundancy is mainly divided into three types: (1) hardware [20][21][22], (2) time [23], and (3) information redundancy [24].   Figure 2 depicts a typical block diagram of the FSMs, which consists of a state register, next state logic, and output logic [17,18]. The n-bit state register stores the current state when the binary state encoding is applied, where n denotes the log of the total number of states [19]. The next state logic and output logic are responsible for calculating the next state and output, given the current state and input [17]. It is noticeable that the two logics are implemented with all combinational logics. Due to the simple structure of the FSM (Figure 2), FSMs are widely used to design the control paths in modern digital systems.

Fault-Tolerant Techniques
Because of the nanoscales used in the manufacturing of semiconductors, the increase in the number of malicious faults, such as event upsets, is inevitable in the existing integrated chips [8,9]. To mitigate this problem, these faults should be carefully dealt with, beginning from the design stage to the manufacturing stage. As mentioned earlier, the redundancy technique is a very popular method that can be implemented right from the design stage to improve the fault tolerance. The redundancy is mainly divided into three types: (1) hardware [20][21][22], (2) time [23], and (3) information redundancy [24].

Fault-Tolerant Techniques
Because of the nanoscales used in the manufacturing of semiconductors, the increase in the number of malicious faults, such as event upsets, is inevitable in the existing integrated chips [8,9]. To mitigate this problem, these faults should be carefully dealt with, beginning from the design stage to the manufacturing stage. As mentioned earlier, the redundancy technique is a very popular method that can be implemented right from the design stage to improve the fault tolerance. The redundancy is mainly divided into three types: (1) hardware [20][21][22], (2) time [23], and (3) information redundancy [24].
Hardware redundancy [20][21][22] duplicates the original design by as many as the redundancy number R. Based on the majority votes, the final output is determined from among the R outputs of different hardware. For the case of R = 3, Figure 3 shows the example of a block diagram of a dk17 FSM with hardware redundancy [20][21][22], where the gray color indicates the additional hardware resources compared to the typical FSM structure. Although hardware redundancy [20][21][22] is simple to design, as shown in Figure 3, it demands the same amount of additional hardware as the redundancy number R. The hardware complexity increases substantially when a large redundancy number R is applied. Next, we discuss time redundancy. Time redundancy [23] provides fault tolerance by performing the same operation repetitively with the same hardware for the number of times corresponding to redundancy number R. Figure 4 shows the example of a block diagram of a dk17 FSM with time redundancy [20][21][22] with an additional check register and exclusive-or gate. Compared with that for hardware redundancy [20][21][22] in Figure 3, the amount of additional hardware required in time redundancy [23] is negligible, as shown in Figure 4; however, time redundancy [23] deteriorates the latency due to the large value of R resulting from additional iterations. Finally, information redundancy [24] uses additional redundant bits to represent binary numbers. In FSMs, information redundancy [24] can provide a solution that is intermediate between that of the hardware and the time redundancy techniques. For instance, the Hamming-h technique for FSMs was introduced, where Hamming distance h indicates the number of bit differences between binary vectors [24]. As the Hamming distance increases, information redundancy can provide strong fault tolerance. Table 2 shows an example of H-2 and H-3 encoding for a dk17 FSM, where H-h represents encoding with Hamming distance h. As shown in Table 2, the vectors in H-2 differ by 2 bits at most, enabling it to provide single bit fault detection. Additionally, the vectors in H-3 differ by 3 bits at most, enabling it to provide single bit fault correction. Note that binary encoding can be interpreted as H-1; thus, it can provide no fault tolerance at all. As shown in Figure 5, the previous H-h [24] in information redundancy can provide desirable fault tolerance with a small increase in the number of hardware and latency, but it must be improved further in terms of hardware efficiency. Hardware redundancy [20][21][22] duplicates the original design by as many as the redundancy number R. Based on the majority votes, the final output is determined from among the R outputs of different hardware. For the case of R = 3, Figure 3 shows the example of a block diagram of a dk17 FSM with hardware redundancy [20][21][22], where the gray color indicates the additional hardware resources compared to the typical FSM structure. Although hardware redundancy [20][21][22] is simple to design, as shown in Figure 3, it demands the same amount of additional hardware as the redundancy number R. The hardware complexity increases substantially when a large redundancy number R is applied. Next, we discuss time redundancy. Time redundancy [23] provides fault tolerance by performing the same operation repetitively with the same hardware for the number of times corresponding to redundancy number R. Figure 4 shows the example of a block diagram of a dk17 FSM with time redundancy [20][21][22] with an additional check register and exclusive-or gate. Compared with that for hardware redundancy [20][21][22] in Figure 3, the amount of additional hardware required in time redundancy [23] is negligible, as shown in Figure 4; however, time redundancy [23] deteriorates the latency due to the large value of R resulting from additional iterations. Finally, information redundancy [24] uses additional redundant bits to represent binary numbers. In FSMs, information redundancy [24] can provide a solution that is intermediate between that of the hardware and the time redundancy techniques. For instance, the Hamming-h technique for FSMs was introduced, where Hamming distance h indicates the number of bit differences between binary vectors [24]. As the Hamming distance increases, information redundancy can provide strong fault tolerance. Table 2 shows an example of H-2 and H-3 encoding for a dk17 FSM, where H-h represents encoding with Hamming distance h. As shown in Table 2, the vectors in H-2 differ by 2 bits at most, enabling it to provide single bit fault detection. Additionally, the vectors in H-3 differ by 3 bits at most, enabling it to provide single bit fault correction. Note that binary encoding can be interpreted as H-1; thus, it can provide no fault tolerance at all. As shown in Figure 5, the previous H-h [24] in information redundancy can provide desirable fault tolerance with a small increase in the number of hardware and latency, but it must be improved further in terms of hardware efficiency.  Hardware redundancy [20][21][22] duplicates the original design by as many as the redundancy number R. Based on the majority votes, the final output is determined from among the R outputs of different hardware. For the case of R = 3, Figure 3 shows the example of a block diagram of a dk17 FSM with hardware redundancy [20][21][22], where the gray color indicates the additional hardware resources compared to the typical FSM structure. Although hardware redundancy [20][21][22] is simple to design, as shown in Figure 3, it demands the same amount of additional hardware as the redundancy number R. The hardware complexity increases substantially when a large redundancy number R is applied. Next, we discuss time redundancy. Time redundancy [23] provides fault tolerance by performing the same operation repetitively with the same hardware for the number of times corresponding to redundancy number R. Figure 4 shows the example of a block diagram of a dk17 FSM with time redundancy [20][21][22] with an additional check register and exclusive-or gate. Compared with that for hardware redundancy [20][21][22] in Figure 3, the amount of additional hardware required in time redundancy [23] is negligible, as shown in Figure 4; however, time redundancy [23] deteriorates the latency due to the large value of R resulting from additional iterations. Finally, information redundancy [24] uses additional redundant bits to represent binary numbers. In FSMs, information redundancy [24] can provide a solution that is intermediate between that of the hardware and the time redundancy techniques. For instance, the Hamming-h technique for FSMs was introduced, where Hamming distance h indicates the number of bit differences between binary vectors [24]. As the Hamming distance increases, information redundancy can provide strong fault tolerance. Table 2 shows an example of H-2 and H-3 encoding for a dk17 FSM, where H-h represents encoding with Hamming distance h. As shown in Table 2, the vectors in H-2 differ by 2 bits at most, enabling it to provide single bit fault detection. Additionally, the vectors in H-3 differ by 3 bits at most, enabling it to provide single bit fault correction. Note that binary encoding can be interpreted as H-1; thus, it can provide no fault tolerance at all. As shown in Figure 5, the previous H-h [24] in information redundancy can provide desirable fault tolerance with a small increase in the number of hardware and latency, but it must be improved further in terms of hardware efficiency.

Proposed Method
The main principle behind the proposed method is to provide differential fault tolerance for the states according to the importance of the states. Whereas the previous H-h [24] encodes the states of an FSM with the same Hamming distance h irrespective of the importance of the states, the proposed method does this with different Hamming distances. More precisely, strong fault tolerance equipped with long Hamming distance is applied to the critical states, and weak fault tolerance resulting from a short Hamming distance is applied to the non-critical states. Because the hardware complexity is proportional to the Hamming distance, the proposed method can provide an area-efficient solution by providing different H-l and H-s to maintain the desirable fault tolerance. The proposed method involves three steps, namely state classification, state encoding, and FSM construction, which are discussed next.

State Classification
The first step in the proposed method is to classify the states in an FSM into critical state SC and non-critical state SNC based on their importance. In the proposed method, we define the importance of a state based on the frequency of its occurrence. When a state occurs frequently, the state determined to require strong fault tolerance is classified as the critical state. Contrarily, when the occurrence of a state is less, the state determined not to require strong fault tolerance is classified as the non-critical state. To clarify the criterion for this classification, we define the coverage C affected by strong fault tolerance, which indicates the frequency ratio of the critical states through the entire operation, i.e., # / (# # ) , where #Sc and #SNC denote the numbers of clock cycles associated with the critical and non-critical states, respectively. The classification process proceeds as follows: 1. Count the frequency of each state using an ordinary FSM with random inputs; 2. List the states based on their descending order of frequency; 3. Extract a state from the top of the frequency list and include it in the critical state Sc;

Proposed Method
The main principle behind the proposed method is to provide differential fault tolerance for the states according to the importance of the states. Whereas the previous H-h [24] encodes the states of an FSM with the same Hamming distance h irrespective of the importance of the states, the proposed method does this with different Hamming distances. More precisely, strong fault tolerance equipped with long Hamming distance is applied to the critical states, and weak fault tolerance resulting from a short Hamming distance is applied to the non-critical states. Because the hardware complexity is proportional to the Hamming distance, the proposed method can provide an area-efficient solution by providing different H-l and H-s to maintain the desirable fault tolerance. The proposed method involves three steps, namely state classification, state encoding, and FSM construction, which are discussed next.

State Classification
The first step in the proposed method is to classify the states in an FSM into critical state S C and non-critical state S NC based on their importance. In the proposed method, we define the importance of a state based on the frequency of its occurrence. When a state occurs frequently, the state determined to require strong fault tolerance is classified as the critical state. Contrarily, when the occurrence of a state is less, the state determined not to require strong fault tolerance is classified as the non-critical state. To clarify the criterion for this classification, we define the coverage C affected by strong fault tolerance, which indicates the frequency ratio of the critical states through the entire operation, i.e., C = #S C /(#S C + #S NC ), where #Sc and #S NC denote the numbers of clock cycles associated with the critical and non-critical states, respectively. The classification process proceeds as follows: 1.
Count the frequency of each state using an ordinary FSM with random inputs; 2.
List the states based on their descending order of frequency; 3.
Extract a state from the top of the frequency list and include it in the critical state Sc; 4.
Repeat step (3) until the accumulation of frequency exceeds the coverage C; 5.
Include the remaining states in the non-critical state S NC .
Following this process, all the states are classified into critical and non-critical states by satisfying the condition that the accumulated ratio of the most frequent states exceeds the coverage C. It means that the strong fault tolerance affects more than C when applying strong fault tolerance to the critica state S C . Note that step 1 should be performed until the frequency is saturated, to achieve a reliable frequency. Table 3 lists the state classification for a dk17 FSM. To achieve a reliable frequency, step 1 is iteratively performed 10 7 times with random inputs. As a result, the frequency of the original states of a dk17 FSM is sorted in descending order and accumulated. Table 3 indicates that S 3 is the most frequent state with a frequency of 24.58%, whereas S 6 is the least frequent state with a frequency of 0.96%. For various values of target coverage C, the critical state becomes different, as shown in Table 3. For instance, the critical set includes (S 3 , S 2 ) and (S 3 , S 2 , S 4 ) for the cases of C = 30% and C = 60%, respectively. Note that C = 0% indicates a non-fault-tolerant FSM, and C = 100% corresponds to the previous H-h FSM. Table 3 divides the states into two sets; however, the proposed method can be extended further by dividing the states into more than two sets to realize finely controlled fault tolerance.

State Encoding
After the classification of the states, the next step is to assign a strong fault tolerance to the critical state and a weak fault tolerance to the non-critical state. Generally, the Hamming distance is used to represent the capability of fault tolerance, because h = (2t + 1) encoding guarantees t fault correction at most. For instance, H-3 and H-5 can correct one and two faults at most, respectively. Therefore, the register-transfer level design selects a suitable Hamming distance for each critical and non-critical set individually. Table 4 illustrates the state encoding manner depending on the Hamming distance in the case of a dk17 FSM; here, we assumed that coverage C = 60% with S C = {S 3 , S 2 , S 4 }. In Table 4, the pairs of (H-hs, H-hw) represent that a strong Hamming encoding of H-hs is applied to the critical state and a weak hamming encoding of H-hw is applied to the non-critical state, where hs ≥ hw. As for the coverage C = 60%, the critical set containing S 3 , S 2 , and S 4 maintains the Hamming distance hs, and the non-critical set containing S 0 , S 1 , S 5 , S 6 , and S 7 maintains the Hamming distance hw. Because a strong fault tolerance demands a long Hamming distance, the number of bits required to encode the states increases with the increasing Hamming distance. Furthermore, Table 5 shows the state encoding manner depending on the coverage C of a dk17 FSM; here, we assume that the pair (H-3, H-1) is applied. The number of states in the critical set increases to 2, 3, and 5, as the coverage C extends from 30% to 90%. Because the critical state demands a larger number of bits than the non-critical state, the total number of bits required to encode the states increases as the number of critical states increases. It is thus apparent that a longer bit is inevitably required for realizing stronger fault tolerance and wider coverage.

FSM Construction
Finally, a new state transition table should be completed to construct an FSM for the proposed differential encoding. We additionally define a redundant state S R , which possesses the error correction capability. The redundant state S R , neighboring the critical state in terms of encoding, is assigned to the same operation as the critical state. When a minor fault occurs in the critical state S C , there is a high probability of moving the redundant state S R , resulting in fault correction by performing a similar operation to the original one. As an example, Table 6 shows the state transition table for the proposed differential (H-3, H-1) encoding with coverage C = 60%. The critical states S 2, S 3 , and S 4 are protected using a redundant state S R that generates an identical next state and output. For instance, when a single fault occurs on S 2 at any bit position, an identical next function S 0 and output O = 001 in I = 00 can be obtained using the redundant state S R . Given the state transition table, FSM can be implemented based on a typical FSM, as shown in Figure 6. The proposed method encodes the states differentially by assigning more bits to the critical states and fewer bits to the non-critical states. Because the bit length obtained from state encoding determines the hardware complexity of the overall FSM, the proposed method can provide an area-efficient fault-tolerant encoding for FSMs. Note that the additional logic in the proposed method is smaller than that in the information redundancy method due to the differential encoding. Furthermore, the proposed method can be simply extended to more than two types of states corresponding to the importance of the states; however, this section focused only on a case with two types of states.

Experimental Results
For a fair comparison, we implement four FSMs from ISCAS'91 FSM benchmarks using a 180 nm CMOS process. Because the proposed method provides a flexible solution, a non-fault tolerance can be interpreted as corresponding to the proposed method with C = 0%, and the previous H-h encoding [24] to the proposed method with C = 100%. First, the area complexity is compared in terms of equivalent gate counts, and the failure rate is analyzed with single, double, and triple fault cases. Finally, the area efficiency calculated from the two comparisons is described to verify the advantages

Experimental Results
For a fair comparison, we implement four FSMs from ISCAS'91 FSM benchmarks using a 180 nm CMOS process. Because the proposed method provides a flexible solution, a non-fault tolerance can be interpreted as corresponding to the proposed method with C = 0%, and the previous H-h encoding [24] to the proposed method with C = 100%. First, the area complexity is compared in terms of equivalent gate counts, and the failure rate is analyzed with single, double, and triple fault cases. Finally, the area efficiency calculated from the two comparisons is described to verify the advantages of the proposed method.
Among the various FSMs available in the ISCAS'91 FSM benchmark, we adopt four FSMs, namely dk17, dk512, bbara, and beecount, since they are synthesizable and provide FSM states from 7 to 15. After designing various FSMs with different coverages and fault tolerances, they are synthesized via a 180 nm CMOS process at the working frequency of 200 MHz. Figure 7 shows the equivalent gate counts according to coverage C and Hamming distance h. Figure 7 shows that the hardware complexity increases as the coverage increases and the Hamming distance increases due to the increase in the number of state bits. Note that the previous non-fault tolerance represented by C = 0% involves the least hardware complexity, and the previous Hamming represented by C = 100% involves the highest hardware complexity, for all cases.  Moreover, the fault rate is analyzed for the proposed method with different coverages and Hamming distances. To perform a practical simulation [25], the error model is designed based on real fault patterns. The stuck-at-zero and stuck-at-one models are used, which represent the situation in which an energetic particle causes the fixed state of the storage temporally [26]. For the number of faults, [8] indicates that SEU is the most frequent fault, and single event multiple upset (SEMU) with up to three bits is dominant in modern integrated circuits [27]. To compute the fault rate of an FSM, it is operated for 1024 clock cycles and random faults using either stuck-at-zero or stuck-at-one models are inserted for one clock cycle [25,28]. Figure 8 shows the failure rate of the proposed method, in which a failure in FSM counts when either the output or the current state of normal operation without faults is different from that of a faulty operation. To account for the cases of both SEU and SEMU, various failure rates are computed under single, double, and triple fault injections [27], as depicted. Figure 8 shows that the failure ratio improves due the increase in the coverage and the Hamming distance caused by providing strong fault tolerance on more states. The previous nonfault tolerance represented by C = 0% provides the worst fault tolerance and the previous Hamming encoding represented by C = 100% provides the best fault tolerance, in all cases. Moreover, the fault rate is analyzed for the proposed method with different coverages and Hamming distances. To perform a practical simulation [25], the error model is designed based on real fault patterns. The stuck-at-zero and stuck-at-one models are used, which represent the situation in which an energetic particle causes the fixed state of the storage temporally [26]. For the number of faults, [8] indicates that SEU is the most frequent fault, and single event multiple upset (SEMU) with up to three bits is dominant in modern integrated circuits [27]. To compute the fault rate of an FSM, it is operated for 1024 clock cycles and random faults using either stuck-at-zero or stuck-at-one models are inserted for one clock cycle [25,28]. Figure 8 shows the failure rate of the proposed method, in which a failure in FSM counts when either the output or the current state of normal operation without faults is different from that of a faulty operation. To account for the cases of both SEU and SEMU, various failure rates are computed under single, double, and triple fault injections [27], as depicted. Figure 8 shows that the failure ratio improves due the increase in the coverage and the Hamming distance caused by providing strong fault tolerance on more states. The previous non-fault tolerance represented by C = 0% provides the worst fault tolerance and the previous Hamming encoding represented by C = 100% provides the best fault tolerance, in all cases.  Finally, we compare the area efficiency of the proposed method. In this comparison, area efficiency is measured by a normalized (100 − failure rate)/(area × latency). The non-fault tolerance encoding interpreted as C = 0% of the proposed method exhibits the smallest area requirement with the worst failure rate. Contrarily, the previous Hamming encoding interpreted as C = 100% of the proposed method exhibits the largest area requirement with the best failure rate. Therefore, it is clear that unlike the two extreme cases of the previous method, the proposed method can provide an intermediate solution that requires a feasible area with a reliable failure rate by improving the area efficiency. Figure 9 shows the area efficiency according to the coverage C and Hamming distance h. The proposed method can provide a better solution than the previous encoding at all times. On average, the proposed method improves the area efficiency by 36.1% and 49.2% compared with that by non-fault tolerance (C = 0%) and Hamming encoding (C = 100%), respectively. Furthermore, the proposed method improves the area efficiency by 43.8% and 74.6% compared with that by previous hardware redundancy and time redundancy, respectively. As a result, the proposed method can provide the most efficient method compared to previous hardware, time, and information redundancy methods. Since the proposed method can be applied to any FSMs, it is allowed to apply the proposed method for any modern circuits equipped with an FSM. Finally, we compare the area efficiency of the proposed method. In this comparison, area efficiency is measured by a normalized (100 − failure rate)/(area × latency). The non-fault tolerance encoding interpreted as C = 0% of the proposed method exhibits the smallest area requirement with the worst failure rate. Contrarily, the previous Hamming encoding interpreted as C = 100% of the proposed method exhibits the largest area requirement with the best failure rate. Therefore, it is clear that unlike the two extreme cases of the previous method, the proposed method can provide an intermediate solution that requires a feasible area with a reliable failure rate by improving the area efficiency. Figure 9 shows the area efficiency according to the coverage C and Hamming distance h. The proposed method can provide a better solution than the previous encoding at all times. On average, the proposed method improves the area efficiency by 36.1% and 49.2% compared with that by non-fault tolerance (C = 0%) and Hamming encoding (C = 100%), respectively. Furthermore, the proposed method improves the area efficiency by 43.8% and 74.6% compared with that by previous hardware redundancy and time redundancy, respectively. As a result, the proposed method can provide the most efficient method compared to previous hardware, time, and information redundancy methods. Since the proposed method can be applied to any FSMs, it is allowed to apply the proposed method for any modern circuits equipped with an FSM.

Conclusions
An area-efficient encoding method was proposed for FSMs to encode the states differently depending on the importance of the states. Unlike the previous non-fault tolerance or complete fault tolerance encoding with a constant Hamming distance, the proposed method classifies the states into critical and non-critical states. After this classification, the proposed method provides a strong fault tolerance to the critical states and a weak fault tolerance to the non-critical states. The fault tolerance results from a long Hamming distance, which increases the hardware complexity. According to the experimental results using the ISCAS'91 FSM benchmarks, the proposed method provides a flexible solution to assign different fault tolerances rather than a fixed fault tolerance. The proposed method improves the area efficiency by 36.1%, 43.8%, 49.2%, and 74.6% compared with that by the non-fault tolerance, previous hardware redundancy, information redundancy, and time redundancy methods, respectively. Furthermore, the proposed method can be extended by classifying the states into more than two sets to realize finely controlled fault tolerance to further improve the area efficiency. For future research, we aim to study a stronger fault-tolerant method resistant to multiple upsets. The proposed method has a limitation in that it supports only single event upset and single event transient. Thus, further research will be conducted on supporting multiple event upset and transient to enhance fault tolerance.

Conclusions
An area-efficient encoding method was proposed for FSMs to encode the states differently depending on the importance of the states. Unlike the previous non-fault tolerance or complete fault tolerance encoding with a constant Hamming distance, the proposed method classifies the states into critical and non-critical states. After this classification, the proposed method provides a strong fault tolerance to the critical states and a weak fault tolerance to the non-critical states. The fault tolerance results from a long Hamming distance, which increases the hardware complexity. According to the experimental results using the ISCAS'91 FSM benchmarks, the proposed method provides a flexible solution to assign different fault tolerances rather than a fixed fault tolerance. The proposed method improves the area efficiency by 36.1%, 43.8%, 49.2%, and 74.6% compared with that by the non-fault tolerance, previous hardware redundancy, information redundancy, and time redundancy methods, respectively. Furthermore, the proposed method can be extended by classifying the states into more than two sets to realize finely controlled fault tolerance to further improve the area efficiency. For future research, we aim to study a stronger fault-tolerant method resistant to multiple upsets. The proposed method has a limitation in that it supports only single event upset and single event transient. Thus, further research will be conducted on supporting multiple event upset and transient to enhance fault tolerance.