A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

: This paper exploits an effective approach to overcome the breakdown limitations of traditional galvanic isolators based on chip-scale isolation barriers, thus achieving a very high isolation rating (i.e., compliant with the reinforced isolation requirements). Such an approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips. Standard packaging along with proper assembling techniques can be profitably used to go beyond 20-kV surge voltage without using expensive or exotic isolation components. As a proof of concept, a bidirectional data transfer system based on RF planar coupling able to withstand an isolation rating as high as 25 kV has been designed in a low-cost standard 0.35-µm CMOS technology. Experimental measurements demonstrated a maximum data rate of 40 Mbit/s using a carrier frequency of about 1 GHz. The adopted approach also guarantees a common mode transient immunity (CMTI) of 250 kV/µs, which is a first-rate performance in view of next generation galvanic isolators for wide-bandgap power semiconductor devices, such as gallium nitride high-electron mobility transistors (GaN HEMTs) and silicon carbide (SiC)


Introduction
In the last decade, several applications take advantage of galvanic isolation to improve safety and reliability, especially in harsh environments. Galvanic isolation is required in the automotive applications (i.e., electric and hybrid vehicles), in the industrial environment (i.e., motor control, automation, etc.), in medical equipment, in consumer products (i.e., home appliance, inductive cooking, etc.) and even in communication networks. A galvanic isolator guarantees data transfer across a galvanic barrier and enables bidirectional communication between two isolated interfaces. A typical galvanically isolated system is depicted in Figure 1. Data communication must be assured not only in the presence of the static difference of potential between the ground references, but also when a rapid shift of grounds occurs. Therefore, a key performance parameter of a galvanic isolator is the common mode transient immunity (CMTI), whose typical values range from 50 to 100 kV/µs. However, the CMTI requirements are becoming more demanding (i.e., > 200 kV/µs) due to the higher switching frequencies allowed by wideband power devices, such as gallium nitride high-electron mobility transistors (GaN HEMT) and silicon carbide (SiC) MOSFETs.
According to recent standardization [1], semiconductor galvanic isolators must withstand high voltages not only for short periods of time (i.e., namely the maximum transient isolation voltage), but also throughout the device lifetime (i.e., namely the maximum repetitive voltage). However, the most stringent specification is represented by the maximum surge isolation voltage, VSURGE, that quantifies the capability of the isolator to withstand very high voltage impulses of a certain transient profile, which can arise from indirect lightning strikes or faults. At the component level, the reinforced isolation level is achieved if the VSURGE is higher than 10 kV. At the present time, both industrial and automotive applications are moving towards 10 kV, some applications. (e.g., patient monitoring systems) already require a VSURGE higher than 15 kV, while galvanic isolation up to 20 kV will be required very soon. State-of-the-art galvanic isolators are based on electromagnetic (EM) coupling (i.e., capacitive or inductive) across a dielectric layer (i.e., the galvanic barrier). Such isolators use either integrated SiO2 or a post-processed polyimide layer. They present inherent limitations in terms of isolation that have been improved only by means of expensive and time-consuming technological arrangements. Moreover, traditional isolation barriers are hardily compliant with CMTI better than 150 kV/µs, thus preventing the highest switching speed operation of wide-bandgap power transistors. This paper explores an alternative approach to overcome both breakdown voltage (BV) and CMTI limitations of semiconductor isolators without reducing the level of integration (i.e., a two dice system-in-package). The approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips [2]. The paper is organized as follows. A brief overview of the main isolation technologies is reported in Section 2, while the RF planar isolation approach is discussed in Section 3 along with the circuit design of the data transfer system. The experimental performance is detailed in Section 4 along with the comparison with the state-of-the-art, and final conclusions are drawn in Section 5.

Technologies for Chip-Scale Galvanic Isolators
An integrated galvanic barrier can be implemented by using silicon dioxide (SiO2), which exhibits a breakdown voltage (BV) of about 1000 V/µm [3], sometimes in combination with silicon nitride (Si3N4) and oxynitride (SiON) to further improve its isolation rating [4]. Oxide galvanic isolation has been successfully exploited in recent years for highly integrated isolated data [5][6][7] and power transfer interfaces [8][9][10][11][12] by means of on-chip capacitors or stacked transformers. However, oxide insulation can reliably provide a limited surge capability (typically 5-6 kV), since increasing the oxide thickness produces wafer mechanical stress and second order BV effects. The use of two series-connected galvanic isolation barriers, namely double isolation, can be exploited to improve the overall isolation rating. This is a viable solution for digital isolators (i.e., only data transfer) [13], with a maximum VSURGE around 13 kV by using a couple of isolation capacitors [14].
The galvanic barrier can be also implemented with other dielectric layers, such as the polyimide, traditionally used in semiconductor industry for stress relief. In this case, the isolation device (typically a stacked transformer) is built as a stand-alone chip by using a custom technology at the cost of reducing the integration level (i.e., from two to three chips per each isolated channel). This approach guarantees high data rates with a very good isolation rating and CMTI performance [15], while being also suited to a power transfer up to several hundreds of mW [16]. Due to a poorer polyimide BV, typically the isolation layer is about 3x thicker to sustain the same surge voltage of an oxide barrier. On the other hand, very thick polyimide layers can be manufactured with a record of 32.5-µm thickness able to withstand 20 kV [15], which is not feasible using silicon dioxide layers. In any case, isolation approaches, based either on integrated SiO2 barriers or post-processed polyimide transformers, have inherent limitations in terms of isolation due to the maximum dielectric thickness that can be reliably manufactured. Little improvements can be achieved at the cost of expensive and time-consuming technological advances.
However, galvanic isolation can be also provided by substituting chip-scale isolation barriers (i.e., SiO2 or polyimide capacitors and transformers) with a package-scale isolation one. In other terms, packaging/assembling techniques and RF coupling between micro-antennas can be properly used to provide isolation and data communication. Some RF galvanic isolators exploit wireless transmission between two stacked chips by means of silicon integrated near-field antennas [17]. To reduce the distance between stacked antennas, the dice can be also assembled face-to-face at the cost of fabricating through holes vias to have a rear side connection [18,19]. A very high isolation rating can be achieved by using proper dielectric isolator films between the dice (i.e., glass, polyimide die attach film etc.). However, the chip assembling complexity and package cost have hindered a widespread adoption of this isolation technology. These drawbacks can be avoided if dice are placed side by side on the package substrate exploiting the magnetic coupling between coplanar antennas. In this case, the physical channel for data communication exploits the weak near-field coupling between two micro-antennas integrated on two side-by-side co-packaged chips (i.e., chip 1 and chip 2), as shown in Figure 2. In this approach, the distance through insulation (DTI), which is responsible for the isolation rating, can be properly increased to guarantee the required VSURGE. Standard molding compounds have a dielectric strength (EM) of at least 50 V/µm, and therefore with a DTI of about 400-500 µm, an isolation rating higher than 20 kV can be achieved [20,21]. Moreover, the intrinsic parasitic capacitance of the isolated channel is extremely low if compared with the ones of traditional chipscale barriers (i.e., isolation capacitors or stacked transformers), thus reducing common mode (CM) currents produced by rapid ground shifts (i.e., CM transients).

Fabrication Technology and System Description
The proposed isolated data transfer system is made up of two chips integrated in a low-cost 0.35-µm CMOS technology provided by STMicroelectronics to be packaged in a standard plastic package on two separated lead frames. The distance between the lead frames (i.e., the DTI in Figure  2) was set to 500 µm to guarantee an isolation rating well above 20 kV. The simplified block diagram of an isolated data transfer channel is shown in Figure 3. Each communication channel exploits two dedicated micro-antennas integrated on chips 1 and 2 for data transmission (TX) and reception (RX), respectively. The EM coupling between the planar antennas through the package molding compound determines the attenuation of the isolated channel, which must be minimized by a proper design of the antenna geometries, as discussed in Section 3.1. Due to the weak EM coupling, the system is designed for narrowband RF operation with both TX and RX antennas in the resonant mode, which are properly tuned at the working frequency. Data transmission exploits the on-off keying (OOK) pulse width modulation (PWM) of an RF carrier (see Figure 4), since it also provides an easy way for clock recovering. Typically, the value of the carrier frequency, fRF, is a tradeoff among contrasting performance parameters, such as antenna coupling and silicon area from one side and current consumption to the other. In this work, an RF carrier frequency of about 1 GHz was chosen, being in some extent also limited by the poor fT performance of the adopted 0.35-µm CMOS node (i.e., about 27 GHz). The voltage supply, VDD, was set to 3.3 V. As shown in Figure 3, chip 1 also includes a TX front-end driven by a base-band interface (i.e., PWM modulator), while chip 2 consists of an RX front-end with a base-band interface for data demodulation (i.e., PWM demodulator). The following subsections will detail the design of the overall isolated data transfer system, i.e., the micro-antennas, the TX front-end, the RF-front-end and the PWM modulator/demodulator.

On-Chip Micro-Antennas
The key point of the proposed isolation approach is the maximization of the EM coupling between the TX and RX antennas. To this aim, it is of utmost importance to reduce the energy loss occurring into both the metal spirals and silicon substrate, which turns in a higher quality factor (Qfactor) of the antennas and better EM coupling between them. In particular, the antenna coupling is considerably affected by the substrate conductivity, σS, mainly due to the magnetically induced substrate eddy currents [22]. In this work, the antennas were designed by taking advantage of the top Al layers of the adopted CMOS technology (i.e., 3-µm metal 4 and 1-µm metal 3). The design was carried out by using EM simulations and to this aim the simulator set-up was preliminary verified by taking advantage of the S-parameter measurements of both the on-wafer single antennas and coupled antennas mounted on a testing PCB, as shown in Figure 5 [23]. The first step of the design was the definition of the antenna geometry in terms of shape, number of turns (n), metal width (w), metal spacing (s) and outer diameter (dOUT). It was mainly accomplished by means of extensive 2D EM simulations in Keysight ADS Momentum, while the time-consuming 3D EM simulations (i.e., Ansoft HFSS) were exploited in the final phase to obtain more precise results. To guarantee more than a 20-kV isolation rating, the DTI between the lead frames was set to 500 µm, which turned in 650 and 730 µm between the chips and the antennas, respectively. Although circular or polygonal spirals achieve a better Q-factor performance, the square shape was preferred for both the TX and RX antennas since this allows optimizing the inductance/area ratio while improving the planar coupling between coils. The minimum metal spacing allowed by the technology was adopted (i.e., 2.75 µm) to maximize coil self-inductance. The number of turns, n, and diameter, dout, were chosen to tradeoff the inductance value and the coil area, while the metal width, w, was set to tune the Q-factor and the self-resonance frequency (SRF). Moreover, a turn ratio (i.e., nRX/nTX) of about 1.7 was exploited to step up the signal received by chip 2. The result of the antenna design optimization is reported in Table 1 which summarizes the geometrical parameters of the TX and RX antennas, while Figure 6a shows the antenna layout. Figure 6b shows the antenna 3D simulations carried out in HFSS. A standard molding compound with a dielectric constant, εR, equal to 3 was included to account for the package capacitive effects, which are fundamental to estimate the CMTI performance of the isolated channel.
To fully understand the impact of the most important design and process parameters on the antenna performance, some EM parametric simulations are reported hereinafter. Figure 7 shows the EM coupling in terms of insertion loss (i.e., IL = −20log S21) between the TX/RX antennas that are spaced by 730 µm (i.e., 500 µm between lead frames). IL is given for the different substrate conductivities, σS, which range from 0.1 to 10 4 S/m (i.e., from very low to very high conductivity substrate). At low values of σS, IL is quite constant, while it rises for σS higher than 10 3 with a coupling degradation of 13 dB at σS = 10 4 S/m. Therefore, typical substrate conductivity values of standard CMOS and BiCMOS technologies are fully compatible with the proposed RF planar isolation approach, whereas those of standard BCD technologies (in the order of 10 4 S/m) are critical values and require more complex implementations. Figure 8 represents the variation of IL at increasing values of DTI and hence at increasing values of the isolation rating, for a molding compound dielectric strength, EM, of about 50 V/µm. The IL curve at 1 GHz exhibits a slope of about 0.6 dB/kV and at 500-µm DTI, corresponding to an isolation rating of 25 kV, the IL is about 54 dB. Finally, Figures 9 and 10 show the simulated inductance and Q-factor of the TX and RX antennas at 500-µm DTI, respectively, while IL as a function of frequency is reported in Figure 11.    Although IL is usually used to account for the loss of a passive component, it does not represent the actual coupling loss between the TX and RX antennas since it is calculated with 50-Ω terminations, whereas the RX input impedance, ZIN_RX, is usually quite high. Moreover, the antennas are operated   Figure 3. For the sake of completeness, the inductance, the Q-factor, the IL and the magnetic coupling factor at 1 GHz (L1GHz, Q1GHz, IL1GHz, k1GHz) are reported in Table 2 for both the TX and RX antennas, along with the SRF and the TX-to-RX coupling losses at 1 GHz in the resonant mode in open-circuit (TRX_OC) and 10-kΩ (TRX_10kΩ) conditions.

TX Front-End
For a better robustness, a PWM technique with an RF carrier was adopted. A baseband PWM modulator is used to generate the PWM signal, PWMIN, which drives the transmitter, TX, as shown in Figure 3. In this work, the PWM modulator is implemented by means of a simple digital scheme, as depicted in Figure 12. The input data, DIN, is first synchronized with the input clock, CKIN, by means of the D flip-flop, DFF1. The synchronized input data, DSYNC, and the elongated version of the clock signal, CKL, are used to produce the data signal, D1, which differs from DSYNC for a reduced bit time duration. Finally, D0 is generated by the D flip-flop, DFF2, driven by the voltage supply, VDD, clocked by CKIN and reset by the delayed clock signal, CKD. The resulting PWM signal is easily obtained as the sum of D0 and D1 and consists of pulse train at the data rate frequency, fD, with the

TX-to-RX insertion loss [dB]
Frequency [GHz] bit time durations T0 and T1 for bits "0" and "1", respectively. As an example, for an fD of 40 Mbit/s, the bit time durations T0 and T1 are 18 ns and 8 ns, respectively, with a minimum time guard between a falling edge and the next rising edge of 7 ns. By varying fD, both T0 and T1 change accordingly, but the minimum time guard remains fixed at 7 ns. For the sake of completeness, Figure 13 displays the PWM modulator signals for an fD of 40 Mbit/s and the bit sequence "110101".  The TX front-end was implemented by means of an RF oscillator by exploiting the TX spiral antenna inductance for the resonant tank. Indeed, the oscillator can be properly turned on and off by using MOS switches controlled by the PWM signal. The main design issues are related to the codesign between the RF oscillator and the TX antenna, as well as the reduction in the current consumption for a given oscillation voltage and the minimization of the start-up time. In this work, an inductor-loaded complementary cross-coupled oscillator was adopted, as shown in Figure 14. Compared with the traditional NMOS cross-coupled oscillator, this topology maximizes the oscillation amplitude within the supply voltage, thus avoiding the need for special thick oxide/lateral transistors with high breakdown voltages [11,12], which are not usually available in standard CMOS technologies. On the other hand, the use of complementary MOS transistor couple pairs give the advantage of nearly double the transconductance at the same current level compared with a simple cross-coupled oscillator, also minimizing the startup-time. An additional capacitor, C2, of about 800 fF was added to tune the oscillator at about 1 GHz. The TX oscillator produces a full swing oscillation (i.e., amplitude about equal to VDD) with a current consumption of 4.5 mA. The total current consumption of the TX section is dominated by the oscillator contribution, which is also a critical parameter of the overall system.

RX Front-End
The rail-to-rail TX signal is greatly attenuated (of about 27 dB) through the isolated channel and therefore the RX front-end must raise it before the rectification and data demodulation. Figure 15 shows the simplified schematic of the RX front-end. It consists of a differential amplifier with resistive load to minimize the silicon area. The signal at the RX antenna is around 140 mV, and the amplifier stage raises up it to around 400 mV (i.e., 8.4-dB voltage gain) with a current consumption of 1 mA. Then, a double-balanced mixer based on a Gilbert cell is exploited as rectifier stage. The output RC load of the mixer guarantees a low-pass filtering to clean the RX signal envelope. The rectification stage provides an additional gain of about 8 dB with a current consumption of 0.6 mA. Finally, the rectified signal is compared with a threshold level to recover the original TX PWM signal. The choice of the threshold determines the RX immunity to noise. In worst case conditions, the minimum amplitude of the rectified signal is higher than 500 mV and thus a 450-mV threshold was adopted. Figure 16 shows the amplified RX signal (i.e., mixer input voltage) and the RX envelope voltage (i.e., the mixer output voltage) along with the threshold voltage adopted for the reconstruction of the PWM signal. Finally, Figure 17 shows the base-band circuit used for the PWM demodulator, which recovers clock, CKOUT, and data, DOUT, from the PWMOUT signal, as displayed in Figure 18. The adopted planar isolation approach is very effective also in terms of CMTI since the isolated channel exhibits a very low parasitic capacitance (i.e., below 5 fF) compared with typical values of traditional isolators. Of course, the adoption of a fully differential architecture is mandatory to reject the induced CM transients. However, a correct estimation of the CMTI performance needs to accurately account for process mismatches by means of Montecarlo (MC) simulations. Figure 19 shows the MC simulation of the isolated data link at 40 Mb/s in the presence of a 250-kV/µs CM disturbance. As is apparent, the OOK-modulated signal at the RX antenna is not significantly affected by the CM disturbance and accurate data, DOUT, and clock, CKOUT, demodulation are obtained.

Experimental Results
The bidirectional isolated data transfer system was implemented by using two identical dice, each including both TX and RX circuitry, as shown in the photograph of Figure 20. The overall die size is 2820 µm × 1340 µm. However, the TX active area including the antenna is only 700 µm × 550 µm, while the RX area is 960 µm × 550 µm. As depicted in Figure 21, the chips were assembled sideby-side on the metal frame with a DTI of 500 µm, thus obtaining a bidirectional data transfer system with very high galvanic isolation, provided that a standard molding compound with the dielectric strength, EM, of about 50 V/µm will be used for packaging. A distance between the isolated channels of about 1700 µm was adopted to reduce the cross-talk at the expense of a higher area consumption. Experimental measurements were carried out at 3.3-V voltage supply up to a data rate of 40 Mbit/s and confirmed the simulated performance.    (9) 286 ̶ ̶ 6000 11682 FoM3 (10) 26 ̶ ̶ ̶ 730 (1) Low/high side; (2) rms; (3) VDD = 5 V; (4) 1.3/2 GHz; (5) From micrographs in [25,26]; (6) Total area/active area; (7) Die attach film (DAF); (8) FoM1 = (VSURGE · CMTI· fDMAX)/(tp·IDD_CH); (9) FoM2 = (VSURGE · CMTI)/EBIT; (10) FoM3 = (VSURGE · CMTI)/(tp·EBIT). Table 3 summarizes the measured performance of the proposed galvanically isolated data transfer system in comparison with the state-of-the-art of galvanic isolators. The comparison is carried out with the best-in-class transformer-based isolator in terms of isolation rating and CMTI [15], as well as with a chip-scale isolator in a standard technology in [24] and package-scale isolators based on stacked or planar coupling [19,25]. The work in [15] achieves a first-rate 20-kV isolation rating and 200-kV/µs CMTI thanks to a dedicated thick polyimide transformer (i.e., 32.5-µm thickness). However, such a performance is guaranteed only at a very low data rate (i.e., 1 Mb/s) and hence quite high energy per bit, EBIT, (i.e., 4.8 nJ/ns). On the other hand, the implementation of a very thick polyimide layer is not trivial in terms of the process complexity and costs. A package-scale isolation barrier implemented by means of face-to-face stacked chips bonded with a die attach film (DAF) (as previously claimed by patent [18]) is exploited in [19] to attain an isolation rating of nearly 10 kV in a 0.25-µm SOI BiCDMOS technology. However, this package-scale galvanic isolator exhibits poor performance in terms of both data rate, fD, propagation delay, tp, and energy per bit, EBIT, while no CMTI value is provided. Moreover, the isolator performance is extremely sensitive to chip alignment, which increases the complexity and cost of the solution. The work in [24], which explores lateral coupled resonators with gap silicon oxide isolation, has the advantage of providing more than 4.5-kV galvanic isolation in a standard 0.25-µm BCD technology without any dedicated isolation component (i.e., thick oxide/polyimide capacitors/transformers). Despite the very good data rate and propagation delay performance, it suffers from the highest current per channel, IDD_CH, and high EBIT, as [15] and [19]. Moreover, no CMTI performance is given, which could be considerably degraded by the high parasitic fringing capacitances of the adopted laterally coupled isolation structures due to the narrow oxide gaps (i.e., 3-µm).
The best comparison is with the die-to-die isolated link reported in [25], which exploits an isolation approach based on planar coupling between side-by-side co-packaged chips, thus achieving almost the same isolation rating of our system. Among the papers in Table 3, it also reports the highest fD and the lowest EBIT, but such a performance is mainly enabled by the adopted 0.18-µm CMOS technology and consequently higher fRF with respect to our work in 0.35-µm CMOS. On the other hand, a CMTI of only 50 kV/µs is claimed, which is already now inadequate for most current applications, while no propagation delay performance is provided, although it is a fundamental parameter, especially for gate-driver applications. Finally, the silicon area per channel, ACH, is nearly double compared with the proposed work. Indeed, differently from our approach, peripherical TX/RX antennas (i.e., with a very large diameter and low number of turns) are used, including all circuitry inside them. Table 3 contains three figures of merits (FoMs) to better evaluate and compare the reported works. All adopted FoMs account for the isolation rating, VSURGE, and the CMTI. The first figure of merit, FoM1, was the already defined in [15] and here it is properly weighted by the data rate, fDMAX. On the other hand, both FoM2 and FoM3 exploit the energy per bit, EBIT, in the place of IDD_CH to better weigh both the data rate and power consumption, while they differ from the presence of the propagation delay, td. Reported values in Table 3 clearly highlight that the proposed work outperforms the state-of-the-art in terms of all the adopted FoMs.

Conclusions
A 0.35-µm CMOS bidirectional data transfer system based on RF planar coupling for reinforced galvanic isolators has been presented. With a standard molding compound, it achieves an isolation rating as high as 25 kV and guarantees 250-kV/µs CMTI at a maximum data rate of 40 Mb/s, thus outperforming traditional silicon-integrated isolators. The proposed package-scale isolation is also a low-cost solution since it can be implemented by using standard CMOS and package technologies, while providing an integration level comparable with state-of-the-art chip-scale solutions. The isolation rating and CMTI performance enable high-voltage/high-switching frequency applications based on wide-bandgap power semiconductor devices, such as GaN HEMTs and SiC MOSFETs.