Analytical Drain Current Model for a-SiGe:H Thin Film Transistors Considering Density of States

Thin film transistors (TFTs) fabricated on flexible and large area substrates have been studied with great interest due to their future applications. Recent studies have developed new semiconductors such as a-SiGe:H for fabrication of high performance TFTs. These films have important advantages, including deposition at low temperatures and low pressures, and higher carrier mobilities. Due to these advantages, the a-SiGe:H films can be used in the fabrication of TFTs. In this work, we present an analytical drain current model for a-SiGe:H TFTs considering density of states and free charges, which describes the current behavior at sub-and above- threshold region. In addition, 2D numerical simulations of a-SiGe:H TFTs are developed. The results of the analytical drain current model agree well with those of the 2D numerical simulations. For all characteristics of the drain current curves, the average absolute error of the analytical model is close to 5.3%. This analytical drain current model can be useful to estimate the performance of a-SiGe:H TFTs for applications in large area electronics.


Introduction
Thin film transistors (TFTs) are key devices to develop large area electronics applications such as active matrix liquid crystal displays (AMLCD) [1][2][3], wearable sensors [4,5] and passive tags RFID (radio frequency identification) [6][7][8]. Nowadays, TFT technology is based on amorphous silicon (a-Si), polysilicon (poly-Si) and IGZO (indium-gallium-zinc oxide) semiconductors. The a-Si TFTs offer small electron mobilities (<1 cm 2 /Vs), and thus low switching speed [9]. The other hand, poly-Si TFTs are devices with high performance, but they are fabricated at higher temperatures (500-600 • C) [10][11][12], while IGZO TFTs have moderate mobilities (>10 cm 2 /Vs) and low temperature of fabrication [13]. However, this semiconductor is only used for the fabrication of n-type devices, for p-type is used a different semiconductor, such as SnO [14]. To overcome these limitations, hydrogenated amorphous silicon-germanium (a-SiGe:H) films can be used to fabricate TFTs at low temperature of deposition (<300 • C) by PECVD technique. This allows carrier mobilities higher than 1 cm 2 /Vs caused by the incorporation of germanium and hydrogen atoms. In addition, a-SiGe:H TFTs can have an ambipolar behavior, allowing their operation into either as n-or p-type [15]. In order to design a-SiGe:H TFTs for specific applications, it is necessary to predict the behavior of their drain currents. Shur et al. [16] reported a physical drain current model for n-and p-channels hydrogenated amorphous silicon and polysilicon staggered bottom-gate top-contact TFTs. This model was implemented into an AIM-SPICE circuit simulator. However, it is adapted from MOSFET model and it does not include semiconductor density of states. Chen et al. [17] reported an analytical drain current model for both triode and saturation region of operation for a-Si:H TFTs considering semiconductor density of states and an effective temperature approach. However, this model registered a high error between measurements and modeled results. Liu et al. [18] presented an analytical drain current model for a-Si:H TFTs based on surface potential, which was compared with numerical simulations considering free and localized carrier densities into the semiconductor. Colalongo et al. [19] designed an analytical drain current model for a-Si:H TFTs based on deep and tail states in both semiconductors, which describe the behavior at sub-threshold and above-threshold mode of operation.
In this paper, we develop an analytical drain current model for a-SiGe:H TFTs that considers free and localized charges into semiconductor and its characteristic temperatures, which can represent the behavior at sub-threshold and above-threshold regions of operation without using fitting parameters. In addition, 2D numerical simulations using finite element method of the output and transfer characteristics of bottom-gate top-contact coplanar a-SiGe:H TFTs are reported. The results of our analytical drain current model agree well with respect to those of the numerical simulations. In Section 2, electrostatic analysis and derivation of expressions for electric field and drain current are explained. In Section 3, comparison of our model and simulation results are presented. Finally, the conclusions are discussed in Section 4.

Density of Estates of Amorphous Semiconductors
The density of states, g(E), of an amorphous semiconductor thin film consists of four energy bands over the bandgap: two tail bands and two deep bands. Tail bands consist of a donor-like valence band, g TA (E), and an acceptor-like conduction band, g TD (E). On the other hand, deep bands are composed of a donor-like valence band, g GA (E), and an acceptor-like conduction band, g GD (E), which are represented as follow, [20]: where E is the trap energy, E C and E v are the conduction and valence band energy, respectively; WTA (kT tail ) and WTD (kT tail ) are acceptor and donor characteristic decay energy for the tail band, respectively; WGA (kT deep ) and WGD (kT deep ) are acceptor and donor characteristic decay energy for the deep band, respectively; NTA, NTD, NDA and NDD are the conduction and valence band edge intercept densities for the tail and deep band, respectively.

Analytical Drain Current Model
Figure 1a shows a schematic cross section of a n-type coplanar bottom-gate top-contact a-SiGe:H TFT with SiO 2 as gate insulator and a-Ge:H n+ layers for drain and source extensions. In this Figure, T ox and T sc are the gate oxide and semiconductor thickness, respectively. Figure 1b depicts the diagram of energy band for MIS (metal-insulator-semiconductor) region for this device working under Electronics 2020, 9, 1016 3 of 12 accumulation regimen, when a positive gate potential (V G ) is applied. For this Figure, E C and E V are energy levels of conduction and valence bands, respectively; E Fm , and E Fn are the Fermi energy levels for metal, intrinsic and n-type semiconductor, respectively; ϕ S and ϕ CH (x) are surface and channel potential; and ϕ F0 (x) is the potential between E c and E Fn .

Derivation of Electric Field
Taking into account the free and localized electron concentration for an n-type amorphous semiconductor, the Poisson's equation in one dimension, along the x direction, can be expressed as: where q is the electron charge, ϕ(x) is the potential across the active layer, ρ(x) is the total charge density, ɛsc is the permittivity constant of the semiconductor layer, nfree(x), ndeep(x) and ntail(x) are the free, deep and tail electron concentrations, respectively. These concentrations for a-SiGe:H layer can be expressed as:

Derivation of Electric Field
Taking into account the free and localized electron concentration for an n-type amorphous semiconductor, the Poisson's equation in one dimension, along the x direction, can be expressed as: where q is the electron charge, φ(x) is the potential across the active layer, ρ(x) is the total charge density, sc is the permittivity constant of the semiconductor layer, n free (x), n deep (x) and n tail (x) are the free, deep and tail electron concentrations, respectively. These concentrations for a-SiGe:H layer can be expressed as: where N C is the free electron concentration, V CH is the potential along the channel, q is the electron charge, k is Boltzmann constant, T is a reference temperature and g is the degeneration factor which depends of the temperature ratio (T/T eff ) as exponential expression. In order to simplify the analysis, an effective carrier concentration (N eff ) instead of free, deep or tail carrier concentrations (N free , N deep or N tail ), which are computed with Equations (8), (10) or (12) equations, respectively, is proposed. In the same way, an effective characteristic temperature (T eff ) instead of free, deep or tail temperature (T free , T deep or T tail ), respectively, is used.
To derivate the electric filed as function of electrostatic potential, it is necessary to solve the following Poisson´s equation: By employing the next expression to change the integration variable, from x to φ(x): By integrating both sides in Equation (14) and applying the square root, we have: By substituting Equation (13) into Equation (15) and applying the boundary conditions from x = 0 (φ S (x)) to x = T SC (φ B (x)), the electric field as a function of φ(x) is expressed as: where n eff is the effective electron density, T eff is the effective characteristic temperature, ε sc is the semiconductor permittivity, φ S (x) is the electrostatic potential in the gate insulator/semiconductor interface , φ B (x) is the electrostatic potential in the semiconductor/passivation layer interface, which is neglected because is close to zero. Thus, the transversal electric field through an amorphous semiconductor, at x direction, is given by:

Derivation of Drain to Source Current in Subthreshold Region, I DS_sub
In the subthreshold region operation of a-SiGe:H TFT, that is gate to source voltage, V GS , is less than threshold voltage, V TH , but larger than the flat band voltage, V FB , (V FB < V GS < V TH ), most of the carriers are free electrons, because of deep and tail localized carriers are trapped into semiconductor defects. Therefore, it is necessary to apply a larger V GS in order to generate a higher transversal electric field to the active layer to set free those charges. In addition, for this semiconductor (see Table 1) the localized energy characteristics (kT tail and kT deep ) are higher than the free energy characteristic (kT free ). Thus, ρ(x) for an a-SiGe:H TFT at subthreshold operation can be obtained by: Electronics 2020, 9, 1016 5 of 12 In order to derive the drain to source current in subthreshold regimen, I DS_sub , is employed the gradual channel approximation expression, which is given by: where W is the channel width of TFT, σ n (x) is the n-type channel conductivity of a-SiGe:H, E(ϕ(x)) is the electric field dependent of potential at x direction, and µ 0 is the carrier mobility of semiconductor. The final expression for drain to source current at region of subthreshold for an a-SiGe:H TFT is computing solving Equation (19), step-by-step at Appendix A, considering N eff = N free and T eff = T free , as follows: with:

Derivation of Drain Current at Above Threshold Region, I DS_abv
Above threshold region of a-SiGe:H TFT operation, that is when V GS > V TH , free and localized charges are taken in to account due to the applied gate to source voltage generates a strong transversal electric field to the active layer which produces an accumulation of both carriers in the semiconductor/gate-insulator interface. However, in this semiconductor n deep (x) << n tail (x). Thus, we obtained the following equation: Poisson's equation is applied as follows: Electronics 2020, 9, 1016 6 of 12 By using the gradual channel approximation Equation (19) and the procedure in Appendix A, taking into account free and tail localized charges along the semiconductor, we can derive the drain to source current for the above threshold region, I DS_abv , as follows:

Total Analytical Drain Current Model
The final unified analytical drain current model for a-SiGe:H TFTs takies into account the sub-threshold and above-threshold regions, which it considers the density of states of such amorphous semiconductor and free electrons, is estimated by adding I DS_sub and I DS_abv with the following expression:

Results and Discussion
In order to compare the results of our analytical drain current model, we develop 2D numerical simulations for bottom-gate top-contact coplanar a-SiGe:H TFTs using Silvaco TCAD software through Atlas and Devedit tools (Santa Clara, CA, USA) [21]. These simulation tools use finite element method to perform the electrostatic analysis. Figure 2 shows a schematic view of the cross-section of the proposed device and its main geometrical parameters. The substrate is silicon oxide with a thickness T SUB = 200 nm. The gate and drain/source electrodes are aluminum with thickness T G and T D/S of 100 nm, respectively. SiO 2 is used as gate insulator with a thickness T OX = 80 nm. An overlap length between gate and drain/source electrodes of L OV = 10 nm is used. Then, a thin film of a-SiGe:H as active layer or semiconductor with a thickness T SC = 100 nm and a length channel L = 75 µm is used. The width of the active layer W = 30 µm is used for calculation. A layer of high doped germanium as drain/source extension region with thickness T EXT = 40 nm and length L D/S = 2 µm are employed to get a good ohmic contact with the semiconductor. Finally, SiN 4 as passivating dielectric layer with T PASS = 200 nm is used in order to reduce broken bonds of the a-SiGe:H surface and carriers recombination.

Total Analytical Drain Current Model
The final unified analytical drain current model for a-SiGe:H TFTs takies into account the subthreshold and above-threshold regions, which it considers the density of states of such amorphous semiconductor and free electrons, is estimated by adding IDS_sub and IDS_abv with the following expression:

Results and Discussion
In order to compare the results of our analytical drain current model, we develop 2D numerical simulations for bottom-gate top-contact coplanar a-SiGe:H TFTs using Silvaco TCAD software through Atlas and Devedit tools (Santa Clara, CA, USA) [21]. These simulation tools use finite element method to perform the electrostatic analysis. Figure 2 shows a schematic view of the crosssection of the proposed device and its main geometrical parameters. The substrate is silicon oxide with a thickness TSUB = 200 nm. The gate and drain/source electrodes are aluminum with thickness TG and TD/S of 100 nm, respectively. SiO2 is used as gate insulator with a thickness TOX = 80 nm. An overlap length between gate and drain/source electrodes of LOV = 10 nm is used. Then, a thin film of a-SiGe:H as active layer or semiconductor with a thickness TSC = 100 nm and a length channel L = 75 µm is used. The width of the active layer W = 30 µm is used for calculation. A layer of high doped germanium as drain/source extension region with thickness TEXT = 40 nm and length LD/S = 2 µm are employed to get a good ohmic contact with the semiconductor. Finally, SiN4 as passivating dielectric layer with TPASS = 200 nm is used in order to reduce broken bonds of the a-SiGe:H surface and carriers recombination.  The parameters for semiconductor and gate insulator layers considered in the numerical simulations and analytical drain current model are listed in Table 1. Furthermore, defects parameters that define the density of states of a-SiGe:H layer used for simulations and modeling are shown in Table 2. Some of those values were taken from [20].  Figure 3 shows the comparison of modeled (lines) and simulated (symbols) characteristics I DS vs V DS for V GS = 1, 2, 3 and 4 Volts. It can be seen that the model is able to represent the behavior of the drain current at the sub-threshold and above-threshold regions for each curve corresponding to different V GS values with a small error for the whole V DS range.  Figure 4 shows the absolute and average error between IDS characteristics modeled and simulated presented, which is computed with Equation (33). It can be seen; the maximum absolute error occurs for the IDS curve when VDS = 0.5 V and VGS = 4 V which is 9.8%. In addition, the average absolute error for all values of VGS is 5%, approximately.  Figure 4 shows the absolute and average error between I DS characteristics modeled and simulated presented, which is computed with Equation (33). It can be seen; the maximum absolute error occurs for the I DS curve when V DS = 0.5 V and V GS = 4 V which is 9.8%. In addition, the average absolute error for all values of V GS is 5%, approximately.  Figure 4 shows the absolute and average error between IDS characteristics modeled and simulated presented, which is computed with Equation (33). It can be seen; the maximum absolute error occurs for the IDS curve when VDS = 0.5 V and VGS = 4 V which is 9.8%. In addition, the average absolute error for all values of VGS is 5%, approximately.

Conclusions
In this paper, was developed an analytical drain current model for a-SiGe:H TFTs that shows very good agreement with 2D numerical simulations which were used to validate it. The model considers free and localized charges into a-SiGe:H layer, characteristic temperature dependence and is able to work for sub-and above-threshold region of operation with a small absolute average error. In this sense, the proposed model has implication for development and prediction of electrical

Conclusions
In this paper, was developed an analytical drain current model for a-SiGe:H TFTs that shows very good agreement with 2D numerical simulations which were used to validate it. The model considers free and localized charges into a-SiGe:H layer, characteristic temperature dependence and is able to work for sub-and above-threshold region of operation with a small absolute average error. In this sense, the proposed model has implication for development and prediction of electrical performance of TFTs at low frequencies based on amorphous semiconductors, such as a-SiGe:H, which is requested for analysis and design of circuits for large area and flexible electronic systems. Future work will include the fabrication and characterization of a-SiGe:H thin films transistors devices. Funding: This research was funded by project PRODEP "Modelado y Desarrollo de Microsensores CMOS-MEMS para la detección de diabetes".

Appendix A
By substituting Equations (7) and (17) in Equation (19), we obtain: Then, by integrating for φ(x) and evaluating from φ(x = 0) = Φ S to φ(x = T SC ) = Φ B , we obtain: where : However, the second term inside of Equation (A2) is neglected (φ B = 0). Thus, Equation (A2) can be rearranged as follows: By integrating Equation (A5) with respect to y at both sides, and by evaluating the boundary conditions from y = 0 (source voltage, V S ) to y = L (drain voltage, V D ) in order to solve V CH(y) , we obtain: Then, by applying the Gauss's Law along the Metal-Oxide-Semiconductor structure, and by substituting the electric field expression, we obtain: where C OX is the capacitance due to gate oxide per area unit, φ s is surface potential at the oxide/semiconductor interface and V FB is flat band voltage.
sc N e f f kT e f f C ox By rewriting Equation (A8) as function of V CH (y), we obtain: By differentiating V CH (y) for φ S (y) from Equation (A7), we obtain: By rewriting Equation (A13), we obtain: where: C e f f = 2kT e f f B e f f (A17)