A Reconfigurable Analog Baseband Circuitry for LFMCW RADAR Receivers in 130-nm SiGe BiCMOS Process

A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.


Introduction
The booming smart portable devices has led to an imperative demand for multi-standard compatibility on mobile/wireless receivers in recent years, such as Global System for Mobile Communications (GSM), Bluetooth, Global Position System (GPS), Wideband Code Division Multiple Access (W-CDMA), Wireless Local Area Network (WLAN), Long Term Evolution (LTE), and so on. Therefore, industrial corporations and academic institutions have released diverse integrated solutions with different RF front-ends covering various bands and sharing one analog baseband, which performs channel selectivity and gains tunability functions after down conversion mixers. In general, the analog baseband should be optimized for multi-purpose application scenarios with a fundamental tradeoff integrated solutions with different RF front-ends covering various bands and sharing one analog baseband, which performs channel selectivity and gains tunability functions after down conversion mixers. In general, the analog baseband should be optimized for multi-purpose application scenarios with a fundamental tradeoff between noise figure, linearity, power consumption, channel selection and gain/bandwidth/filter order programmability in itself. The fundamental principle, which prevents the analog baseband from obtaining universality, is that: the noise figure is determined by the preceding stages while the linearity is decided by the backward ones. The major challenges to be settled in the design of flexible analog circuits are the following: a. performance programmability; b. specification compatibility; c. energy scalability; d. complexity and cost.
In direct conversion receivers, typical analog baseband consists of a programmable gain amplifier (PGA) and a low-pass filter (LPF) as depicted in Figure 1. Thus, two general architectures emerge with their respective pros and cons: the LPF-first topology is more suitable for the receivers with high linearity/medium noise figure, while the PGA-first topology fits the receivers more with low noise figure/medium linearity. The authors of [1] proposed a fourth-order Chebyshev active-R-C LPF + PGA + fourth-order Chebyshev active-R-C LPF topology, which emphasized the filtering capability. The authors of [2] proposed a third-order LPF + PGA topology. The authors of [3] proposed a discrete time IIR LPF + active FIR topology, which focuses on the discrete time filtering function. The authors of [4][5][6][7][8] proposed a typical LPF + VGA topology, with tunable cut-off frequency/noise/gain performances. The authors of [9] proposed a fourth-order merged closed-loop analog baseband topology, which integrates the channel selection and gain programmability in one merged PGA/LPF biquad. However, the closed-loop topology is intrinsically power-hungry and frequency limited since the operational amplifier should exhibit gain bandwidth product (GBW) several times larger than closed-loop bandwidth requirement [10,11]. Therefore, there is no unique optimum solution, but a myriad solution with a variety proportional to the number of input specifications, with the expectation of sufficiently fine gain resolution, bandwidth programmability, excellent noise/linearity performance, acceptable chip footprint and low power consumption.
In this paper, a highly reconfigurable open-loop analog baseband prototype chip is proposed with optimized noise/linearity/power consumption performance, and digitally programmable bandwidth/gain/filter order for integrated linear FMCW radar receivers. Power consumption minimization is achieved via two methods: a. open-loop analog baseband chain with feasible compensations for process/voltage/temperature (PVT) variations; b. allocating channel selection/signal amplification specifications to every block across the baseband chain, and adjusting current consumed for diverse gain levels. The noise figure is maintained low with the help of a low noise figure/high gain pre-amplifier, while the linearity of the Gm-C LPF is guaranteed with a novel connection style without any rise in power consumption. Moreover, a novel high linearity buffer amplifier with active peaking is designed for testing purposes. The proposed prototype is fabricated in a 130 nm SiGe BiCMOS process, and the experimental results demonstrate the practicality of the proposal.
The rest of the paper is organized as follows. After the introduction given in Section 1, Section 2 derives the LFMCW radar requirement on the overall analog baseband chain, Section 3 illustrates the detailed implementation schematic, Section 4 demonstrates the experimental results and Section 5 concludes the paper.

Analog Baseband Architecture for LFMCW Radar
LFMCW radars are expansively used in automotive anti-collision, security check, imaging and presence detection applications when high range resolution is required in localization/tracking. A variety of modulation schemes are available, with a transmitted frequency signal acting as sine wave, sawtooth wave, triangular wave or square wave. In a sawtooth wave-based FMCW radar, the achievable range and velocity resolution depend on the transmitting signal bandwidth BW and the linear chirp period T m , as seen in Figure 2. The range resolution ∆r, which refers to the minimum detectable separation distance of two targets of equal cross sections that can be differentiated as distinct targets, is proportional to c/2/BW, where c is the velocity of light. This means that a large modulation bandwidth BW is needed for a fine range resolution. For a transceiver operating at 94 GHz, a modulation period in the order of 100 µs, a modulation bandwidth of higher than 500 MHz, the analog baseband bandwidth can be calculated as follows: where BW is the transmitting signal bandwidth, T m is the linear chirp period, K is the FMCW slope, f o is the center operating frequency, v is the target velocity, c is the velocity of light, r is the distance from source to target, f IF,static is the analog baseband frequency for static target ranging, and f IF,moving is the analog baseband frequency for moving target ranging. After setting BW = 500 MHz, T m = 100 µs, c = 3 × 10 8 m/s, r = 6~7 km into Equations (1)-(4), we can calculate the f IF,static to be 20~23.4 MHz. When doppler radar effect is taken into account, the IF frequency should cover the range of 18~25 MHz. Therefore, for generally used LPFs, the analog baseband −3 dB bandwidth is set to be 18/19/20/21/22/23/24/25 MHz, with 3-bit digital control words to cover the frequency shift coming from potential target moving.

Analog Baseband Architecture for LFMCW Radar
LFMCW radars are expansively used in automotive anti-collision, security check, imaging and presence detection applications when high range resolution is required in localization/tracking. A variety of modulation schemes are available, with a transmitted frequency signal acting as sine wave, sawtooth wave, triangular wave or square wave. In a sawtooth wave-based FMCW radar, the achievable range and velocity resolution depend on the transmitting signal bandwidth BW and the linear chirp period Tm, as seen in Figure 2. The range resolution Δr, which refers to the minimum detectable separation distance of two targets of equal cross sections that can be differentiated as distinct targets, is proportional to c/2/BW, where c is the velocity of light. This means that a large modulation bandwidth BW is needed for a fine range resolution. For a transceiver operating at 94 GHz, a modulation period in the order of 100 µs, a modulation bandwidth of higher than 500 MHz, the analog baseband bandwidth can be calculated as follows: where BW is the transmitting signal bandwidth, Tm is the linear chirp period, K is the FMCW slope, fo is the center operating frequency, v is the target velocity, c is the velocity of light, r is the distance from source to target, fIF,static is the analog baseband frequency for static target ranging, and fIF,moving is the analog baseband frequency for moving target ranging. After setting BW = 500 MHz, Tm = 100 µs, c = 3 × 10 8 m/s, r = 6~7 km into Equations (1)-(4), we can calculate the fIF,static to be 20~23.4 MHz. When doppler radar effect is taken into account, the IF frequency should cover the range of 18~25 MHz. Therefore, for generally used LPFs, the analog baseband −3 dB bandwidth is set to be 18/19/20/21/22/23/24/25 MHz, with 3-bit digital control words to cover the frequency shift coming from potential target moving.
T ra n sm it S ign a l R eceived S ign al F M C W P erio d In this LFMCW radar, direct conversion architecture is adopted to evade image rejection problems and, thus, the analog baseband consumes lower power, since its bandwidth is half of that in low-IF/super heterodyne receivers. Paradoxically, typical dynamic range of direct conversion receiver is lower than that of low-IF/super heterodyne ones. Therefore, novel dynamic range optimization techniques are investigated in two directions: lower noise figure and higher linearity. Merged PGA/LPF biquads in [9] simultaneously optimized the two specifications owing to a closed-loop topology with switchable filter orders. However, this kind of topology becomes power-hungry when the frequency rises, and its gain resolution depends on the resistor/capacitor array size. In other words, the merged analog baseband compromises power consumption and chip size for noise/linearity/gain/filter order reconfigurability. What is more, the noise figure of PGA/LPF is normally higher than 25 dB, which deteriorates the receiver noise specification, since the front-end (including a low noise amplifier and a mixer) of the linear FMCW receiver usually possesses a gain of lower than 20 dB. Thus, architectures in Figure 1 and the merged analog baseband in [9] cannot satisfy the noise/linearity/power consumption requirement concurrently.
This paper makes a modification to the LPF-first/PGA-first topology by adding a programmable gain pre-amplifier with course gain tuning ability to its front, as depicted in Figure 3, which forms a PGA-LPF-PGA topology. In detail, this topology includes a pre-amplifier for noise optimization and course gain tuning, a folded Gilbert variable gain amplifier (VGA) with a symmetrical exponential voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable G m -C LPF, a DC offset cancellation (DCOC) circuit, two fixed gain amplifiers (FGA) with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. DC coupling is utilized on account of spectrally efficient modulation schemes [12]. The architecture in Figure 3 is open-loop and thus, frequency/power scalable. From the LPF-first viewpoint, this topology optimizes noise figure with another PGA ahead. From the PGA-first viewpoint, this topology ameliorates linearity with another PGA behind. Nonetheless, a heavy signal-processing burden is placed upon the LPF and its high linearity is a prerequisite.
In search of a high linearity LPF, researchers proposed numerous high linearity structures, such as active-R-C and class-AB G m -C ones [6,[13][14][15][16]. Linearity is refined with a compromise of power consumption and operation frequency, which is fundamentally determined by the closed-loop LPF topology and the complex routings inside the trans-conductor. Thus, high linearity open loop LPFs, which theoretically decouples the linearity from power consumption, are urgently needed.  In this LFMCW radar, direct conversion architecture is adopted to evade image rejection problems and, thus, the analog baseband consumes lower power, since its bandwidth is half of that in low-IF/super heterodyne receivers. Paradoxically, typical dynamic range of direct conversion receiver is lower than that of low-IF/super heterodyne ones. Therefore, novel dynamic range optimization techniques are investigated in two directions: lower noise figure and higher linearity. Merged PGA/LPF biquads in [9] simultaneously optimized the two specifications owing to a closedloop topology with switchable filter orders. However, this kind of topology becomes power-hungry when the frequency rises, and its gain resolution depends on the resistor/capacitor array size. In other words, the merged analog baseband compromises power consumption and chip size for noise/linearity/gain/filter order reconfigurability. What is more, the noise figure of PGA/LPF is normally higher than 25 dB, which deteriorates the receiver noise specification, since the front-end (including a low noise amplifier and a mixer) of the linear FMCW receiver usually possesses a gain of lower than 20 dB. Thus, architectures in Figure 1 and the merged analog baseband in [9] cannot satisfy the noise/linearity/power consumption requirement concurrently.
This paper makes a modification to the LPF-first/PGA-first topology by adding a programmable gain pre-amplifier with course gain tuning ability to its front, as depicted in Figure 3, which forms a PGA-LPF-PGA topology. In detail, this topology includes a pre-amplifier for noise optimization and course gain tuning, a folded Gilbert variable gain amplifier (VGA) with a symmetrical exponential voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C LPF, a DC offset cancellation (DCOC) circuit, two fixed gain amplifiers (FGA) with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. DC coupling is utilized on account of spectrally efficient modulation schemes [12]. The architecture in Figure 3 is open-loop and thus, frequency/power scalable. From the LPF-first viewpoint, this topology optimizes noise figure with another PGA ahead. From the PGA-first viewpoint, this topology ameliorates linearity with another PGA behind. Nonetheless, a heavy signal-processing burden is placed upon the LPF and its high linearity is a prerequisite.
In search of a high linearity LPF, researchers proposed numerous high linearity structures, such as active-R-C and class-AB Gm-C ones [6,[13][14][15][16]. Linearity is refined with a compromise of power consumption and operation frequency, which is fundamentally determined by the closed-loop LPF topology and the complex routings inside the trans-conductor. Thus, high linearity open loop LPFs, which theoretically decouples the linearity from power consumption, are urgently needed.

Detailed Circuit Designs
In this section, detailed sub-block circuit schematics and their respective design procedures are presented.

Detailed Circuit Designs
In this section, detailed sub-block circuit schematics and their respective design procedures are presented.

Pre-Amplifier
As the first stage in the analog baseband chain, the pre-amplifier should exhibit low noise figure and simultaneously sufficient gain to suppress the noise contribution from the following stages to the overall analog baseband circuitry. Moreover, the gain programmability serves as a critical safeguard for large variations in input signal strength and a powerful certification of automatic gain control (AGC). Class-A/AB amplifiers are usually selected with common mode stability circuitry, with a high noise figure attributed to circuit complexities. Although the three fundamental gain programmability schemes, including current switching/bleeding, load resistor switching and source degeneration, are reported as depicted in Figure 4, their merits and demerits are evident: a. current switching method dynamically varies gain by correspondingly adjusting biasing current. High gain typically corresponds to high linearity/low noise figure/high dynamic range, while low gain is in accordance with low linearity/high noise figure/low dynamic range. Therefore, the dynamic range fluctuates over all gain settings; b. load resistor switching assumes a gain switching scheme with little noise figure variations, since the noise contribution from load resistors is restrained by amplifying the transistors. However, the load resistor switching has a detrimental effect on voltage swings and thus, the voltage swing varies with gain; c. the source degeneration scheme monitors the transconductance of main amplification transistors with a corresponding adjustment in noise figure and linearity. When the gain is high, a weak source degeneration is formed with a low noise figure and a medium linearity. When the gain is low, a strong source degeneration is constructed with a high linearity and a medium noise figure. Nevertheless, the current consumption is stable over all gain settings, which deteriorates the power dissipation self-adaptability. The advantages and disadvantages of them are listed in Table 1.

Pre-Amplifier
As the first stage in the analog baseband chain, the pre-amplifier should exhibit low noise figure and simultaneously sufficient gain to suppress the noise contribution from the following stages to the overall analog baseband circuitry. Moreover, the gain programmability serves as a critical safeguard for large variations in input signal strength and a powerful certification of automatic gain control (AGC). Class-A/AB amplifiers are usually selected with common mode stability circuitry, with a high noise figure attributed to circuit complexities. Although the three fundamental gain programmability schemes, including current switching/bleeding, load resistor switching and source degeneration, are reported as depicted in Figure 4, their merits and demerits are evident: a. current switching method dynamically varies gain by correspondingly adjusting biasing current. High gain typically corresponds to high linearity/low noise figure/high dynamic range, while low gain is in accordance with low linearity/high noise figure/low dynamic range. Therefore, the dynamic range fluctuates over all gain settings; b. load resistor switching assumes a gain switching scheme with little noise figure variations, since the noise contribution from load resistors is restrained by amplifying the transistors. However, the load resistor switching has a detrimental effect on voltage swings and thus, the voltage swing varies with gain; c. the source degeneration scheme monitors the transconductance of main amplification transistors with a corresponding adjustment in noise figure and linearity. When the gain is high, a weak source degeneration is formed with a low noise figure and a medium linearity. When the gain is low, a strong source degeneration is constructed with a high linearity and a medium noise figure. Nevertheless, the current consumption is stable over all gain settings, which deteriorates the power dissipation self-adaptability. The advantages and disadvantages of them are listed in Table 1.  Forasmuch as the low noise and course gain tuning requirements, this paper utilizes a limiting amplifier structure with no common mode control [12] and adds 3-bit gain programmability with a switched resistor source degeneration technique, which is depicted in Figure 5. The common mode stabilization is left to following stages with noise figure optimization. Although the issue of stable current consumption still exists as one in source degeneration structure, the limiting amplifier structure avoids the common mode control circuitry, which is usually power-hungry. In short, the power consumption problem is partially circumvented. The component sizes and post-simulated specifications at TT 27 • are given in Table 2.  Forasmuch as the low noise and course gain tuning requirements, this paper utilizes a limiting amplifier structure with no common mode control [12] and adds 3-bit gain programmability with a switched resistor source degeneration technique, which is depicted in Figure 5. The common mode stabilization is left to following stages with noise figure optimization. Although the issue of stable current consumption still exists as one in source degeneration structure, the limiting amplifier structure avoids the common mode control circuitry, which is usually power-hungry. In short, the power consumption problem is partially circumvented. The component sizes and post-simulated specifications at TT 27° are given in Table 2.

VGA and Symmetrical Exponential Voltage Generator
Intrinsically, Gilbert structure can be regarded as a hybrid combination of current switching and load resistor switching since the current is simultaneously split between load resistors R 1 /R 2 and tail currents I tail1 /I tail2 in Figure 6. Therefore, an optimization regarding the pros and cons of the two schemes can be conducted for the sake of dynamic range expansion. In essence, the Gilbert cell adjusts its gain via the current switching technique, but the difference between current switching and Gilbert cell lies in the current feeding through load resistors. In the Gilbert cell, the current through load resistors is stable across all gain settings, which circumvents dynamic range fluctuations encountered in current switching technique. Thus, the Gilbert structure is utilized for its wide gain tuning range and robustness, while a dB-linear voltage generator with an R-2R DAC is utilized for digital gain tuning precision. The variable gain amplifier cell with its control voltage generator is depicted in Figure 6. Moreover, dual supply voltages 1.2 V/1.8 V are adopted for power optimization. Specifically, 1.8 V feeds VGA, while 1.2 V feeds the voltage exponential generator.
In the VGA cell, assuming the transistors are working in strong saturation regions and square law model is adopted, the linear relationship between the input and output of VGA is expressed as follows: where µ n is the low field mobility coefficient, C ox is the unit area oxide capacitance and W/L is the aspect ratio of the transistors. The voltage gain is in a dB-linear relationship with the input voltage as expressed in Equation (5). The component sizes and post-simulated specifications at TT 27 • are given in Table 3.

DAC
R-2R DAC is employed to facilitate the digital control of the dB-linear voltage generator and to ensure fine gain resolution, with a single pole double throw (SPDT) based gain tuning scheme, switchable between analog continuous tuning and digital step tuning [8]. A 10-bit R-2R DAC with its output buffer is depicted in Figure 7. Two respective voltage ports named Vrefh and Vrefl refer to the high and low reference voltages, which are in accordance with Figure 3. The unit resistor value is selected to be 14.95 Kohms, with accuracy in mind.
In the design of a 10-bit DAC, component accuracy, symmetry of differential components and environmental consistency are three crucial points in layout floor planning. Thus, dummy cells near key components, shielded signal path optimization should be iterated several times. In addition, the output buffer should possess rail to rail output swing and acceptable drive capability. Therefore, the folded cascode topology depicted in Figure 7b is chosen with a linearization technique.

DAC
R-2R DAC is employed to facilitate the digital control of the dB-linear voltage generator and to ensure fine gain resolution, with a single pole double throw (SPDT) based gain tuning scheme, switchable between analog continuous tuning and digital step tuning [8]. A 10-bit R-2R DAC with its output buffer is depicted in Figure 7. Two respective voltage ports named V refh and V refl refer to the high and low reference voltages, which are in accordance with Figure 3. The unit resistor value is selected to be 14.95 Kohms, with accuracy in mind.
In the design of a 10-bit DAC, component accuracy, symmetry of differential components and environmental consistency are three crucial points in layout floor planning. Thus, dummy cells near key components, shielded signal path optimization should be iterated several times. In addition, the output buffer should possess rail to rail output swing and acceptable drive capability. Therefore, the folded cascode topology depicted in Figure 7b is chosen with a linearization technique.
In the static simulation of the whole DAC, the full voltage range is 1.2 V, the INL is 0.17 LSB and the DNL is 0.34 LSB. In dynamic simulations, a sampling frequency of 1 MHz, with a sinusoidal input signal of 0.4961 MHz, is chosen and the effective number of bits (ENOB) is higher than 9.88 bits.
The component sizes and post-simulated specifications at TT 27 • are given in Table 4. In the static simulation of the whole DAC, the full voltage range is 1.2 V, the INL is 0.17 LSB and the DNL is 0.34 LSB. In dynamic simulations, a sampling frequency of 1 MHz, with a sinusoidal input signal of 0.4961 MHz, is chosen and the effective number of bits (ENOB) is higher than 9.88 bits.
The component sizes and post-simulated specifications at TT 27° are given in Table 4.

Level Shifter
In between VGA and LPF, a level shifter is inserted for the sake of common mode voltage stabilization, since its preceding pre-amplifier and VGA do not provide this kind of function. The level shifter is depicted in Figure 8, and a typical one-stage amplification with two-stage DC voltage feedback is used. R 2 /C 1 performs the gain/phase margin compensation and snake resistors layout are utilized with large MOS-capacitors. The component sizes and post-simulated specifications at TT 27 • are given in Table 5.

Level Shifter
In between VGA and LPF, a level shifter is inserted for the sake of common mode voltage stabilization, since its preceding pre-amplifier and VGA do not provide this kind of function. The level shifter is depicted in Figure 8, and a typical one-stage amplification with two-stage DC voltage feedback is used. R2/C1 performs the gain/phase margin compensation and snake resistors layout are utilized with large MOS-capacitors. The component sizes and post-simulated specifications at TT 27° are given in Table 5.

Programmable G m -C LPF
G m -C filters are well known for their open loop and frequency scalable characteristics. In theory, the G m -C topology with simplicity, modularity and programmability would be the perfect choice for high frequency continuous-time filter designs. However, the mediocre linearity specification limits its potential use in analog baseband chain of direct conversion receivers. Therefore, linearity improvement techniques are pursued in two aspects: a. the transconductor cell [5][6][7][8]; b. the filter architecture. Most relevant work focuses on the former one with an emphasis on class AB transconductors. Nonetheless, class-AB transconductors are inherently power-hungry and possess a medium noise figure [10]. In addition, its common mode feedforward and feedback circuitry needs special care in common mode analysis, and its layout and routing are complex [6,13]. Moreover, previously reported linearity enhancement techniques in class-A transconductors are categorized into five groups: a. source degeneration; b. cross coupled transistors; c. load switching; d. current bleeding; e. local g m -boosting feedback. None of them offers an architectural approach to promote linearity. This paper proposes a modified 3rd order Butterworth LPF with 3-bit logarithmic bandwidth tuning ability, as depicted in Figure 9.
Traditional third-order Butterworth LPF is depicted in Figure 9a, with a bandwidth tuning technique. From the bi-quad cascading viewpoint, an exchange of V 2+ and V 1− is conducted as in Figure 9b. The voltage-current relationships of the two bi-quads are derived as follows.
Therefore, the output current remains the same for the two bi-quads. A quick glimpse of the right half of Figure 9b reveals that for a typical transconductor cell (G m in Figure 9), the differential input signal swing is replaced by common mode input signal swing. Since the major nonlinearity is attributed to the transconductor itself, this change circumvents the differential signal processing vulnerability, with a new burden on common mode signal processing ability. On one hand, differential input signals experience the same voltage-to-current transformation in transconductor cells. Therefore, the frequency response remains the same after the modifications. On the other hand, common mode input signals experience different path, which results in larger variations in common mode signal swing. In short, the modification method essentially linearizes the LPF with an increase in common mode voltage variation, and a corresponding reduction in the differential mode voltage swing in the meantime. Therefore, the common mode rejection ratio and common mode feedback circuit should be designed iteratively with an emphasis on common mode stability. It should be cautious to use traditional sharing technique of common mode feedback circuit.
Afterwards, similar input exchange procedures are executed in Figure 9a and, thus, Figure 9c demonstrates the modified Gm-C LPF with its individual transconductor cell and switched capacitor array. Simulation results show that the output third-order interception point (OIP3) of a third-order Butterworth LPF is elevated from around 4.5 dBm to 14.5 dBm. Electronics 2020, 9,   As to the bandwidth tuning aspect, typical binary capacitor array cannot set the bandwidth linearly when the operation frequency range covers several decades. For typical LPF, the −3 dB bandwidth is determined as follows.  As to the bandwidth tuning aspect, typical binary capacitor array cannot set the bandwidth linearly when the operation frequency range covers several decades. For typical LPF, the −3 dB bandwidth is determined as follows.
where f o is the −3 dB cutoff frequency, L is the inductance value and C is the capacitance value. Thus, C is in a square root relation with f o . For example, in order to achieve 2% step size in bandwidth over two decades of the frequency range, a 6-bit resolution in bandwidth programmability is required (2 6 > 1/2%), while higher than 12-bit resolution is a prerequisite in capacitor array (100 2 /98 2 requires another resolution of 6-bit for the lower than 0.025 capacitance resolution), which wastes the majority of the chip area. Therefore, the logarithmic bandwidth tuning technique is also adopted in the LPF design, as depicted in Figure 9c, since the logarithmic equation shrinks the capacitor array into small scale. The individual capacitor value can be calculated with a Taylor series expansion method, as follows: where C unit is the unit capacitor and b 2 /b 1 /b 0 are three digital control bits. This logarithmic tuning theoretically relaxes the passive array resolution by half. The post-simulated specifications of a third-order Butterworth LPF is listed in Table 6.

DC Offset Cancellation (DCOC)
Unlike the typical DC stabilization circuitry used in level shifter and LPF, an f T doubler based DC offset cancellation circuit is proposed for the sake of reduced parasitics, as depicted in Figure 10. The DC extraction LPF is given in Figure 3, which is composed of R 1 and C 1 . C 1 is an area efficient MOS-capacitor. The −3 dB corner frequency of the LPF is around 100 kHz. The component sizes and post-simulated specifications at TT 27 • are given in Table 7.
Electronics 2020, 9, x FOR PEER REVIEW 13 of 19 two decades of the frequency range, a 6-bit resolution in bandwidth programmability is required (2 6 > 1/2%), while higher than 12-bit resolution is a prerequisite in capacitor array (100 2 /98 2 requires another resolution of 6-bit for the lower than 0.025 capacitance resolution), which wastes the majority of the chip area. Therefore, the logarithmic bandwidth tuning technique is also adopted in the LPF design, as depicted in Figure 9c, since the logarithmic equation shrinks the capacitor array into small scale. The individual capacitor value can be calculated with a Taylor series expansion method, as follows: where Cunit is the unit capacitor and b2/b1/b0 are three digital control bits. This logarithmic tuning theoretically relaxes the passive array resolution by half. The post-simulated specifications of a thirdorder Butterworth LPF is listed in Table 6. Table 6. Post simulated performance specifications of a third-order Butterworth LPF.

DC Offset Cancellation (DCOC)
Unlike the typical DC stabilization circuitry used in level shifter and LPF, an fT doubler based DC offset cancellation circuit is proposed for the sake of reduced parasitics, as depicted in Figure 10. The DC extraction LPF is given in Figure 3, which is composed of R1 and C1. C1 is an area efficient MOS-capacitor. The −3 dB corner frequency of the LPF is around 100 kHz. The component sizes and post-simulated specifications at TT 27° are given in Table 7.   Two FGAs are used to meet the gain compensation and stability requirement. Figure 11 illustrates one FGA with three gain stages with an active inductive peaking technique, which is formed by M7/M8. It should be pointed out that active peaking in itself affects frequency dependent group delay and, thus, data dependent jitter is worsened more or less. Therefore, group delay should be carefully verified in the FGA design. The component sizes and post-simulated specifications at TT 27 • are given in Table 8.

Fixed Gain Amplifier (FGA)
Two FGAs are used to meet the gain compensation and stability requirement. Figure 11 illustrates one FGA with three gain stages with an active inductive peaking technique, which is formed by M7/M8. It should be pointed out that active peaking in itself affects frequency dependent group delay and, thus, data dependent jitter is worsened more or less. Therefore, group delay should be carefully verified in the FGA design. The component sizes and post-simulated specifications at TT 27° are given in Table 8.

Buffer Amplifier
A low power transconductance-linearized buffer with bandwidth extension technique is proposed, as depicted in Figure 12. An internal negative feedback is formed by M1/M3/M5/M6, and the output voltage can be expressed as follows.

Buffer Amplifier
A low power transconductance-linearized buffer with bandwidth extension technique is proposed, as depicted in Figure 12. An internal negative feedback is formed by M1/M3/M5/M6, and the output voltage can be expressed as follows.
In summary, the presented buffer has triple fold advantages. Firstly, the transconductance linearization technique involves cross-coupling CMOS pairs. Secondly, the output load is lowered with the source follower topology and, hence, the bandwidth is broadened compared to common source based ones. Thirdly, the voltage headroom is V gs,PMOS + 2 × V ds,NMOS , which suits low voltage buffer design well. The component sizes and post-simulated specifications at TT 27 • are given in Table 9.
Electronics 2020, 9, If we assume the ideal output resistance is infinite and neglect parasitic capacitance of transistors, we can derive a simplified version of Equation (10), which intrinsically demonstrates a voltage buffer feature.
In summary, the presented buffer has triple fold advantages. Firstly, the transconductance linearization technique involves cross-coupling CMOS pairs. Secondly, the output load is lowered with the source follower topology and, hence, the bandwidth is broadened compared to common source based ones. Thirdly, the voltage headroom is Vgs,PMOS + 2 × Vds,NMOS, which suits low voltage buffer design well. The component sizes and post-simulated specifications at TT 27° are given in Table 9.

Experimental Results
The proposed analog baseband is implemented in a 130 nm SiGe BiCMOS technology. The chip photograph is given in Figure 13 and its chip area is 1400 µm × 800 µm, with its core area of 1000 µm × 300 µm. The extra area occupied is used for on-chip measurement and on-chip decoupling capacitors. The voltage gain tuning range is −30~35 dB, when the DAC reference voltage V refh and V refl are set between 0.6 V and 0.95 V as depicted in Figure 14. However, when a dB-linear voltage gain curve is required, V refh and V refl should be set as 0.68 V and 0.9 V, which reduces the voltage gain range to −28~32 dB. The measured gain resolution is better than 0.1 dB, which is in accordance with the post-simulated DAC performance. The programmable cut-off frequency response is measured as depicted in Figure 15, when voltage gain is around −7 dB. The biasing current of trans-conductors is adjusted to match the LPF bandwidth requirement. Therefore, the −3 dB cutoff frequency via programmable capacitor array is listed as 17~24 MHz, with a 1 MHz step. The filter order is configured for different requirements in Figure 16 with orders of three and six. The chip adopted a dual power supply of 1.2 V/1.8 V for optimized power consumption. The power consumption is 2.9 mA@1.8 V and 0.3~2.5 mA@1.2 V, which is divided to sub-blocks as depicted in Figure 17. The measured OP1 dB is around −3 dBm when the input signal is at 20 MHz. A general comparison with related works is summarized in Table 10. The proposed analog baseband exhibits comparable specifications with previous works, while the voltage gain resolution is far better, thanks to the DAC and exponential voltage generator. In future research, the minimum bit of the LPF will be modified to obtain more desirable results.

Experimental Results
The proposed analog baseband is implemented in a 130 nm SiGe BiCMOS technology. The chip photograph is given in Figure 13 and its chip area is 1400 µm × 800 µm, with its core area of 1000 µm × 300 µm. The extra area occupied is used for on-chip measurement and on-chip decoupling capacitors. The voltage gain tuning range is −30~35 dB, when the DAC reference voltage Vrefh and Vrefl are set between 0.6 V and 0.95 V as depicted in Figure 14. However, when a dB-linear voltage gain curve is required, Vrefh and Vrefl should be set as 0.68 V and 0.9 V, which reduces the voltage gain range to −28~32 dB. The measured gain resolution is better than 0.1 dB, which is in accordance with the post-simulated DAC performance. The programmable cut-off frequency response is measured as depicted in Figure 15, when voltage gain is around −7 dB. The biasing current of trans-conductors is adjusted to match the LPF bandwidth requirement. Therefore, the −3 dB cutoff frequency via programmable capacitor array is listed as 17~24 MHz, with a 1 MHz step. The filter order is configured for different requirements in Figure 16 with orders of three and six. The chip adopted a dual power supply of 1.2 V/1.8 V for optimized power consumption. The power consumption is 2.9 mA@1.8 V and 0.3~2.5 mA@1.2 V, which is divided to sub-blocks as depicted in Figure 17. The measured OP1 dB is around −3 dBm when the input signal is at 20 MHz. A general comparison with related works is summarized in Table 10. The proposed analog baseband exhibits comparable specifications with previous works, while the voltage gain resolution is far better, thanks to the DAC and exponential voltage generator. In future research, the minimum bit of the LPF will be modified to obtain more desirable results.

Experimental Results
The proposed analog baseband is implemented in a 130 nm SiGe BiCMOS technology. The chip photograph is given in Figure 13 and its chip area is 1400 µm × 800 µm, with its core area of 1000 µm × 300 µm. The extra area occupied is used for on-chip measurement and on-chip decoupling capacitors. The voltage gain tuning range is −30~35 dB, when the DAC reference voltage Vrefh and Vrefl are set between 0.6 V and 0.95 V as depicted in Figure 14. However, when a dB-linear voltage gain curve is required, Vrefh and Vrefl should be set as 0.68 V and 0.9 V, which reduces the voltage gain range to −28~32 dB. The measured gain resolution is better than 0.1 dB, which is in accordance with the post-simulated DAC performance. The programmable cut-off frequency response is measured as depicted in Figure 15, when voltage gain is around −7 dB. The biasing current of trans-conductors is adjusted to match the LPF bandwidth requirement. Therefore, the −3 dB cutoff frequency via programmable capacitor array is listed as 17~24 MHz, with a 1 MHz step. The filter order is configured for different requirements in Figure 16 with orders of three and six. The chip adopted a dual power supply of 1.2 V/1.8 V for optimized power consumption. The power consumption is 2.9 mA@1.8 V and 0.3~2.5 mA@1.2 V, which is divided to sub-blocks as depicted in Figure 17. The measured OP1 dB is around −3 dBm when the input signal is at 20 MHz. A general comparison with related works is summarized in Table 10. The proposed analog baseband exhibits comparable specifications with previous works, while the voltage gain resolution is far better, thanks to the DAC and exponential voltage generator. In future research, the minimum bit of the LPF will be modified to obtain more desirable results.   a Core area is 0.3 mm 2 and total chip area is 1.12 mm 2 ; b The author did not give the port impedance levels; c The noise figure is post-simulated at maximum gain; d The filter order is programmable and thus this parameter varies across filter order settings.  a Core area is 0.3 mm 2 and total chip area is 1.12 mm 2 ; b The author did not give the port impedance levels; c The noise figure is post-simulated at maximum gain; d The filter order is programmable and thus this parameter varies across filter order settings.

Conclusions
This paper proposed a reconfigurable analog baseband circuitry for LFMCW RADAR receivers with bandwidth/gain/filter order programmability. Measurement results are acceptable and match the simulations well. Although the majority of performance specifications are acceptable with respect to recent references, there is still no clear distinction between the closed loop analog baseband and an open loop one in the facet of power consumption. However, when operating frequency rises, closed loop architecture will soon evaporate, owing to the upper limit of GBW and power consumption. In future research, the reconfigurable analog baseband should be updated with a bandpass filter or complex filter, in order to reduce the in-band integrated noise for better receiver detection specification.

Conclusions
This paper proposed a reconfigurable analog baseband circuitry for LFMCW RADAR receivers with bandwidth/gain/filter order programmability. Measurement results are acceptable and match the simulations well. Although the majority of performance specifications are acceptable with respect to recent references, there is still no clear distinction between the closed loop analog baseband and an open loop one in the facet of power consumption. However, when operating frequency rises, closed loop architecture will soon evaporate, owing to the upper limit of GBW and power consumption. In future research, the reconfigurable analog baseband should be updated with a bandpass filter or complex filter, in order to reduce the in-band integrated noise for better receiver detection specification.