A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.


Introduction
The low noise amplifier (LNA) is considered a crucial component in wireless communication systems. Since it is the first stage of the receiver, the LNA design characteristics (such as high-gain, low-noise figure, linearity) condition the reception performance of the whole system [1]. However, it is a fact that in radio frequency (RF) design, it is very difficult to meet all the specifications simultaneously because of the large number of constraints to be satisfied. Broadly, there are two approaches to designing an LNA, depending on the critical specification to be addressed: looking for the maximum gain or the minimum noise figure. The traditional high frequency MOS design flow is tedious, time-consuming, and usually relies on the designer's experience. This supposes conducting an iterative process, generally assisted by a CAD simulation tool, until the design specifications are satisfied.
In order to characterize these kinds of circuits, the scattering parameters (or S-parameters) are the most likely symbolic approach, where signal power considerations are more easily quantified and measured than currents and voltages. These parameters reflect the power gain and the input and output matching of the circuit. However, there is no model that relates S-parameters to the physical characteristics of the transistors, which represent the main variables to consider in order to address the aforementioned LNA design constraints [2].
On one hand, the advanced compact MOSFET (ACM) model [3] is a powerful tool for hand calculations with MOS transistors. Unlike most of the available models, it presents simple and precise equations together with a small but meaningful number of physics parameters. On the other hand, the relationship between the transistor's transconductance (gm) and the drain current (I D ), also known

Design Approach: Linking the Circuit S-Parameters with the gm/I D Transistor Ratio
The gm/I D ratio is a resourceful tool for performing transistor sizing and biasing. As mentioned earlier, this method exploits the fact that transconductance and drain currents vary with the gate width. From the design perspective, the gm/I D ratio is the parameter that tells the designer how much current is needed to obtain a particular gm, prescribed by the gain-bandwidth constraint. Figure 1 shows the well-known I D versus V gs characteristics of a NMOS transistor. From this curve, one can obtain the gm/I D ratio as follows: Electronics 2020, 9,785 3 of 17 Electronics 2020, 9, x FOR PEER REVIEW 3 of 17 The above equation is plotted in Figure 2. From Equation (1), it can be noted that the gm/ID ratio does not depend on the gate width but on the inversion region where the transistors are biased. As seen in Figure 2, the gm/ID is at its maximum when the Vgs is at its minimum. This is because the gm/ID is inversely proportional to the gate-voltage-overdrive Vov = Vgs -Vth. Based on the value of Vgs, the MOS transistor can operate in three different regions: weak, moderate, and strong inversion. In the first region, the value of the gm/ID is at its maximum, while its minimum is in strong inversion. Conversely, the current is at its maximum in strong inversion and at its minimum in weak inversion, as shown in Figure 1.
A more useful plot is shown in Figure 3, in which the gm/ID ratio is plotted as a function of the normalized current iD, which is given by: In this way, its position along the horizontal axis of the gm/ID curve becomes independent of the threshold voltage Vth. For a given ID and a desired operation region (gm/ID), the transistor size is easily obtained as the following: At the same time, through the curve in Figure 2, one can obtain the needed Vgs biasing voltage. In short, the gm/ID, iD, and Vgs form a trinity that defines the transistor working conditions. Knowing the value of one of these values and using the curves in Figures 2 and 3, the values of the other two can be inferred.  The above equation is plotted in Figure 2. From Equation (1), it can be noted that the gm/I D ratio does not depend on the gate width but on the inversion region where the transistors are biased. As seen in Figure 2, the gm/I D is at its maximum when the V gs is at its minimum. This is because the gm/I D is inversely proportional to the gate-voltage-overdrive V ov = V gs -V th . Based on the value of V gs , the MOS transistor can operate in three different regions: weak, moderate, and strong inversion. In the first region, the value of the gm/I D is at its maximum, while its minimum is in strong inversion. Conversely, the current is at its maximum in strong inversion and at its minimum in weak inversion, as shown in Figure 1.
A more useful plot is shown in Figure 3, in which the gm/I D ratio is plotted as a function of the normalized current i D , which is given by: In this way, its position along the horizontal axis of the gm/I D curve becomes independent of the threshold voltage V th . For a given I D and a desired operation region (gm/I D ), the transistor size is easily obtained as the following: At the same time, through the curve in Figure 2, one can obtain the needed V gs biasing voltage. In short, the gm/I D , i D , and V gs form a trinity that defines the transistor working conditions. Knowing the value of one of these values and using the curves in Figures 2 and 3, the values of the other two can be inferred.  The above equation is plotted in Figure 2. From Equation (1), it can be noted that the gm/ID ratio does not depend on the gate width but on the inversion region where the transistors are biased. As seen in Figure 2, the gm/ID is at its maximum when the Vgs is at its minimum. This is because the gm/ID is inversely proportional to the gate-voltage-overdrive Vov = Vgs -Vth. Based on the value of Vgs, the MOS transistor can operate in three different regions: weak, moderate, and strong inversion. In the first region, the value of the gm/ID is at its maximum, while its minimum is in strong inversion. Conversely, the current is at its maximum in strong inversion and at its minimum in weak inversion, as shown in Figure 1.
A more useful plot is shown in Figure 3, in which the gm/ID ratio is plotted as a function of the normalized current iD, which is given by: In this way, its position along the horizontal axis of the gm/ID curve becomes independent of the threshold voltage Vth. For a given ID and a desired operation region (gm/ID), the transistor size is easily obtained as the following: At the same time, through the curve in Figure 2, one can obtain the needed Vgs biasing voltage. In short, the gm/ID, iD, and Vgs form a trinity that defines the transistor working conditions. Knowing the value of one of these values and using the curves in Figures 2 and 3, the values of the other two can be inferred.   The key idea is to use the gm/ID ratio as a free parameter that enables sweeping the transistor through all modes of operation in order to explore the design space. Broadly, there are two working methodologies: experimental or analytical. The first derives the gm/ID ratio from experimental ID = f(Vgs) characteristics. The currents are acquired from measurements carried out on real transistors whose W and L are known a priori. Another option is to obtain the ID from simulations with advanced models, such as BSIM or PSP4, as these allow the reconstruction of drain currents that are very close to real ones. The last option is also known as the semi-empirical gm/ID sizing method.
This LNA design approach is based on the analysis of the variation in the circuit S-parameters as a function of the physical transistor (gm/ID). Thus, it is necessary to link the transistor geometry and biasing conditions (expressed in terms of the gm/ID ratio) with the design specifications given in terms of the S-parameters. In this direction, the expressions given by the ACM model for the full characterization of the MOS transistors [3,8] can be used. Figure 4 shows the RF small signal equivalent circuit for an MOS transistor with intrinsic and extrinsic components depicted separately. From the ACM model, it is possible to obtain the expressions of the intrinsic capacitances in terms of the gm/ID transistor ratio. The latter are synthetized in Table 1, while Table 2 reports the expressions for the extrinsic capacitances. In these expressions, W is the channel width, L is the channel length, Φt is the thermal voltage, COX is the gate capacitance density, COV is the overlap capacitance density, and Cj' is the junction capacitance density. Table 3 shows the definition of the gate and bulk transconductance (gm and gmb, respectively) and the drain conductance (gds), which can also be expressed as a function of the MOS gm/ID. In this case, n is the subthreshold slope factor, and VA represents the early voltage. The key idea is to use the gm/I D ratio as a free parameter that enables sweeping the transistor through all modes of operation in order to explore the design space. Broadly, there are two working methodologies: experimental or analytical. The first derives the gm/I D ratio from experimental I D = f(V gs ) characteristics. The currents are acquired from measurements carried out on real transistors whose W and L are known a priori. Another option is to obtain the I D from simulations with advanced models, such as BSIM or PSP4, as these allow the reconstruction of drain currents that are very close to real ones. The last option is also known as the semi-empirical gm/I D sizing method.
This LNA design approach is based on the analysis of the variation in the circuit S-parameters as a function of the physical transistor (gm/I D ). Thus, it is necessary to link the transistor geometry and biasing conditions (expressed in terms of the gm/I D ratio) with the design specifications given in terms of the S-parameters. In this direction, the expressions given by the ACM model for the full characterization of the MOS transistors [3,8] can be used. Figure 4 shows the RF small signal equivalent circuit for an MOS transistor with intrinsic and extrinsic components depicted separately.  The key idea is to use the gm/ID ratio as a free parameter that enables sweeping the transistor through all modes of operation in order to explore the design space. Broadly, there are two working methodologies: experimental or analytical. The first derives the gm/ID ratio from experimental ID = f(Vgs) characteristics. The currents are acquired from measurements carried out on real transistors whose W and L are known a priori. Another option is to obtain the ID from simulations with advanced models, such as BSIM or PSP4, as these allow the reconstruction of drain currents that are very close to real ones. The last option is also known as the semi-empirical gm/ID sizing method.
This LNA design approach is based on the analysis of the variation in the circuit S-parameters as a function of the physical transistor (gm/ID). Thus, it is necessary to link the transistor geometry and biasing conditions (expressed in terms of the gm/ID ratio) with the design specifications given in terms of the S-parameters. In this direction, the expressions given by the ACM model for the full characterization of the MOS transistors [3,8] can be used. Figure 4 shows the RF small signal equivalent circuit for an MOS transistor with intrinsic and extrinsic components depicted separately. From the ACM model, it is possible to obtain the expressions of the intrinsic capacitances in terms of the gm/ID transistor ratio. The latter are synthetized in Table 1, while Table 2 reports the expressions for the extrinsic capacitances. In these expressions, W is the channel width, L is the channel length, Φt is the thermal voltage, COX is the gate capacitance density, COV is the overlap capacitance density, and Cj' is the junction capacitance density. Table 3 shows the definition of the gate and bulk transconductance (gm and gmb, respectively) and the drain conductance (gds), which can also be expressed as a function of the MOS gm/ID. In this case, n is the subthreshold slope factor, and VA represents the early voltage. From the ACM model, it is possible to obtain the expressions of the intrinsic capacitances in terms of the gm/I D transistor ratio. The latter are synthetized in Table 1, while Table 2 reports the expressions for the extrinsic capacitances. In these expressions, W is the channel width, L is the channel length, Φ t is the thermal voltage, C OX is the gate capacitance density, C OV is the overlap capacitance density, and C j ' is the junction capacitance density. Table 3 shows the definition of the gate and bulk transconductance (gm and gmb, respectively) and the drain conductance (gds), which can also be expressed as a function of the MOS gm/I D . In this case, n is the subthreshold slope factor, and V A represents the early voltage.  Table 2. MOS extrinsic capacitance expressions.

Parameter Expression
Extrinsic gate-drain overlap capacitance Table 3. MOS transconductance and conductance expressions.

Parameter Expression
Gate small signal transconductance When the transistor modelled in Figure 4 is part of a more complex circuit arrangement with other external components, this arrangement can be represented as a quadrupole (shown in Figure 5), and its admittance parameters (Y ij ) can be derived from the complete circuit using a two-port model. Then, each Y-matrix element will be a function of the aforementioned MOS elements (capacitances, conductance, and transconductance) and the involved external components. These admittance parameters are used as an intermediate step for obtaining the S-parameters.

Parameter Expression
Gate small signal transconductance = = ( ) Output small signal conductance = = When the transistor modelled in Figure 4 is part of a more complex circuit arrangement with other external components, this arrangement can be represented as a quadrupole (shown in Figure  5), and its admittance parameters (Yij) can be derived from the complete circuit using a two-port model. Then, each Y-matrix element will be a function of the aforementioned MOS elements (capacitances, conductance, and transconductance) and the involved external components. These admittance parameters are used as an intermediate step for obtaining the S-parameters. Finally, the S-parameters can be easily obtained from the admittance matrix [31], as follows: Electronics 2020, 9, 785 6 of 17 Figure 6 summarizes the procedure for obtaining the circuit's S-parameters as a function of the physical properties of the transistor. A validation of these relations can be found in [29], where this strategy was applied to the characterization of an LNA common source stage, and concurrent simulations with the ACM and IBM BSIM4 MOS 65 nm models were performed.
Electronics 2020, 9, x FOR PEER REVIEW 6 of 17 Figure 6 summarizes the procedure for obtaining the circuit's S-parameters as a function of the physical properties of the transistor. A validation of these relations can be found in [29], where this strategy was applied to the characterization of an LNA common source stage, and concurrent simulations with the ACM and IBM BSIM4 MOS 65 nm models were performed.

LNA Design Methodology
The selected LNA configuration, shown in Figure 7, corresponds to a cascode topology. It consists of the transistors, M1 and M2, in common source and common gate configuration, respectively, which fix the gain of the LNA. C1 and L1 set a stabilization network that ensures that the amplifier is unconditionally stable. The C2-L2 pair is part of the input-matching network, setting the input impedance to 50 ohms at the working frequency. C3-L3 is the output-matching network. The rest of the circuit (M3, R1, and R2) form the bias network that sets the LNA bias conditions (Vgs and ID at M1). It is worth noting that the analysis of the admittance matrix must be individually performed for each LNA stage. This is because the transistor configuration is different at each stage and, consequently, the involved elements of the small signal transistor model will also be different for each of them. As mentioned above, the presence of external components must be considered. This work focuses on the amplifier core, consisting of the common source (CS) stage and the common gate (CG) stage, highlighted in Figure 7. For the sake of clarity, the general expressions of the Y-matrix

LNA Design Methodology
The selected LNA configuration, shown in Figure 7, corresponds to a cascode topology. It consists of the transistors, M1 and M2, in common source and common gate configuration, respectively, which fix the gain of the LNA. C1 and L1 set a stabilization network that ensures that the amplifier is unconditionally stable. The C2-L2 pair is part of the input-matching network, setting the input impedance to 50 ohms at the working frequency. C3-L3 is the output-matching network. The rest of the circuit (M3, R1, and R2) form the bias network that sets the LNA bias conditions (Vgs and I D at M1).
Electronics 2020, 9, x FOR PEER REVIEW 6 of 17 Figure 6 summarizes the procedure for obtaining the circuit's S-parameters as a function of the physical properties of the transistor. A validation of these relations can be found in [29], where this strategy was applied to the characterization of an LNA common source stage, and concurrent simulations with the ACM and IBM BSIM4 MOS 65 nm models were performed.

LNA Design Methodology
The selected LNA configuration, shown in Figure 7, corresponds to a cascode topology. It consists of the transistors, M1 and M2, in common source and common gate configuration, respectively, which fix the gain of the LNA. C1 and L1 set a stabilization network that ensures that the amplifier is unconditionally stable. The C2-L2 pair is part of the input-matching network, setting the input impedance to 50 ohms at the working frequency. C3-L3 is the output-matching network. The rest of the circuit (M3, R1, and R2) form the bias network that sets the LNA bias conditions (Vgs and ID at M1). It is worth noting that the analysis of the admittance matrix must be individually performed for each LNA stage. This is because the transistor configuration is different at each stage and, consequently, the involved elements of the small signal transistor model will also be different for each of them. As mentioned above, the presence of external components must be considered. This work focuses on the amplifier core, consisting of the common source (CS) stage and the common gate (CG) stage, highlighted in Figure 7. For the sake of clarity, the general expressions of the Y-matrix It is worth noting that the analysis of the admittance matrix must be individually performed for each LNA stage. This is because the transistor configuration is different at each stage and, consequently, the involved elements of the small signal transistor model will also be different for each of them. As mentioned above, the presence of external components must be considered. This work focuses on the amplifier core, consisting of the common source (CS) stage and the common gate (CG) stage, highlighted in Figure 7. For the sake of clarity, the general expressions of the Y-matrix elements for the CS stage as a function of the MOS physical characteristics and bias conditions are presented (Equations (8) to (11)). The admittance matrix for the CG stage can be ascertained in the same way.
In these expressions, Y SB is the MOS source-bulk admittance, and C gs represents the gate-source capacitance. Both are defined as follows: The procedure, depicted in Figure 8, starts with the analysis of each LNA's stage. For each, the variation of the transistor drain current (I D ) and transconductance (gm) with its size and bias voltage (Vgs for CS and Vgg for CG) is determined by simulation. With both functions, the MOS gm/I D ratio is then established. Using the relationships found in the second section (Tables 1-3 and Equations (4) to (7)), the S-parameters are characterized as a function of the transistor's gm/I D and size.
Electronics 2020, 9, x FOR PEER REVIEW 7 of 17 elements for the CS stage as a function of the MOS physical characteristics and bias conditions are presented (Equations (8) to (11)). The admittance matrix for the CG stage can be ascertained in the same way.
In these expressions, YSB is the MOS source-bulk admittance, and Cgs represents the gate-source capacitance. Both are defined as follows: The procedure, depicted in Figure 8, starts with the analysis of each LNA's stage. For each, the variation of the transistor drain current (ID) and transconductance (gm) with its size and bias voltage (Vgs for CS and Vgg for CG) is determined by simulation. With both functions, the MOS gm/ID ratio is then established. Using the relationships found in the second section (Tables 1-3 and Equations (4) to (7)), the S-parameters are characterized as a function of the transistor's gm/ID and size. The gain, noise figure, and stability factor of each stage can be easily derived from its Sparameters, allowing the design space exploration of such parameters as a function of the gm/ID ratio and the transistor geometry. In this way, the designer sizes the MOS transistor by simply selecting the gain and noise figure points that best fit with the stage requirement and by verifying stability with the K factor.
The S-matrix of the whole amplifier can be expressed as the result of the cascade of two quadrupoles (CS and CG stages), each characterized by its individual S-matrix. With this new Smatrix, it should be verified that the amplifier complies with the gain and noise figure specifications. The next subsections provide further details about the complete design procedure. The circuit was characterized in an MOS 65 nm technology for a 2440 MHz operation frequency. Simulations were performed with Microwave Office (MWO)-AWR using the IBM BSIM4 model. The gain, noise figure, and stability factor of each stage can be easily derived from its S-parameters, allowing the design space exploration of such parameters as a function of the gm/I D ratio and the transistor geometry. In this way, the designer sizes the MOS transistor by simply selecting the gain and noise figure points that best fit with the stage requirement and by verifying stability with the K factor.
The S-matrix of the whole amplifier can be expressed as the result of the cascade of two quadrupoles (CS and CG stages), each characterized by its individual S-matrix. With this new S-matrix, it should be verified that the amplifier complies with the gain and noise figure specifications. The next subsections provide further details about the complete design procedure. The circuit was characterized in an MOS 65 nm technology for a 2440 MHz operation frequency. Simulations were performed with Microwave Office (MWO)-AWR using the IBM BSIM4 model.  Figure 9 shows the simulation setup for the common source stage. As stated earlier, the elements C1 and L1 were added to the circuit in order to ensure the stability of the amplifier. The S-parameters are obtained as a function of the gm/I D performing parametric AC simulation by varying the W/L in the range of 1000 and 5750 in steps of 250, and the V gs between 600 and 1075 mV in steps of 25 mV.

Common Source (CS) Stage Characterisation
Electronics 2020, 9, x FOR PEER REVIEW 8 of 17 Figure 9 shows the simulation setup for the common source stage. As stated earlier, the elements C1 and L1 were added to the circuit in order to ensure the stability of the amplifier. The S-parameters are obtained as a function of the gm/ID performing parametric AC simulation by varying the W/L in the range of 1000 and 5750 in steps of 250, and the Vgs between 600 and 1075 mV in steps of 25 mV. The available power gain (GA), defined as the ratio between the available power at the output network (PN) and the available power from the source (PS), is given by the following:

Common Source (CS) Stage Characterisation
In the above equation, S must be zero at the maximum gain. In this condition, the GA depends only on the S-parameters that can be expressed in terms of the transistor gm/ID. Consequently, Equation (14) now becomes: Figure 10a reports the result for the GACS as a function of the gm/ID ratio for different transistor sizes. The maximum GACS is 10.71 dB for a gm/ID of 13.39 V −1 and a W/L ratio of 1000. Similarly, the noise figure for the CS stage is depicted in Figure 10b. The minimum NFCS is 0.9076 dB for a gm/ID of 13.11 V −1 and a W/L ratio of 2000. As can be verified from Figure 10c, the circuit with the stabilization network C1-L1 is unconditionally stable since the K factor is greater than one in all cases. The available power gain (GA), defined as the ratio between the available power at the output network (P N ) and the available power from the source (P S ), is given by the following: In the above equation, Γ S must be zero at the maximum gain. In this condition, the GA depends only on the S-parameters that can be expressed in terms of the transistor gm/I D . Consequently, Equation (14) now becomes:  Figure 10b. The minimum NF CS is 0.9076 dB for a gm/I D of 13.11 V −1 and a W/L ratio of 2000. As can be verified from Figure 10c, the circuit with the stabilization network C1-L1 is unconditionally stable since the K factor is greater than one in all cases.

Common Gate (CG) Stage Characterisation
The same procedure is executed in order to obtain the S-parameters for the common gate configuration (see Figure 11). It should be noted that this configuration does not need extra components to warrant the stability of the circuit. As in the previous case, the simulation was performed varying the W/L between 1000 and 5750 in steps of 250, but the V gg was in the range between 1210 and 1400 mV in steps of 10 mV.

Common gate (CG) Stage Characterisation
The same procedure is executed in order to obtain the S-parameters for the common gate configuration (see Figure 11). It should be noted that this configuration does not need extra components to warrant the stability of the circuit. As in the previous case, the simulation was performed varying the W/L between 1000 and 5750 in steps of 250, but the Vgg was in the range between 1210 and 1400 mV in steps of 10 mV. The GACG expression in terms of the S-parameters and transistor gm/ID is given by the following: The available gain is plotted in Figure 12a for different W/L ratios. The maximum GACG is 9.76 dB for a gm/ID of 12.41 V −1 with a W/L ratio of 3250. Figure 12b shows the NFCG for different W/L ratios. The minimum noise figure of this stage is 1.335 dB for a gm/ID of 13.85 V −1 and a W/L ratio of 5750. Finally, Figure 12c confirms that the configuration is unconditionally stable, with K always greater than one.

Common gate (CG) Stage Characterisation
The same procedure is executed in order to obtain the S-parameters for the common gate configuration (see Figure 11). It should be noted that this configuration does not need extra components to warrant the stability of the circuit. As in the previous case, the simulation was performed varying the W/L between 1000 and 5750 in steps of 250, but the Vgg was in the range between 1210 and 1400 mV in steps of 10 mV. The GACG expression in terms of the S-parameters and transistor gm/ID is given by the following: The available gain is plotted in Figure 12a for different W/L ratios. The maximum GACG is 9.76 dB for a gm/ID of 12.41 V −1 with a W/L ratio of 3250. Figure 12b shows the NFCG for different W/L ratios. The minimum noise figure of this stage is 1.335 dB for a gm/ID of 13.85 V −1 and a W/L ratio of 5750. Finally, Figure 12c confirms that the configuration is unconditionally stable, with K always greater than one. The GA CG expression in terms of the S-parameters and transistor gm/I D is given by the following: The available gain is plotted in Figure 12a for different W/L ratios. The maximum GA CG is 9.76 dB for a gm/I D of 12.41 V −1 with a W/L ratio of 3250. Figure 12b shows the NF CG for different W/L ratios. The minimum noise figure of this stage is 1.335 dB for a gm/I D of 13.85 V −1 and a W/L ratio of 5750. Finally, Figure 12c confirms that the configuration is unconditionally stable, with K always greater than one.
As can be seen from the analysis of each stage, the optimal condition of the MOS transistor geometry and bias diverges depending on the design focus. At this point, the designer should set the transistors' W/L ratios and bias conditions that best fit with the LNA performance specifications and in agreement with the design focus. Both the maximum gain and the minimum noise figure will be analyzed in the next subsection for demonstration purposes. As can be seen from the analysis of each stage, the optimal condition of the MOS transistor geometry and bias diverges depending on the design focus. At this point, the designer should set the transistors' W/L ratios and bias conditions that best fit with the LNA performance specifications and in agreement with the design focus. Both the maximum gain and the minimum noise figure will be analyzed in the next subsection for demonstration purposes.

Cascode Characterisation
Once the CS and CG stages have been individually characterized by their S-matrices, the Sparameters of the cascode topology can be expressed as the result of the cascade connection of two quadrupoles [31]. In this way, each S-matrix element of the cascode stage is given as follows: With the W/L ratios of the above stages fixed according to the design criteria, the cascode Sparameters can be analyzed as a function of the gm/ID of both transistors. The cascode gain parameter, given by Equation (21), can be processed in the same way.
First, the design procedure will be explained in order to obtain the maximum LNA gain. The available power gain area in Figure 13a has been generated for a (W/L)CS ratio of 1000 and a (W/L)CG ratio of 3250, which correspond to the transistor sizes for the maximum gain of each stage. The GACASCODE is presented as a function of the gm/ID of each configuration in order to determine the exact polarization points that set the maximum gain condition.

Cascode Characterisation
Once the CS and CG stages have been individually characterized by their S-matrices, the S-parameters of the cascode topology can be expressed as the result of the cascade connection of two quadrupoles [31]. In this way, each S-matrix element of the cascode stage is given as follows: With the W/L ratios of the above stages fixed according to the design criteria, the cascode S-parameters can be analyzed as a function of the gm/I D of both transistors. The cascode gain parameter, given by Equation (21), can be processed in the same way.
First, the design procedure will be explained in order to obtain the maximum LNA gain. The available power gain area in Figure 13a has been generated for a (W/L) CS ratio of 1000 and a (W/L) CG ratio of 3250, which correspond to the transistor sizes for the maximum gain of each stage. The GA CASCODE is presented as a function of the gm/I D of each configuration in order to determine the exact polarization points that set the maximum gain condition.
If the polarization conditions for the maximum gain in each stage (shown as P1 in Figure 13) are evaluated, the available power gain of the cascode configuration results in 15.55 dB. However, the point of the maximum power gain is 15.69 dB, and corresponds to a (gm/I D ) CS of 10.07 V −1 and a (gm/I D ) CG of 12.12 V −1 (labelled as P2). This small shift in the bias conditions derives from an internal impedance mismatch in the cascode connection of both stages. These new adjusted values will be those used in the next design processes, focusing on the maximum gain constraint. Electronics 2020, 9,  If the polarization conditions for the maximum gain in each stage (shown as P1 in Figure 13) are evaluated, the available power gain of the cascode configuration results in 15.55 dB. However, the point of the maximum power gain is 15.69 dB, and corresponds to a (gm/ID)CS of 10.07 V −1 and a (gm/ID)CG of 12.12 V −1 (labelled as P2). This small shift in the bias conditions derives from an internal impedance mismatch in the cascode connection of both stages. These new adjusted values will be those used in the next design processes, focusing on the maximum gain constraint.
An analysis of the noise figure behavior of the cascode configuration was performed for the above-described conditions, and the results are shown in Figure 13b. This graph is obtained by using the Friis equation [32] for the noise factor: It can be noted that the total noise (FT) depends on the noise of each stage (Fi) and gain of the previous stages (Gi-1…GN-1). For the cascode arrangement, Equation (22) is reduced to the following: An analysis of the noise figure behavior of the cascode configuration was performed for the above-described conditions, and the results are shown in Figure 13b. This graph is obtained by using the Friis equation [32] for the noise factor: It can be noted that the total noise (F T ) depends on the noise of each stage (F i ) and gain of the previous stages (G i−1 . . . G N−1 ). For the cascode arrangement, Equation (22) is reduced to the following: Figure 13c reports the behavior of the stability factor K as a function of the gm/I D of each stage. In the evaluated points (P1 and P2), the cascode configuration is still unconditionally stable for the maximum gain condition.
Conversely, if the design had been approached following the noise criteria, the correct decision would have been to minimize the noise figure at the CS and the CG stages. Using the same procedure as in the previous case, an analysis of the noise behavior of the cascode stage is performed for a (W/L) CS of 2000 and a (W/L) CG ratio of 5750, which correspond to the transistor sizes obtained for the minimum noise figure in the CS and CG stages' characterizations. Figure 14a summarizes the simulation results, showing the NF CASCODE as a function of the gm/I D of each transistor.
In the evaluated points (P1 and P2), the cascode configuration is still unconditionally stable for the maximum gain condition.
Conversely, if the design had been approached following the noise criteria, the correct decision would have been to minimize the noise figure at the CS and the CG stages. Using the same procedure as in the previous case, an analysis of the noise behavior of the cascode stage is performed for a (W/L)CS of 2000 and a (W/L)CG ratio of 5750, which correspond to the transistor sizes obtained for the minimum noise figure in the CS and CG stages' characterizations. Figure 14a summarizes the simulation results, showing the NFCASCODE as a function of the gm/ID of each transistor.
The minimum NFCASCODE is 1.042 dB, found for a (gm/ID)CS of 6.792 V −1 and a (gm/ID)CG of 17.120 V -1 (P2 in Figure 14a). This polarization condition generates an available power gain of 11.02 dB (see P2 in Figure 14b). As in the case of the maximum gain, the minimum noise figure is shifted with respect to the polarization conditions set in the characterization of the individual stages (denoted as P1 in Figure 14) due to the internal impedance mismatch in the The minimum NF CASCODE is 1.042 dB, found for a (gm/I D ) CS of 6.792 V −1 and a (gm/I D ) CG of 17.120 V −1 (P2 in Figure 14a). This polarization condition generates an available power gain of 11.02 dB (see P2 in Figure 14b). As in the case of the maximum gain, the minimum noise figure is shifted with respect to the polarization conditions set in the characterization of the individual stages (denoted as P1 in Figure 14) due to the internal impedance mismatch in the cascode connection. Figure 14c describes how stable the circuit is, depending on the bias condition of each stage. These graphs verify that the stability factor K increases as the noise figure decreases.

Complete LNA Circuit
Once the physical parameters of the cascode amplifier have been established, the LNA design is completed with the input and output matching networks and the bias network sections (see Figure 7). The latter sets the gate-source voltage (V gs ) of the CS transistor, which determines the bias condition of the entire cascode arrangement, while the former allows the LNA to achieve the maximum energy transfer. Only the maximum power gain analysis is taken into consideration at this stage. Table 4 summarizes the MOS physical parameters obtained for the maximum gain condition. Using the gm/I D design methodology, choosing the M3 gm/I D ratio of 10.07 V −1 in order to obtain 700 mV at the M1 gate leads to a W/L of 20 for the bias network transistor. The optimum power gain is obtained from a transistor when Y IN and Y OUT are conjugately matched to Y SOURCE and Y LOAD , respectively. For an unconditionally stable transistor (or in this case, an unstable one that has been stabilized for the conditions reported in Table 4), it is possible to find a simultaneous conjugate match solution yielding an amplifier design for which the input and output ports are perfectly and simultaneously matched to the load and source. This can be accomplished at any frequency for which S-parameters of a stable transistor are available and provides the maximum stable gain (MSG) at such a frequency. In this case, the conjugate impedance values for the MSG were ascertained as (11.39 Ω + i 161.81 Ω) for the input and (22.15 Ω + i 504.23 Ω) for the output.
Both the input and the output matching networks comprise a series capacitor and a parallel inductor. Figure 15 presents Smith's chart used for calculating the values of these elements, starting from the conjugate impedance value for the MSG to reach the real 50 Ω of both the source and the load. The complete LNA schematic circuit, including matching and bias networks, designed for maximum gain condition, is shown in Figure 16.    The simulation results are presented in Figure 17, where the point of the maximum available power gain of 29.71 dB is located at the working frequency (2.44 GHz) with a noise figure of 0.6257 dB and a K factor of 1.228. It is worth noting that the plot shows a significant gain improvement and noise figure decrease with respect to that reported in the analysis of the cascode stage because the output and the input are now perfectly adapted. This can be verified from the values of S11 (−18.15 dB) and S22 (−30.67 dB) obtained from simulation, reported in Figure 18. Since the K factor is still greater than one, the amplifier maintains its unconditionally stable characteristic. The simulation results are presented in Figure 17, where the point of the maximum available power gain of 29.71 dB is located at the working frequency (2.44 GHz) with a noise figure of 0.6257 dB and a K factor of 1.228. It is worth noting that the plot shows a significant gain improvement and noise figure decrease with respect to that reported in the analysis of the cascode stage because the output and the input are now perfectly adapted. This can be verified from the values of S 11 (−18.15 dB) and S 22 (−30.67 dB) obtained from simulation, reported in Figure 18. Since the K factor is still greater than one, the amplifier maintains its unconditionally stable characteristic.

Conclusions
This work describes a methodology for designing a cascode LNA combining the use of the Sparameters and the gm/ID ratio of each involved MOS transistor. The latter is used as a free variable to explore the design space while allowing designers to optimally bias and size the transistors. It is possible to design the circuit for maximum power gain or for the minimum noise figure, but at the same time, a trade-off can easily be achieved between them. The cascode LNA was chosen as a test vehicle for demonstrating the usefulness of this methodology, and it can also be used with most RF circuit topologies for which the use of S-parameters has been reported for verification purposes only. The theoretical background behind this methodology was exposed at the beginning of this paper. The link between scattering parameters and the universal gm/ID ratio of MOS transistors was demonstrated starting with the hybrid ACM model, whose elements depend on the gm/ID of the MOS transistor and using the matrix transformations. However, it is well-known that, especially at high frequencies, S-parameters are more reliably measured than admittance or hybrid parameters. Therefore, looking at more realistic results, designers could directly work with real measured Sparameters as a function of the transistors' gm/ID extracted from a test chip, instead of using handcalculated hybrid parameters and matrix transforms.

Conclusions
This work describes a methodology for designing a cascode LNA combining the use of the S-parameters and the gm/I D ratio of each involved MOS transistor. The latter is used as a free variable to explore the design space while allowing designers to optimally bias and size the transistors. It is possible to design the circuit for maximum power gain or for the minimum noise figure, but at the same time, a trade-off can easily be achieved between them. The cascode LNA was chosen as a test vehicle for demonstrating the usefulness of this methodology, and it can also be used with most RF circuit topologies for which the use of S-parameters has been reported for verification purposes only.
The theoretical background behind this methodology was exposed at the beginning of this paper. The link between scattering parameters and the universal gm/I D ratio of MOS transistors was demonstrated starting with the hybrid ACM model, whose elements depend on the gm/I D of the MOS transistor and using the matrix transformations. However, it is well-known that, especially at high frequencies, S-parameters are more reliably measured than admittance or hybrid parameters. Therefore, looking at more realistic results, designers could directly work with real measured S-parameters as a function of the transistors' gm/I D extracted from a test chip, instead of using hand-calculated hybrid parameters and matrix transforms.