Open-Loop Switched-Capacitor Integrator for Low Voltage Applications

: An architecture of a switched-capacitor integrator that includes a charge bu ﬀ er operating in an open-loop is hereby proposed. As for the switched-capacitor ﬁlters, the gain of the proposed integrator, which is given by the input / output capacitor ratio, ensures desensitization to process, voltage, and temperature variations. The proposed circuit is suitable for low voltage supplies. It enables a signiﬁcant power saving compared to a traditional switched-capacitor integrator. This was demonstrated through an analytical comparison between the proposed integrator and a traditional switched-capacitor integrator. The mathematical results were supported and veriﬁed by simulations performed on a circuit prototype designed in 16 nm ﬁnFET technology with 0.95 V supply. The proposed switched-capacitor integrator consumes 76 µ W, resulting in more than twice the e ﬃ ciency for the traditional closed-loop switched-capacitor ﬁlter as an input voltage equal to 31.25 mV at 7 ns clock period is considered. The comparison of architectures was led among the proposed integrator and the state-of-the-art technology in terms of the ﬁgure of merit.


Introduction
Switched-capacitor filters are used in a variety of applications like sensors interfaces [1], audio applications [2], RF front-ends [3], analog-to-digital converters [4], etc. The high accuracy, comparable to the capacitors mismatch and the ease of reprogramming, makes this topology preferable. Such filters require high-performance operational transconductance amplifiers (OTAs). Using modern IC technologies helps to reach high-frequency operation. However, obtaining high DC-gain becomes more challenging for two main reasons: the low supply voltage of the modern IC technologies that limit the number of stackable devices, generally used to obtain high DC-gain OTAs; the reduced length of the transistors that reduces the output resistances and limits the transistor intrinsic gain. On the other hand, the required high-DC gain is obtainable, increasing the number of gain stages of the OTA at the cost of higher power consumption.
In this paper, an open-loop switched-capacitor filter as a building block for the design of a higher-order switched-capacitor filter is presented. Despite its open-loop architecture, the integrator gain depends on the capacitor ratio whose accuracy is related to the capacitor mismatch as it is usually done in closed-loop switched-capacitor integrators. Furthermore, the proposed switched-capacitor integrator enables low voltage operation and relaxes the power requirement compared to the closed-loop counterpart. The paper is organized as follows: Section 2 starts with the analysis from the conventional switched-capacitor integrator used as a benchmark. Section 3 extends the analysis to the proposed open-loop integrator. Section 4 reports the simulation results and Section 5 concludes the paper.
to the proposed open-loop integrator. Section 4 reports the simulation results and Section 5 concludes the paper. Figure 1 shows the conventional architecture of a switched capacitor integrator. The switching scheme of this architecture is defined by two complementary clock phases, ɸ1 and ɸ2. During ɸ1 phase, the input signal, vs, is sampled with the input capacitor, C1. During ɸ2 phase the charge collected by C1 is transferred to the feedback capacitor C2, assuming an ideal virtual ground at the input of the OTA. The overall transfer function in Z-domain is the following = − · (1) As in many other electronic systems, the feedback in this circuit serves two main functions:

The Closed Loop Switched-Capacitor Integrator
 mitigate the impact of nonlinearities in the OTA;  desensitize the overall transfer function to process, voltage, and temperature (PVT) variations.
The cost of these desirable features is an excessive OTA requirement.

Analysis of the Requirements of the Single Stage OTA
To evaluate the OTA requirements, a single-stage architecture was considered. The linear model of the OTA includes a transconductance gm and an output resistance ro. Figure 2 reports the linear model of the integrator including the model of the OTA. In a switched-capacitor integrator, the input signal, vs, changes suddenly at each clock hit. Therefore, vs. can be assimilated to a step signal whose a maximum amplitude is equal to Vi: The switching scheme of this architecture is defined by two complementary clock phases, φ 1 and φ 2 . During φ 1 phase, the input signal, v s , is sampled with the input capacitor, C 1 . During φ 2 phase the charge collected by C 1 is transferred to the feedback capacitor C 2 , assuming an ideal virtual ground at the input of the OTA. The overall transfer function in Z-domain is the following As in many other electronic systems, the feedback in this circuit serves two main functions: mitigate the impact of nonlinearities in the OTA; desensitize the overall transfer function to process, voltage, and temperature (PVT) variations.
The cost of these desirable features is an excessive OTA requirement.

Analysis of the Requirements of the Single Stage OTA
To evaluate the OTA requirements, a single-stage architecture was considered. The linear model of the OTA includes a transconductance g m and an output resistance r o . Figure 2 reports the linear model of the integrator including the model of the OTA.
Electronics 2020, 9, x FOR PEER REVIEW 2 of 24 to the proposed open-loop integrator. Section 4 reports the simulation results and Section 5 concludes the paper. Figure 1 shows the conventional architecture of a switched capacitor integrator. The switching scheme of this architecture is defined by two complementary clock phases, ɸ1 and ɸ2. During ɸ1 phase, the input signal, vs, is sampled with the input capacitor, C1. During ɸ2 phase the charge collected by C1 is transferred to the feedback capacitor C2, assuming an ideal virtual ground at the input of the OTA. The overall transfer function in Z-domain is the following = − · (1) As in many other electronic systems, the feedback in this circuit serves two main functions:

The Closed Loop Switched-Capacitor Integrator
 mitigate the impact of nonlinearities in the OTA;  desensitize the overall transfer function to process, voltage, and temperature (PVT) variations.
The cost of these desirable features is an excessive OTA requirement.

Analysis of the Requirements of the Single Stage OTA
To evaluate the OTA requirements, a single-stage architecture was considered. The linear model of the OTA includes a transconductance gm and an output resistance ro. Figure 2 reports the linear model of the integrator including the model of the OTA. In a switched-capacitor integrator, the input signal, vs, changes suddenly at each clock hit. Therefore, vs. can be assimilated to a step signal whose a maximum amplitude is equal to Vi: In a switched-capacitor integrator, the input signal, v s , changes suddenly at each clock hit. Therefore, v s can be assimilated to a step signal whose a maximum amplitude is equal to The function v s (t) reported in Equation (2) is transformed in s domain and combined with Equation (3), and then the inverse Laplace Transform is evaluated as follows: where τ p and τ z are time constants calculated as reciprocal of pole and zero of the transfer function, i.e., Assuming A 0 1 + C 1 C 2 , τ p can be approximated as follows: The output voltage v o (0) at t = 0, is defined as: The discontinuity is due to the zero in the transfer function.

Requirements of the Single Stage OTA
A finite gain of the OTA, A 0 , and the non-null time is required for settling introduced errors on the output voltage. The OTA finite gain determines an error in a steady state. This error is called static error, ε stat : On the base of Equations (4) and (5), the static error, ε stat , is calculated as follows: where the last approximation is valid as A 0 1 + C 1 C 2 . The charging process of the feedback capacitance, C 1 , has a finite duration. In the following calculations, it is assumed that the duration of the charging phase is half of the clock period, T CLK . Furthermore, an incomplete settling of the output voltage produces an error, which is called dynamic error, ε dyn , which is defined as follows: By using the expression of v o (t), reported in Equation (5), the dynamic error, ε dyn , is calculated as follows: which can be simplified combining Equation (12) with Equations (6) and (7) that: Figure 3 shows the qualitative behavior of the output voltage. Both static and dynamic errors are highlighted.
Electronics 2020, 9, x FOR PEER REVIEW 4 of 24 On the base of Equations (4) and (5), the static error, εstat, is calculated as follows: where the last approximation is valid as The charging process of the feedback capacitance, C1, has a finite duration. In the following calculations, it is assumed that the duration of the charging phase is half of the clock period, TCLK. Furthermore, an incomplete settling of the output voltage produces an error, which is called dynamic error, εdyn, which is defined as follows: By using the expression of vo(t), reported in Equation (5), the dynamic error, εdyn, is calculated as follows: which can be simplified combining Equation (12) with Equations (6) and (7) that: Figure 3 shows the qualitative behavior of the output voltage. Both static and dynamic errors are highlighted. The overall error, εtot, evalueated on the output voltage, is defined as the difference between the ideal output voltage, C2/C1•Vi, and the output voltage measured at TCLK/2:  The overall error, ε tot , evalueated on the output voltage, is defined as the difference between the ideal output voltage, C 2 /C 1 ·V i , and the output voltage measured at T CLK /2: As Equation (14) shows, ε tot is calculated as the sum of ε stat and ε dyn .

DC-Gain Requirement of the Single-Stage OTA
The overall error must be less than the required accuracy, ξ, which is a parameter related to the application. According to the definition, both ε stat and ε dyn must be positive and smaller than the required accuracy, ξ.
To fulfill the DC-gain requirement, the accuracy of the static error, ε stat , needs to be addressed as follows: Combining Equations (10) and (15), the following is obtained: Then, the following constraint on the DC-gain, A o , is derived: Since the DC-gain, A o , undergoes process, voltage and temperature variations, the sensitivity of where last approximation is valid as A 0 1 + C 1 C 2 .

Transconductance Requirement of the Single Stage OTA
A transconductance constrain is determined through the relation between the accuracy specification and the dynamic error, ε dyn , i.e.: Combining Equations (13) and (19), it is obtained: The approximation contained in Equation (20) is justified as it is assumed that A 0 1 + C 1 C 2 . Combining Equations (7) and (20) the following constraint on g m is set: where the last approximation is valid as 1 1 and τ z T CLK 2 .

Circuit Implementation of the Single Stage OTA
A common circuit solution for the OTA is represented by the telescopic Cascode OTA, shown in Figure 4 [5,6]. As the DC-gain requirement is satisfied and the output signal swing is sufficient, the telescopic Cascode OTA reported in Figure 2 remains the most efficient and simplest OTA solution. Therefore, it was used as a benchmark in this paper.

Circuit Implementation of the Single Stage OTA
A common circuit solution for the OTA is represented by the telescopic Cascode OTA, shown in Figure 4 [5,6]. As the DC-gain requirement is satisfied and the output signal swing is sufficient, the telescopic Cascode OTA reported in Figure 2 remains the most efficient and simplest OTA solution. Therefore, it was used as a benchmark in this paper. The overdrive voltage of M1-M2 input transistors is limited by the available supply voltage, Vdd, and the NMOS transistor threshold, VTHN. Assuming a common mode, Vcm, equal to Vdd/2, by applying Kirchoff's voltage law we obtain: where VGS1 is the gate-source voltage of M1-M2 input transistors, and VDS0 is the drain-source voltage of the M0 bias transistor. The common mode, Vcm, must assure that M1-M2 and the M0 transistors work in the saturation region. Therefore, assuming that all the overdrives of M1-M2 and M0 transistors are equal to Vov, from Equation (23) we derive: Thus: As seen in Equation (25), there is a strict limitation to the design of the overdrive of the input transistors at low supply voltage, which is typical of the modern CMOS IC technologies. For example, in finFET 16 nm technology, Vdd is 0.95 V, and VTHN is 0.275 V, therefore Vov must be less than 100 mV. The overdrive voltage of M 1 -M 2 input transistors is limited by the available supply voltage, V dd , and the NMOS transistor threshold, V THN . Assuming a common mode, V cm , equal to V dd /2, by applying Kirchoff's voltage law we obtain: where V GS1 is the gate-source voltage of M 1 -M 2 input transistors, and V DS0 is the drain-source voltage of the M 0 bias transistor. The common mode, V cm , must assure that M 1 -M 2 and the M 0 transistors work in the saturation region. Therefore, assuming that all the overdrives of M 1 -M 2 and M 0 transistors are equal to V ov , from Equation (23) we derive: Thus: Electronics 2020, 9, 762 7 of 24 As seen in Equation (25), there is a strict limitation to the design of the overdrive of the input transistors at low supply voltage, which is typical of the modern CMOS IC technologies. For example, in finFET 16 nm technology, V dd is 0.95 V, and V THN is 0.275 V, therefore V ov must be less than 100 mV.

Small Signal Analysis of the Single-Stage OTA
The transconductance g m of the linear model of Figure 2 corresponds to the transconductance g m1 of M 1 -M 2 input transistors. The bias current, I B , of the OTA is defined by the settling requirements, which mainly depends on M 1 -M 2 input transistors.
The output resistance r o of the linear model of Figure 2 is calculated as follows: where g m3 and g m5 are the transconductances of M 3 and M 5 transistors, respectively, and r o1 , r o3 , and r o5 are the output resistances of M 1 , M 2 , and M 3 transistors, respectively. The last approximation in Equation (24) is valid assuming g m3 g m5 , r o3 r o5, and r o1 r o7 . In practice, the output resistance of M 1 -M 2 transistors, r o1 , is boosted by the intrinsic gain of transistor M 3 , g m3 ·r o3 . The voltage gain, A 0 , can be calculated as follows: Rearranging Equation (27), we obtain: where V A3 , V A1 , V ov3 , and V ov1 are the early and the overdrive voltages of M 3 and M 1 transistors, respectively. As derived in Equation (28), the margins to increase the voltage gain A o are limited. A possibility to increment the voltage gain consists of reducing V ov3 and V ov1 . M 3 and M 1 transistors are then pushed to work in the subthreshold region, where the transconductance depends only on the bias current, while the transistor overdrives approach their inferior limit of about 50 mV [7]. Therefore, V ov1 and V ov3 have a strict range of variability between 50 mV and 100 mV. V A3 and V A1 can be increased by augmenting the length of M 3 and M 1 . This solution degrades the frequency performance of the OTA since larger transistors introduce bigger parasitic capacitances. Moreover, every IC fabrication process has an intrinsic limit to the maximum allowable transistor length, which is lower and lower as the technology is scaled. For example, in FinFET 16 nm, the maximum allowable transistor length is 240 nm. If the DC-gain requirement is not reachable by the telescopic Cascode OTA, it is necessary to modify the OTA architecture. An increment of r o and, consequently, A o is obtained by using a regulated Cascode OTA [8] or adding an output stage [9]. Both previous solutions imply a significant increase in power consumption. It is also possible to increase the gain by augmenting the number of stacked transistors. At low voltage supply, the last solution is not practicable because of the further reduction of the output signal swing.

Slew-Rate (SR) Analysis of the Single-Stage OTA
Due to the finite bias current, I B , the OTA goes into a slew-rate regime at the beginning of the charging process.
According to Equation (5), the maximum rate of variation of the output voltage is obtained at Electronics 2020, 9, 762 8 of 24 where V SRi,max is the maximum amplitude of the input voltage step that keeps the OTA in the linear region. The corresponding output voltage in steady state is given by V SRo,max , which is calculated as follows: where the last approximation is valid as A 0 >> 1 + C 1 /C 2 . In a single-stage OTA, the slew-rate depends on the bias current I B and the feedback capacitance C 2 , i.e.: where g m1 and V ov1 are the transconductance and the overdrive of the M 1 -M 2 input transistors, respectively. Matching the SR formula in Equation (31) to the maximum rate of variation of the output voltage reported in Equation (29), the V SRo,max calculation is obtained: Due to its differential structure, the OTA starts slewing as the input differential voltage step, V i , overcomes 2·V SRi,max . The value of V SRi,max is calculated by combining Equations (30) and (32): The OTA slews until the output voltage reaches the value where the starting value of V i depends on the fact that, at t = 0 s, the capacitances of the integrator behave like short circuits, transferring the input voltage directly to the output. From the previous equation, it is possible to calculate the slewing time of the OTA, τ s : During τ s , the OTA output voltage evolves according to the linear law. Considering the slew-rate, the equation of the differential output voltage, v od (t), is then calculated as follows: Figure 5 shows the step response of the closed loop switched capacitor integrator including the slewing period.

Signal to Noise (SNR) Calculations of the Closed-Loop Switched-Capacitor Integrator
The telescopic Cascode OTA suffers from a reduced output swing. Indeed, both single-ended output voltages must guarantee that the Cascode transistors (M3-M4 and M5-M6) work in a saturation region even under the signal swing. The main limitation is the negative output swing since three

Signal to Noise (SNR) Calculations of the Closed-Loop Switched-Capacitor Integrator
The telescopic Cascode OTA suffers from a reduced output swing. Indeed, both single-ended output voltages must guarantee that the Cascode transistors (M 3 -M 4 and M 5 -M 6 ) work in a saturation region even under the signal swing. The main limitation is the negative output swing since three transistors are stacked between the ground and the output nodes, while only two transistors are stacked between V dd and the output nodes. Focusing the analysis on a single branch, V o+ must satisfy the following inequation to guarantee that M 3 transistors operate in saturation region: where V S3 and V DS,sat3 are the source and the saturation voltages of M 3 transistor, respectively. It is assumed that V ds,sat3 is equal to V ov . The bias voltage V b1 is chosen to make M 1 transistor operating in saturation, i.e.: where V DS1 , V S1 , and V DS,sat1 are the drain-source, the source, and the saturation voltages of M 1 transistor, respectively. In this case, it is assumed that V ds,sat1 is equal to V ov . V S1 is derived from the input transistor common mode, V cm , by dropping the gate-drain voltage of the M 1 transistors, V GS1 , i.e.: Combining Equations (38) and (39) we obtain the minimum source voltage of M 3 transistor, V S3,min : By replacing V S3 in Equation (37) with the value of V S3,min calculated in Equation (40), the minimum value of V o+ , V o+,min , is obtained: As the output voltage starts swinging from the common-mode voltage, V cm , down to V o+,min , it is possible to calculate the maximum output voltage swing, V swing : where the 2 factor is due to the differential architecture. The thermal noise due to the switches around C 1 is calculated as 2· K·T C 1 , where the coefficient 2 takes into account both the sampling (φ 1 ) and the integration phase (φ 2 ). Assuming that the thermal noise 2· K·T C 1 is dominant, from Equation (42), the signal to noise ratio of the overall closed-loop switched-capacitor integrator, SNR CL , is calculated as follows: where v 2 n,o is the total output noise, as a result of the thermal noise contribution due to the C 1 switched-capacitor multiplied by the square of the integrator gain , furthermore, the 1 2 factor takes into account that the input signal is a sinusoid.

Power Consumption Requirements
Regarding the telescopic Cascode shown in Figure 4, the power consumption is given by the product of the supply voltage, V dd , and the bias current I B : Assuming dominant the thermal noise of C 1 , the power consumption of the switched-capacitor integrator is determined by the settling time requirement. In fact, as the input transistor overdrive, V ov1 , is bonded to considerations on the DC-point at low voltage supply, the constraint on the input transistor transconductance, g m1 , expressed by in Equation (21), determines the minimum required bias current I B,min : Therefore, the minimum power consumption, P w,min , is obtained as follows: As the OTA starts slewing, the minimum bias current, I B,min , is determined by taking into account a different calculation for the dynamic error, ε dyn . Indeed, considering Equation (36) that assumes the slewing of the OTA, the differential output voltage at t = T CLK 2 is calculated as follows: The dynamic error, ε dyn , is, then, calculated as follows: Since ε dyn must be less than the required accuracy, ξ, as reported in Equation (19), we obtain: Moreover, the minimum bias current I B,min is evaluated considering τ p reported in Equation (7), the transconductance of the input transistors, g m1 , determined as The minimum power consumption, P w,min , is derived from the last equation as follows:

Proposed Open-Loop Integrator
As an alternative solution, an open-loop switched-capacitor integrator is presented ( Figure 6).
Since εdyn must be less than the required accuracy, ξ, as reported in Equation (19), we obtain: Moreover, the minimum bias current IB,min is evaluated considering τp reported in Equation (7), the transconductance of the input transistors, gm1, determined as , , the formula of the slewing time, τs, in Equation (35), and the previous equation. As a result the minimum bias current IB,min, is calculated as follows: The minimum power consumption, Pw,min, is derived from the last equation as follows:

Proposed Open-Loop Integrator
As an alternative solution, an open-loop switched-capacitor integrator is presented ( Figure 6).  The active element is an OTA, with a low input impedance, which is called charge buffer. Once the input capacitance, C 1 , is connected to the charge buffer input, it is discharged and its charge is transferred to the output capacitance C 2 . The proposed open-loop switched-capacitor integrator does not include two input nodes with high and low impedances, unlike the switched-capacitor integrator based on a current conveyor [10,11], but only low impedance input nodes. Therefore, the voltage buffer used at the input in the conveyor integrators is eliminated. These simplifications help to get a more efficient circuit implementation.
According to the operation mode aforementioned, C 1 is connected to the inverting input terminal, it is possible to write: where Q 1 (n−1) and Q 2 (n) are the charges stored in C 1 and C 2 capacitances, at n − 1 and n time steps, respectively. From Equation (52), it is obtained: where v o and v s are the output and the input voltages. Therefore, it is possible to calculate the integrator By using the proposed approach, we obtain a gain expression, which is identical to the traditional closed-loop integrator reported in Equation (1). In both cases, the desensitization of the gain concerning the OTA parameters is reached as the gain depends only on the C 1 and C 2 capacitor ratio, in the ideal case.

Small Signal Analysis of the Proposed Charge Buffer
To evaluate the impact of the non-null input resistance and the finite output resistance of the charge buffer, the linear model of the integrator reported in Figure 7 was considered.
By using the proposed approach, we obtain a gain expression, which is identical to the traditional closed-loop integrator reported in Equation (1). In both cases, the desensitization of the gain concerning the OTA parameters is reached as the gain depends only on the C1 and C2 capacitor ratio, in the ideal case.

Small Signal Analysis of the Proposed Charge Buffer
To evaluate the impact of the non-null input resistance and the finite output resistance of the charge buffer, the linear model of the integrator reported in Figure 7 was considered. In practice, the C1 capacitance is discharged on input resistance ri, producing the input current ii. This current is amplified with a current gain Ai by the current amplifier that feds the output load made by the output resistance ro and the output capacitance C2.
First of all, the transfer function, , is calculated as previously done for the traditional closedloop switched-capacitor integrator: Compared to the transfer function of the closed-loop switched-capacitor integrator shown in Equation (3), the transfer function of the open-loop switched-capacitor integrator already is calculated, has an additional pole due to the finite output resistance ro. In practice, the C 1 capacitance is discharged on input resistance r i , producing the input current i i . This current is amplified with a current gain A i by the current amplifier that feds the output load made by the output resistance r o and the output capacitance C 2 .
First of all, the transfer function, v o v s (s), is calculated as previously done for the traditional closed-loop switched-capacitor integrator: Compared to the transfer function of the closed-loop switched-capacitor integrator shown in Equation (3), the transfer function of the open-loop switched-capacitor integrator already is calculated, has an additional pole due to the finite output resistance r o .

Transient Analysis of the Proposed Charge Buffer
Assuming a step signal at the input as reported in Equation (2), the output voltage becomes: A v is the voltage gain. The error on the current gain, A i , of the current mirror, directly affects the accuracy of the output voltage. This error mainly depends on the transistor mismatch, which can be minimized thanks to the appropriate design of the overdrive of the transistors forming the current mirror [12].
The output resistance r o , partially drags the charge stored in C 2 . Considering a first-order Taylor's expansion for the e −t/τp2 term, and assuming a unitary current gain, the output voltage, v o (t), at t = T CLK /2, is calculated as follows from Equation (56): The impact of each source of error is evaluated considering the remaining ones disabled.
To evaluate the error, ε r , due to the finite voltage gain, A v , it is assumed that τ p1 tends to zero and τ p2 tends to infinite. In these conditions, the output voltage can be approximated as follows: The corresponding error, ε r , is calculated as the difference between the ideal voltage obtained using the ideal gain value shown in Equation (54), and the value of the voltage expressed in Equation (59), i.e., To evaluate the error due to τ p1 , it is assumed that τ p2 tends to infinite. In these conditions, the output voltage can be approximated as follows: The error due to τ p1 , ε τp1 , is calculated as the difference between the output voltages expressed in Equations (50) and (52), i.e.: The error due to τ p2 , ε τp2 , is calculated as the difference between the output voltages expressed in Equations (58) and (61), i.e.: Figure 8 shows the output voltage behavior.
The error due to τp2, ετp2, is calculated as the difference between the output voltages expressed in Equations (58) and (61), i.e.: Figure 8 shows the output voltage behavior. The sum of the three error εr, ετp1, and ετp2, gives the total error εtot, which must be less than the required accuracy, ξ: Since the error terms εr, ετp1, and ετp2 are positive, each of them must be less than ξ.

Voltage Gain Requirement of the Proposed Charge Buffer
As calculated in Equation (60), εr is less than the ξ, therefore, we obtain In Equation (65)   The sum of the three error ε r , ε τp1 , and ε τp2 , gives the total error ε tot , which must be less than the required accuracy, ξ:

Input and Output Resistances Requirements of the Proposed Charge Buffer
Since the error terms ε r , ε τp1 , and ε τp2 are positive, each of them must be less than ξ.

Voltage Gain Requirement of the Proposed Charge Buffer
As calculated in Equation (60), ε r is less than the ξ, therefore, we obtain In Equation (65) where the last approximation is valid as A v

Input and Output Resistances Requirements of the Proposed Charge Buffer
Assuming ε τp1 , calculated in Equation (62), less than ξ we obtain

Last approximation in Equation (67) is valid as
Electronics 2020, 9,762 15 of 24 Taking into account the expression of τ p1 in Equation (57), the following constraint on the input resistance, r i , is obtained: Assuming ε τp2 , calculated in Equation (63), less than ξ we obtain In this case, last approximation is valid as A v C 1 C 2 . Considering τ p2 in Equation (57), from Equation (69) it is derived the following constraint on the output resistance, r o : As already done for the voltage gain, A v , from Equation (58) where last approximation is valid as 1. This inequation is verified as the condition imposed by Equations (67) and (69) are satisfied, since, generally, V i ξ and According to Equation (69) and considering that V i ξ 1 and is quite less than 1. Therefore, the impact of the r o variation on the integrator performance is limited. Figure 9 shows a possible circuit implementation of the charge buffer. The switched capacitors network at the output nodes is used to set the output common-mode voltage at V cm . Reference V b1 is designed to set the input common-mode voltage at V cm . To keep M 2 and M 8 transistors in the saturation region, their source-drain voltage must be more than their saturation voltage, i.e.:

Circuit Implementation of the Proposed Charge Buffer
It is supposed that V cm is equal to half supply voltage and the saturation voltages correspond to the transistor overdrive, V ov2 , from Equation (73) we derive To bias the M 1 transistor in the saturation region, it must be guaranteed that its source-drain voltage, V SD1 , overcomes its saturation voltage, corresponding to the transistor overdrive, V ov1 , i.e.: From the last equation, we obtain Assuming V cm = V dd /2, the last equation can be rearranged to obtain a constraint on the difference between the M 1 and M 2 transistors overdrives, ∆V ov2−1 , i.e.: Using the finFET 16 nm we obtain the result V dd = 0.95 V, V THP = 0.4 V. Consequently, ∆V ov2−1 must be higher than 75 mV.
According to Equations (74) and (77), using a charge buffer in open-loop configuration gives more flexibility to the design since larger overdrives can be defined for the transistors, to employing an OTA in a closed-loop fashion. This is extremely important at low voltage supply.
Electronics 2020, 9, x FOR PEER REVIEW 15 of 24 Figure 9 shows a possible circuit implementation of the charge buffer. The switched capacitors network at the output nodes is used to set the output common-mode voltage at Vcm. Reference Vb1 is designed to set the input common-mode voltage at Vcm. To keep M2 and M8 transistors in the saturation region, their source-drain voltage must be more than their saturation voltage, i.e.:

Circuit Implementation of the Proposed Charge Buffer
It is supposed that Vcm is equal to half supply voltage and the saturation voltages correspond to the transistor overdrive, Vov2, from Equation (73) we derive To bias the M1 transistor in the saturation region, it must be guaranteed that its source-drain voltage, VSD1, overcomes its saturation voltage, corresponding to the transistor overdrive, Vov1, i.e.:

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(75) From the last equation, we obtain Assuming Vcm = Vdd/2, the last equation can be rearranged to obtain a constraint on the difference between the M1 and M2 transistors overdrives, ΔVov2−1, i.e.: Using the finFET 16 nm we obtain the result Vdd = 0.95 V, VTHP = 0.4 V. Consequently, ΔVov2−1 must be higher than 75 mV.
According to Equations (74) and (77), using a charge buffer in open-loop configuration gives more flexibility to the design since larger overdrives can be defined for the transistors, to employing an OTA in a closed-loop fashion. This is extremely important at low voltage supply. The input and the output resistances, ri and ro, are calculated as follows: where gm1 and gm2 are the transconductance of M1 and M2 transistors, respectively, while rds3 and rds6 are the output resistance of M3 and M6 transistors, respectively.
The voltage gain, Av, is calculated as follows: The input and the output resistances, r i and r o , are calculated as follows: where g m1 and g m2 are the transconductance of M 1 and M 2 transistors, respectively, while r ds3 and r ds6 are the output resistance of M 3 and M 6 transistors, respectively. The voltage gain, A v , is calculated as follows: The telescopic Cascode OTA reported in Figure 4 implements the boost of the output resistance, r o . On the other end, the proposed charge buffer circuit enables the boosting of the transconductance of the input transistors, g m1 , by a g m2 ·r ds3 factor, lowering the input resistance, r i . The impact on the final voltage gain is similar as demonstrated by the similitude of the voltage gain expressions reported in Equations (79) and (27), even if the voltage gain, A v , of the proposed charge buffer results the double with respect to the telescopic Cascode OTA.
In both cases, the power consumption is determined by the settling requirements, i.e., both the time constants τ p and τ p1 for the closed-loop and the proposed open-loop switched-capacitor integrator, respectively. The time constant, τ p , depends on 1/g m1 . In this case, the only possibility to increase g m1 is to increase the bias current I B of the telescopic Cascode OTA, since the input transistor overdrive is bound to bias constraints. For the proposed integrator, the time constant τ p1 is proportional to r i . However, in the last case, as the boost on the input transistor transconductance lowers the input resistance, r i , a significant power saving is obtained.

Slew-Rate Analysis of the Proposed Charge Buffer
According to Equation (56), the maximum rate of variation of the output voltage, i.e., the slew-rate, is obtained at the initial instant, t = 0 s: where: The last approximation in Equation (81) is valid assuming τ p1 τ p2 . The slew-rate depends on the bias current I B and the output capacitance C 2 , i.e.: where I B is the bias current of each branches composing the charge buffer drawn in Figure 9.
Combining Equations (80) and (82) and considering the expression of τ p1 and r i reported in Equations (57) and (78), respectively, we derive: where V ov1 and V ov2 are the overdrive voltage of M 1 and M 2 transistors, respectively, and V A3 is the early voltage of M 3 transistor. Combining Equations (81) and (84), the value of V SRi,max is obtained: The output voltage range where the charge buffer operates in the linear regime, V SRo,max , has been reduced by a factor equal to 4·V A3 V ov2 concerning the traditional closed-loop switched-capacitor integrator with the OTA. Due to its differential structure, the charge buffer starts slewing as V i > 2·V SRi,max . If a slewing period is considered, the differential output voltage, v od (t), can be calculated as follows: where τ s is the duration of the slewing period. The charge buffer slews until the output differential voltage, v od (t), is less than 2·V SRo,max concerning the final value in steady-state, neglecting the losses due to the output resistance (i.e., τ p2 →∞): From the combination of the last equation and Equation (83), the expression of τ s is derived:

SNR Analysis of the Proposed Open-Loop Switched-Capacitor Integrator
By focusing the analysis on a single branch, V o+ must satisfy the following inequation to guarantee that M 4 transistors operate in saturation region: where V S4 and V DS,sat4 are the source and the saturation voltages of M 4 transistor, respectively. It is assumed that V ds,sat4 is equal to V ov . The bias voltage V b5 was chosen to make M 5 transistor operating in saturation, i.e., where V DS5 , and V DS,sat5 are the drain-source, and the saturation voltages of M 4 transistor, respectively. In this case, it is assumed that V ds,sat1 is equal to V ov . V S1 is derived from the V b5 bias voltage, by dropping the gate-drain voltage of the M 4 transistors, V GS4 , i.e.: V b1 can be designed to make V S4 , and, hence, V DS5 equal to V DS5,sat , i.e., V ov . If so, from Equation (88) we derive the minimum output voltage, V o+,min : As the output voltage starts swinging from the common-mode voltage, V cm , down to V o,min , it is possible to calculate the maximum output voltage swing, V swing : where the 2 factor is due to the differential architecture. It is assumed that V cm is equal to half V dd .
Assuming that the thermal noise due to the switches around C 1 , 2· KT C 1 is dominant, from Equation (92), the signal to noise ratio of the overall open loop switched capacitor integrator, SNR OL , is calculated as follows: where v 2 n,o is the total output noise, which is given by the thermal noise contribution due to the C 1 switched-capacitor multiplied by the square of the integrator gain C 1 C 2 2 , and the 1 2 factor takes into account that the input signal is a sinusoid.
The resulting SNR OL is slightly higher than the SNR CL calculated by Equation (43). The output noise is about the same since the noise contribution of C 1 is assumed dominant. However, assuming V TH = 0.275 V and V dd = 0.95 V as for the finFET technology and V ov = 0.1 V, due to bias constraint as defined by Equation (43), the output voltage swing for the proposed switched-capacitor integrator is higher.

Power Consumption Requirement of the Proposed Charge Buffer
The minimum power consumption, P w,min , is given by the product of the supply voltage V dd , by the minimum total bias current I BTOT.min : where I B,min is the minimum I B bias current. The power requirement is calculated according to the settling time requirement. In practice, the minimum bias current I B,min is derived assuming that the ε τp1 error must be less than the required accuracy ξ, i.e.: As V i < 2·V SRi,max , the charge buffer is in the linear regime, where the expression of I B,min is derived from Equation (62): Combining Equations (94) and (96), the minimum required power consumption, P w,min , is calculated as follows: As V i > 2·V SRi,max , the charge buffer starts slewing. Considering the expression of the differential output voltage v od (t), including the slewing period reported in Equation (85), the calculation of the error due to τ p1 , ε τp1 , is updated as follows: Considering ε τp1 as reported in the previous equation, the constraint on τ p1 is derived from Equation (95): Electronics 2020, 9, 762 20 of 24 Looking at τ p1 and r i in Equations (57) and (78), respectively, the minimum bias current that satisfies Equation (99), I B,min is calculated as follows: Combining Equations (97) and (100), the minimum required power consumption is calculated as follows: Figure 10 shows the power consumption of the proposed switched-capacitor integrator and the closed-loop switched-capacitor integrator plotted as a function of V i .
The two curves in Figure 10 are obtained plotting the Equations (97) and (101) for the proposed design, and Equations (46) and (51) for the closed-loop switched-capacitor integrator. The common design parameters are reported in Table 1. Table 1. Design parameters of the switched capacitor integrator.

Small Signal Analysis of the Charge Buffer Considering the Parasitic Capacitance Cpar1
The small-signal equivalent circuit shown in Figure 7 is a first-order approximation of the smallsignal behavior of the proposed transistor-level open-loop switched-capacitor integrator. Considering also the Cpar1 as a parasitic capacitance shown in Figure 9, a more accurate transfer function is obtained:  The minimum power required by the closed-loop switched-capacitor integrator is higher than the proposed open loop integrator for an input signal up to 140 mV large. For V i = 31.25 mV, the proposed circuit requires a minimum power of 76 µW, while the closed-loop switched-capacitor integrator requires about 173 µW, i.e., more than the double.

Small Signal Analysis of the Charge Buffer Considering the Parasitic Capacitance C par1
The small-signal equivalent circuit shown in Figure 7 is a first-order approximation of the small-signal behavior of the proposed transistor-level open-loop switched-capacitor integrator.
Considering also the C par1 as a parasitic capacitance shown in Figure 9, a more accurate transfer function is obtained: where hr ds3 is the output resistances of M 3 transistor. The parasitic capacitance, C par1 , mainly depends on the gate capacitances of M 2 and M 6 transistors. Therefore, it can be approximated as follows: where W 2 and L 2 , and W 6 and L 6 , are the width and the length of M 2 and M 6 transistors.
Concerning the transfer function reported in Equation (55), the transfer function in Equation (84) includes a further zero, z 1 : This zero is considered to be at a very high frequency and it does not produce significant effects on the step response of the proposed circuit.
Moreover, two complex poles appear in the transfer function. Their frequency, ω o , and quality factor, Q, are calculated as follows: A high Q factor determines a large overshoot, OS, on the step response of the proposed circuit, and wide oscillations, which can have a severe impact on the accuracy of the output voltage. Otherwise, as the circuit is excessively dumped, the step response slows significantly. The criterion here adopted is to limit the overshoot to the required accuracy, ξ, i.e.: The previous equation is valid in linear regime; otherwise, in case of slewing of the charge buffer, the overshot is calculated as follows: For the proposed design, the last equation is satisfied for a Q value of about to 0.75. The Q factor can be reduced by operating on V ov2 and V ov1 , or, by acting on the H factor, which gives a further degree of freedom to the design.
The desired value of Q is reached by designing an H factor of 2.

Simulation Results
A transistor-level design of the proposed switched-capacitor circuit was performed in finFET 16 nm CMOS technology. The design parameter reported in Table 1 were considered. The input signal, V i , was assumed equal to 31.25 mV. The bias current, I B , set to 10 µA, corresponds to the minimum value, I B,min , as predicted by Equation (100). The H factor was set to 2 as derived from Equation (107). The minimum power consumption of the core circuit was 76 µA, as predicted by Equation (83).
According to Equation (65), the required voltage gain is 56 dB, while a voltage gain of 71 dB results from simulations. Similarly, the required output resistance obtained from Equation (70) was 1.4 MΩ, while the value obtained through simulations was 1.85 MΩ. Therefore, we can conclude that the voltage gain and the output resistance requirements were largely satisfied. Figure 11 shows the response of the circuit to an input step of 31.25 mV for the theoretical model and simulations. The two curves are very close, proving the validity of the proposed circuit model. Based on the design parameters, the expected error on the output voltage at T CLK /2 was 1 mV. This results from both the model prediction and the simulations. The simulation results show a slightly marked overshot due to the complex poles generated by the internal loop including M1 and M2 transistors, as predicted in paragraph 3.9. However, the firstorder model gives a valid approximation of the circuit behavior especially in the steady-state regime. Table 2 summarizes the required values of the design parameters and their values obtained through simulations.  Table 3 reports the performance summary of the proposed switched-capacitor integrator and compares it to the state-of-the-art approach. The following figure of merit (FoM) is introduced for a fast comparison where N is the number of poles of the switched-capacitor filter under consideration, Pw is its power, fCLK is the clock frequency and OSR is the oversampling ratio, i.e., the ratio between The simulation results show a slightly marked overshot due to the complex poles generated by the internal loop including M 1 and M 2 transistors, as predicted in paragraph 3.9. However, the first-order model gives a valid approximation of the circuit behavior especially in the steady-state regime. Table 2 summarizes the required values of the design parameters and their values obtained through simulations.  Table 3 reports the performance summary of the proposed switched-capacitor integrator and compares it to the state-of-the-art approach. The following figure of merit (FoM) is introduced for a fast comparison where N is the number of poles of the switched-capacitor filter under consideration, P w is its power, f CLK is the clock frequency and OSR is the oversampling ratio, i.e., the ratio between half clock frequency and the maximum signal bandwidth. As can be seen in Table 3, the proposed work is well compared to the state of the art in terms of FoM.

Conclusions
An architecture of a switched-capacitor integrator including a charge buffer operating in open-loop have been proposed and designed in finFET 16 nm technology. As for the switched capacitor filters, the gain of the proposed integrator is given by the capacitor ratio, guarantying desensitization concerning the PVT variations. Furthermore, the proposed circuit is more suitable for low voltage supplies. Moreover, the analytical study demonstrated that the proposed integrator is more efficient than the traditional closed-loop switched-capacitor integrator for input signal amplitude less than 140 mV. The proposed switched-capacitor integrator results were more than twice the efficiency when compared to the traditional closed-loop switched-capacitor filter, as it consumes 76 µW from the 0.95 V supply, assuming an input voltage of 31.25 mV and a clock period of 7 ns. The proposed work results were satisfactory when compared to the state-of-the-art in terms of the figure of merit.