Organic Field-E ﬀ ect Transistor Memory Device Based on an Integrated Carbon Quantum Dots / Polyvinyl Pyrrolidone Hybrid Nanolayer

: In this work, we present a pentacene-based organic ﬁeld-e ﬀ ect transistor memory (OFETM) device, which employs one-step microwave-assisted hydrothermal carbon quantum dots (CQDs) embedded in a polyvinyl pyrrolidone (PVP) matrix, to form an integrated hybrid nanolayer as the charge trapping layer. The as-prepared CQDs are quasi-spherical amorphous C, with sizes ranging from 5 to 20 nm, with a number of oxygen-containing groups and likely some graphite-like domains that produce CQDs with excellent electron-withdrawing characteristics. The incorporation of CQDs into PVP dielectric materials results in a bidirectional storage property. By optimizing the concentration of CQDs embedded into the PVP matrix, the OFETM shows excellent memory characteristics with a large memory window of 8.41 V under a programming / erasing (P / E) voltage of ± 60 V and a retention time of up to 10


Introduction
Organic memory devices have attracted wide attention in recent years due to their many merits over their inorganic counterparts, such as their low-cost, lightweight, solution processability, and mechanical flexibility characteristics [1][2][3]. Among the many types of organic memory devices, organic field-effect transistor memory (OFETM) devices have attracted the most attention due to their excellent properties, such as their single transistor memory cells, nondestructive readouts, compatibility with CMOS technology and potential multi-bit storage [4][5][6]. Generally, OFETM devices are divided into three types according to the charge trapping materials and the mechanism of data storage. A floating-gate OFETM device has a structure similar to that of an organic field-effect transistor (OFET) except the supplementary charge trapping units and tunneling layer which are inserted into the gate dielectric and semiconductor layer [1]. The channel current of the floating-gate OFETM device is modulated by the charges trapped in the floating gates after the programming (P)/erasing (E) pulse voltage is removed. Many materials, such as the noble metals Au, Ag, and Pt nanoparticles (NPs) [7][8][9], polymer semiconductor nanoparticles [10], carbon-based NPs [11], small molecule organic semiconductor materials [12], and transition metal dichalcogenide (TMD) monolayers [13], have been used as charge trapping units in floating-gate OFETM devices. Ferroelectric OFETM devices, in which the threshold voltage (V T ) shifts on the transfer curves, have been implemented by tuning the polarization of the gate dielectric. The polarization direction in the dielectric is determined by the dipole orientation, thus directly leading to the "1" and "0" states of the memory device [14]. Common ferroelectric materials Electronics 2020, 9,753 2 of 9 such as poly(vinylidene fluoride) (PVDF) and its copolymer poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) have been widely studied due to their large spontaneous polarizations and excellent chemical stabilities [15,16]. The third type is polymer electret OFETM devices, which use stable, solution processable, and chargeable dielectric materials inserted between the gate insulator layer and the active layer of the OFETs [17]. Different from floating-gate OFETM, polymer electret OFETM devices have a continuous charge trapping layer and can maintain the captured charges for a long time even without the tunneling layer. The possible memory mechanisms of polymer electrets are summarized as follows: (1) the orientation of permanent dipoles (in polar materials); (2) charge trapping inside the polymer electret bulk (structural defects and impurity centers); (3) charge trapping at the polymer layer/semiconductor layer interface and (or) at the polymer layer/gate insulator layer interface; and (4) charge trapping at the amorphous-crystalline interfaces (in semicrystalline polymers) and the grain boundaries (in polycrystalline materials) [18,19]. The storage capability of the polymer electret materials is determined by the chemical structures, composite ratio and morphology [17]. Baeg. et al. [18] fabricated pentacene-based OFETM devices using various chargeable thin polymer electrets layer onto silicon oxide insulating layers and investigated the effects of the hydrophobicity and polarity of polymer electrets on the properties of OFETM devices. The experimental results show that devices with hydrophobic and nonpolar polymers have nonvolatile characteristics that are superior to those of hydrophilic and polar polymers. For many p-type polymer electret OFETM devices, the influence of the negative gate pulse voltage on the transfer characteristic curves is obviously greater than that of the positive gate pulse voltage. This phenomenon is due to the high electron barrier between the semiconductor and the polymer electret materials [20]. To solve this problem, optical assistance was adopted to reduce (or displace) the positive operating pulse voltage and increase the storage windows [6]. However, there is also another method that uses select materials with strong electron withdrawing properties to be doped into polymer electrets to form integrated hybrid nanocomposites as charge trapping layers [21].
Polyvinyl pyrrolidone (PVP) is a kind of polymer electret material with moderate polarity and amphiphilic properties that is soluble in water and ethanol. Carbon quantum dot (CQD) is a new class of carbon nanomaterials that have emerged in recent years. CQDs have the advantages of low toxicity, environmental friendliness, low cost and simple synthesis methods. Due to their excellent optical properties, many studies using CQDs as light-emitting materials for organic light-emitting diodes (OLED) devices have been reported [22,23]. However, there have been few reports on CQDs used in OFETM as charge trapping sites. In this work, we will report a pentacene-based bottom gate top contact (BGTC) OFETM that uses a CQDs/PVP hybrid nanolayer as the charge trapping layer to realize bidirectional memory characteristics. The CQDs are prepared with low cost materials, and the preparation method is simple. As a result, a large memory window of 8.41 V with a relatively low programming/erasing (P/E) voltage [20] and a data retention time of up to 10 4 s is realized.

Synthesis of the CQDs
The CQDs were prepared by a one-step microwave-assisted hydrothermal method. First, 1 g citric acid and 2 g urea were dissolved in 20 mL deionized water and stirred evenly. Then, this transparent liquid was placed into the microwave oven and heated at 750 W for 5 mins 30 s to obtain a dark, clustered solid sample. Then, the obtained reaction products were put into a vacuum drying oven at 100 • C for 1 h to remove the residual small molecule compounds. The annealed sample was dissolved in 50 mL anhydrous ethanol to obtain a CQD-ethanol saturated solution. After repeated centrifugation (8000 rpm/min, 20 mins), the upper solution was taken to obtain a green quantum-emitting CQD-ethanol solution.
Electronics 2020, 9, 753 3 of 9 Figure 1 shows the schematic of the device structure. The devices were fabricated on heavily doped Si substrates, with a 300-nm-thick SiO 2 on top to form the control gate and control dielectric layer. The CQD/PVP hybrid ethanol solution was spin coated on the Si/SiO 2 substrate at a speed of 2700 rpm/min to fabricate an integrated hybrid charge trapping layer, followed by annealing in a vacuum drying oven at 100 • C for 2 h to remove the residual solution. Subsequently, with the substrates at room temperature, the 50-nm-thick pentacene was deposited onto the CQDs/PVP hybrid nanolayer through vacuum deposition in a high-vacuum system at a pressure of 3 × 10 −4 mbar, where the deposition rate was approximately 0.15∼0.2 Å/s. Finally, 70-nm-thick Au was deposited on the pentacene through thermal evaporation on a shadow mask to fabricate the drain and source electrodes; the working pressure was 3 × 10 −4 mbar, and the deposition rate was kept at 0.3 Å/s. The channel length and the channel width of the device were 80 and 4000 µm, respectively. To research the dependence of the memory characteristics on the concentration of CQDs distributed in the PVP matrix, the CQD-ethanol saturated solution and anhydrous ethanol were mixed in volume ratios of 1:1 and 1:2. Samples were prepared by taking 1 mL from each of the two different CQD-ethanol solutions and mixing them with 6 mg PVP. The corresponding samples were defined as device A (1:1) and device B (1:2). The control sample without CQDs in the PVP matrix was simultaneously prepared following the same process, which was defined as device C (6 mg PVP dissolved in 1 mL anhydrous ethanol).

Device Fabrication
Electronics 2020, 9, x FOR PEER REVIEW 3 of 9 layer. The CQD/PVP hybrid ethanol solution was spin coated on the Si/SiO2 substrate at a speed of 2700 rpm/min to fabricate an integrated hybrid charge trapping layer, followed by annealing in a vacuum drying oven at 100 °C for 2 h to remove the residual solution. Subsequently, with the substrates at room temperature, the 50-nm-thick pentacene was deposited onto the CQDs/PVP hybrid nanolayer through vacuum deposition in a high-vacuum system at a pressure of 3 10 -4 mbar, where the deposition rate was approximately 0.15 ~ 0.2 Å/s. Finally, 70-nm-thick Au was deposited on the pentacene through thermal evaporation on a shadow mask to fabricate the drain and source electrodes; the working pressure was 3 10 -4 mbar, and the deposition rate was kept at 0.3 Å/s. The channel length and the channel width of the device were 80 and 4000 μm, respectively. To research the dependence of the memory characteristics on the concentration of CQDs distributed in the PVP matrix, the CQD-ethanol saturated solution and anhydrous ethanol were mixed in volume ratios of 1:1 and 1:2. Samples were prepared by taking 1 mL from each of the two different CQDethanol solutions and mixing them with 6 mg PVP. The corresponding samples were defined as device A (1:1) and device B (1:2). The control sample without CQDs in the PVP matrix was simultaneously prepared following the same process, which was defined as device C (6 mg PVP dissolved in 1 mL anhydrous ethanol).

Characterization
The CQDs were characterized by transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS). The evaporated pentacene film and Au electrode thickness were measured by a quartz monitor crystal. The surface morphology and the root mean square (RMS) surface roughness of the CQDs/PVP hybrid nanolayer and pentacene layer were characterized by atomic force microscopy (AFM). The electrical characterization of the devices was performed with a Keithley 4200-SCS semiconductor characterization system under an atmospheric environment at room temperature.

CQDs and Hybrid Nanolayer Characterization
In Figure 2a, the TEM image of the CQDs shows that the as-prepared CQDs are quasi-spherical nanoparticles with sizes ranging from 5 nm to 20 nm. The high-resolution TEM imagery did not exhibit a lattice structure for the CQDs. Figure 2b is the XPS C 1s spectrum of the CQDs. The C 1s peak is dominated by the C-C/C=C feature at a binding energy of approximately 284.5 eV, accompanied by the C=O feature at approximately 288.2 eV. The TEM and XPS results suggest that the CQDs are amorphous C with a number of oxygen-containing groups, and may contain some graphite-like domains that produce the as-prepared CQDs with electron-donating and/or electronwithdrawing capabilities [24].

Characterization
The CQDs were characterized by transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS). The evaporated pentacene film and Au electrode thickness were measured by a quartz monitor crystal. The surface morphology and the root mean square (RMS) surface roughness of the CQDs/PVP hybrid nanolayer and pentacene layer were characterized by atomic force microscopy (AFM). The electrical characterization of the devices was performed with a Keithley 4200-SCS semiconductor characterization system under an atmospheric environment at room temperature.

CQDs and Hybrid Nanolayer Characterization
In Figure 2a, the TEM image of the CQDs shows that the as-prepared CQDs are quasi-spherical nanoparticles with sizes ranging from 5 nm to 20 nm. The high-resolution TEM imagery did not exhibit a lattice structure for the CQDs. Figure 2b is the XPS C 1s spectrum of the CQDs. The C 1s peak is dominated by the C-C/C=C feature at a binding energy of approximately 284.5 eV, accompanied by the C=O feature at approximately 288.2 eV. The TEM and XPS results suggest that the CQDs are amorphous C with a number of oxygen-containing groups, and may contain some graphite-like domains that produce the as-prepared CQDs with electron-donating and/or electron-withdrawing capabilities [24].

Field-Effect Characteristics of the OFETM Devices
Figure S1a-c show the output characteristics of the prepared organic field-effect transistor memory (OFETM devices), which exhibit excellent p-channel field-effect transistor characteristics in hole accumulation mode, with a drain source voltage (VDS) ranging from 0 V to −30 V, and a gate source voltage (VGS) from 10 V to −30 V in steps of −5 V (Please see supplementary materials). Figure  4a-c are the initial transfer characteristics of the three devices. The field effect mobility µ and threshold voltage (VT) of the device can be calculated using the following formula: where Ci is the insulator capacitance per unit area, which includes the SiO2 layer and polymer layer. The channel length (L) and width (W) of these devices are 80 and 4000 µm, respectively. As shown in Figure S2.

Field-Effect Characteristics of the OFETM Devices
Figure S1a-c show the output characteristics of the prepared organic field-effect transistor memory (OFETM devices), which exhibit excellent p-channel field-effect transistor characteristics in hole accumulation mode, with a drain source voltage (VDS) ranging from 0 V to −30 V, and a gate source voltage (VGS) from 10 V to −30 V in steps of −5 V (Please see supplementary materials). Figure  4a-c are the initial transfer characteristics of the three devices. The field effect mobility µ and threshold voltage (VT) of the device can be calculated using the following formula: where Ci is the insulator capacitance per unit area, which includes the SiO2 layer and polymer layer. The channel length (L) and width (W) of these devices are 80 and 4000 µm, respectively. As shown in Figure S2.

Field-Effect Characteristics of the OFETM Devices
Figure S1a-c show the output characteristics of the prepared organic field-effect transistor memory (OFETM devices), which exhibit excellent p-channel field-effect transistor characteristics in hole accumulation mode, with a drain source voltage (V DS ) ranging from 0 V to −30 V, and a gate source voltage (V GS ) from 10 V to −30 V in steps of −5 V (Please see supplementary materials). Figure 4a-c are the initial transfer characteristics of the three devices. The field effect mobility µ and threshold voltage (V T ) of the device can be calculated using the following formula: where C i is the insulator capacitance per unit area, which includes the SiO 2 layer and polymer layer. The channel length (L) and width (W) of these devices are 80 and 4000 µm, respectively. As shown Electronics 2020, 9, 753 5 of 9 in Figure S2, the C i of the bilayer insulator capacitance of devices A, B, and C were 8 Figure 5c shows the memory characteristics of device C (control sample). When the negative gate programming voltage (VP) of −60 V for 0.1 s is applied to the control sample, an obvious negative VT drift of 3.09 V is obtained. In addition, the VDS is kept at 0 V throughout the P/E operation. In our previous experiments, no obvious shifts in VT were observed under similar P operation for a pentacene-based OFET without polymer dielectric layers [26]. Thus, the negative VT shifts in device C originate from the insertion of polymer dielectric layers, either via dipolar polarization or charge trapping in the PVP layer. By comparing the storage characteristics of several electret materials with different polarizations, Baeg. et al. proved that the VT shifts in the polymer electron OFETM devices are mainly caused by the charges captured in the electret materials, not by the polarization [18]. Thus, as shown in Figure S3, the electrons transferred from the lowest unoccupied molecular orbital level (LUMO) of PVP to pentacene increase the channel electron concentration of device C, and induce a negative VT drift. Then, a positive erasing gate voltage (VE) of +60 V for 0.1 s was applied to device C. The VT has no significant shift in the positive direction. This effect is due to the electron barrier between the pentacene and PVP (0.1 eV), as shown in Figure S4 and Figure S3. Increasing the VE time to 1 s, the transfer characteristic curves move in the positive direction, which indicates that with increasing P time, some of the hot electrons can obtain enough energy to overcome the barrier and return to the PVP layer, but the shift is still slight, as shown in Figure 5c.  Figure 5c shows the memory characteristics of device C (control sample). When the negative gate programming voltage (V P ) of −60 V for 0.1 s is applied to the control sample, an obvious negative V T drift of 3.09 V is obtained. In addition, the V DS is kept at 0 V throughout the P/E operation. In our previous experiments, no obvious shifts in V T were observed under similar P operation for a pentacene-based OFET without polymer dielectric layers [26]. Thus, the negative V T shifts in device C originate from the insertion of polymer dielectric layers, either via dipolar polarization or charge trapping in the PVP layer. By comparing the storage characteristics of several electret materials with different polarizations, Baeg. et al. proved that the V T shifts in the polymer electron OFETM devices are mainly caused by the charges captured in the electret materials, not by the polarization [18]. Thus, as shown in Figure S3, the electrons transferred from the lowest unoccupied molecular orbital level (LUMO) of PVP to pentacene increase the channel electron concentration of device C, and induce a negative V T drift. Then, a positive erasing gate voltage (V E ) of +60 V for 0.1 s was applied to device C. The V T has no significant shift in the positive direction. This effect is due to the electron barrier between the pentacene and PVP (0.1 eV), as shown in Figures S3 and S4. Increasing the V E time to 1 s, the transfer characteristic curves move in the positive direction, which indicates that with increasing P time, some of the hot electrons can obtain enough energy to overcome the barrier and return to the PVP layer, but the shift is still slight, as shown in Figure 5c.  Figure 5a,b show the memory characteristics of devices A and B, which embedded CQDs into the PVP matrix. When VP = −60 V for 0.1 s is applied (state 1), the negative VT drifts of devices A and B are 3.8 and 4.06 V, respectively, which slightly increases compared with device C. This drift indicates that the as-prepared CQDs have weak electron-donating properties. The electrons that cause the negative shift of VT are mainly provided by the PVP layer, but only a few by CQDs sites, as shown in Figure 6a. Then, the VE = +60 V and the exerting time period from 0.1 s to 0.3 s are applied on device A (state 0). The transfer characteristic curve first returns to its initial position at 0.1 s and continues to move forward as the erasing time increases. Compared with the PVP-only device C, these bidirectional memory characteristics can be attributed to the CQDs embedded into the PVP matrix. The proposed erasing operating mechanism for device A that uses hybrid nanolayer as the charge storage layer is described in Figure 6. The electrons were transferred from the pentacene to the charge trapping layer and were trapped by the CQD sites under the applied positive pulse gate voltage. The as-prepared CQDs have a strong electron-withdrawing capability. One of the electron transfer mechanisms from the active layer to the CQDs is the Fowler-Nordheim (FN) tunneling mechanism, which is attributed to the low field effect mobility of the OFETM [27]. However, because the CQDs are discretely distributed in the PVP matrix, the distance between different CQDs and the pentacene/PVP interface is distinct. For CQDs close to the pentacene/PVP interface, some of the electrons in the pentacene will reach the CQDs via a direct tunneling mechanism. The electrons transferred from the pentacene to the hybrid charge trapping layer reduced the channel electron  Figure 5a,b show the memory characteristics of devices A and B, which embedded CQDs into the PVP matrix. When V P = −60 V for 0.1 s is applied (state 1), the negative V T drifts of devices A and B are 3.8 and 4.06 V, respectively, which slightly increases compared with device C. This drift indicates that the as-prepared CQDs have weak electron-donating properties. The electrons that cause the negative shift of V T are mainly provided by the PVP layer, but only a few by CQDs sites, as shown in Figure 6a. Then, the V E = +60 V and the exerting time period from 0.1 s to 0.3 s are applied on device A (state 0). The transfer characteristic curve first returns to its initial position at 0.1 s and continues to move forward as the erasing time increases. Compared with the PVP-only device C, these bidirectional memory characteristics can be attributed to the CQDs embedded into the PVP matrix.  Figure 5a,b show the memory characteristics of devices A and B, which embedded CQDs into the PVP matrix. When VP = −60 V for 0.1 s is applied (state 1), the negative VT drifts of devices A and B are 3.8 and 4.06 V, respectively, which slightly increases compared with device C. This drift indicates that the as-prepared CQDs have weak electron-donating properties. The electrons that cause the negative shift of VT are mainly provided by the PVP layer, but only a few by CQDs sites, as shown in Figure 6a. Then, the VE = +60 V and the exerting time period from 0.1 s to 0.3 s are applied on device A (state 0). The transfer characteristic curve first returns to its initial position at 0.1 s and continues to move forward as the erasing time increases. Compared with the PVP-only device C, these bidirectional memory characteristics can be attributed to the CQDs embedded into the PVP matrix. The proposed erasing operating mechanism for device A that uses hybrid nanolayer as the charge storage layer is described in Figure 6. The electrons were transferred from the pentacene to the charge trapping layer and were trapped by the CQD sites under the applied positive pulse gate voltage. The as-prepared CQDs have a strong electron-withdrawing capability. One of the electron transfer mechanisms from the active layer to the CQDs is the Fowler-Nordheim (FN) tunneling mechanism, which is attributed to the low field effect mobility of the OFETM [27]. However, because the CQDs are discretely distributed in the PVP matrix, the distance between different CQDs and the pentacene/PVP interface is distinct. For CQDs close to the pentacene/PVP interface, some of the electrons in the pentacene will reach the CQDs via a direct tunneling mechanism. The electrons transferred from the pentacene to the hybrid charge trapping layer reduced the channel electron The proposed erasing operating mechanism for device A that uses hybrid nanolayer as the charge storage layer is described in Figure 6. The electrons were transferred from the pentacene to the charge trapping layer and were trapped by the CQD sites under the applied positive pulse gate voltage. The as-prepared CQDs have a strong electron-withdrawing capability. One of the electron transfer mechanisms from the active layer to the CQDs is the Fowler-Nordheim (FN) tunneling mechanism, which is attributed to the low field effect mobility of the OFETM [27]. However, because the CQDs are discretely distributed in the PVP matrix, the distance between different CQDs and the pentacene/PVP interface is distinct. For CQDs close to the pentacene/PVP interface, some of the electrons in the pentacene will reach the CQDs via a direct tunneling mechanism. The electrons transferred from the pentacene to the hybrid charge trapping layer reduced the channel electron concentration and induced the positive V T drift of device A. As a result, a memory window of approximately 8.41 V was obtained for device A at V P = −60 V for 0.1 s and V E = +60 V for 0.3 s. Device B had the same bidirectional storage characteristics as device A. However, because the concentration of CQDs embedded into the PVP layer of device B was smaller than that of device A, under the same P/E condition (V P = −60 V for 0.1 s and V E = +60 V for 0.3 s), device B only obtained a 4.26 V memory window. Figure 7 shows the retention characteristics of device A. The retention characteristics are important indicators that reflect the capability of nonvolatile data storage in memory. In this work, the retention characteristics of device A were measured by recording I DS at both the 1 and 0 states versus time, at a reading voltage V R = V GS = −10 V in the dark, after a supplied V P = −60 V for 0.1 s and V E = +60 V for 0.3 s, respectively, as shown in Figure 7a. At state 1, the negative reading of I DS slowly increased during the whole measurement process, and this dissipation of trapped charges in the PVP layer is attributed to the internal conduction pathways that form from dipoles, moisture, and ions [18]. However, at the 0 state, I DS exhibit almost no significant change during the entire testing process, which is due to the discrete distribution and electron-withdrawing capability of the CQDs. Figure 7b shows that the memory on/off ratio of the present memory reaches 50% of the initial after 10 4 s, which indicates a long retention time of the device.  Figure 7 shows the retention characteristics of device A. The retention characteristics are important indicators that reflect the capability of nonvolatile data storage in memory. In this work, the retention characteristics of device A were measured by recording IDS at both the 1 and 0 states versus time, at a reading voltage VR = VGS = −10 V in the dark, after a supplied VP = −60 V for 0.1 s and VE = +60 V for 0.3 s, respectively, as shown in Figure 7a. At state 1, the negative reading of IDS slowly increased during the whole measurement process, and this dissipation of trapped charges in the PVP layer is attributed to the internal conduction pathways that form from dipoles, moisture, and ions [18]. However, at the 0 state, IDS exhibit almost no significant change during the entire testing process, which is due to the discrete distribution and electron-withdrawing capability of the CQDs.

Conclusions
In summary, we have demonstrated a strategy to achieve an OFETM based on a CQDs/PVP hybrid nanolayer as a charge trapping layer, and the operating mechanism is discussed in detail. In our experiment, the CQDs prepared by one-step microwave-assisted hydrothermal method have excellent electron-withdrawing properties. Embedding the CQDs into the PVP layer can improve the positive storage performance of the OFETM device. By optimizing the concentration of CQDs doped into the PVP matrix, the device A presents bidirectional memory characteristics. As a result, a large memory window of 8.41 V and a data retention time up to 10 4 s is realized.
Supplementary Materials: The following are available online at www.mdpi.com/xxx/s1, Figure S1: Output characteristics of devices A, B, and C., Figure S2: Device structure to measure the Ci of the bilayer insulator capacitance., Figure S3: Energy band diagrams of device C during programming and erasing operation., Figure  S4: Energy level diagram of devices A and B without applying voltage.

Conclusions
In summary, we have demonstrated a strategy to achieve an OFETM based on a CQDs/PVP hybrid nanolayer as a charge trapping layer, and the operating mechanism is discussed in detail. In our experiment, the CQDs prepared by one-step microwave-assisted hydrothermal method have excellent electron-withdrawing properties. Embedding the CQDs into the PVP layer can improve the positive storage performance of the OFETM device. By optimizing the concentration of CQDs doped into the PVP matrix, the device A presents bidirectional memory characteristics. As a result, a large memory window of 8.41 V and a data retention time up to 10 4 s is realized.
Supplementary Materials: The following are available online at http://www.mdpi.com/2079-9292/9/5/753/s1, Figure S1: Output characteristics of devices A, B, and C., Figure S2: Device structure to measure the C i of the bilayer insulator capacitance., Figure S3: Energy band diagrams of device C during programming and erasing operation., Figure S4: Energy level diagram of devices A and B without applying voltage.