High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler

This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduce the propagation delay and hence increase the maximum operating frequency. The measurement results show that the proposed divide-by-2/3 and divide-by-4/5 prescalers can operate up to 17 GHz and 15.3 GHz, respectively, which increase by 5.4 GHz and 4.3 GHz compared with conventional TSPC prescalers. The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler. The chip occupies an area of 20 × 35 μm2 and 20 × 50 μm2 for the proposed divide-by-2/3 and divide-by-4/5 prescalers.


Introduction
The frequency synthesizer plays an important role in CMOS radio-frequency (RF) and millimeterwave (MMW) applications [1,2]. The high speed dual-modulus frequency prescaler is one of the key blocks in the design of pulse swallow frequency dividers in frequency synthesizers [3,4], since it can achieve multiple division ratios. Operating frequency, power consumption and circuit complexity are usually the main design considerations.
Several types of prescalers have been discussed in previous works. Current mode logic (CML) topology can realize a higher operating frequency while consuming higher power. True-single-phaseclock (TSPC) dividers [5] and prescalers are usually consisted of several stages of TSPC logic gates, which have single-phase clock-controlled latches. Compared to the CML structure, TSPC topology suffers from a relatively lower operating frequency, but benefits from a lower power consumption and smaller area [5][6][7][8][9][10][11]. In addition, the TSPC technique exhibits lower phase noise due to the fewer transistors and faster transitions [12]. The extended-TSPC (E-TSPC) topology has a higher speed than the TSPC topology, since it has one less transistor of each stage, and it is widely studied and optimized [13][14][15][16]. However, the power consumption of E-TSPC blocks is largely affected by the amplitude and DC level of the input clock signal, which have little influence on the TSPC blocks. Besides, E-TSPC architecture has a higher short circuit power than TSPC structures [17]. Moreover, since the NMOS and PMOS transistors may turn on simultaneously, the E-TSPC structure can cause the wrong state in the following stages [5]. Therefore, TSPC prescalers with extended operating frequency are a better choice, which are widely studied [6,[17][18][19][20][21][22][23][24] and applied [2,25] for low power applications.
A TSPC dual-modulus prescaler generally consists of several stages of TSPC D-flip-flops (DFFs) and other logic gates to realize two division ratios. There are many ways to enhance the operating frequency range, such as DFF optimizing [26][27][28][29] and logic-gate embedding [17]. In order to achieve the frequency range, such as DFF optimizing [26][27][28][29] and logic-gate embedding [17]. In order to achieve the highest possible speed using the traditional TSPC DFF, this work mainly focuses on logic modification to reduce the total propagation delay. In addition, logic gates are embedded as well.
This manuscript presents a new structure of a TSPC divide-by-2/3 prescaler and divide-by-4/5 prescaler in a 90-nm CMOS technology. Section 2 describes the circuit design of the proposed prescalers. The measurement results are discussed in Section 3. Finally, a conclusion is provided in Section 4. Figure 1 shows the topology and gate level circuit schematic of the conventional divide-by-2/3 prescaler, which consists of two stages of DFFs, an AND gate and an OR gate. MC (modulus control signal) is used for the divider modulus control. The logic gates incorporated between the DFFs introduce an extra time delay, which limits the operating frequency of the conventional divide-by-2/3 prescaler. The block diagram and schematic of the proposed TSPC divide-by-2/3 prescaler is shown in Figure 2a,b, respectively, which consists of two stages of DFF and two stages of NAND gates. When MC1 is logically low, the 2/3 prescaler operates in the divide-by-2 mode, whereas the 2/3 prescaler operates in the divide-by-3 mode when MC1 is logically high. The advantages of the proposed The block diagram and schematic of the proposed TSPC divide-by-2/3 prescaler is shown in Figure 2a,b, respectively, which consists of two stages of DFF and two stages of NAND gates. When MC 1 is logically low, the 2/3 prescaler operates in the divide-by-2 mode, whereas the 2/3 prescaler operates in the divide-by-3 mode when MC 1 is logically high. The advantages of the proposed prescaler can be better understood by comparing the signal path between nodes Q B1 and S 4 in Figures 1b and 2b. Specifically, two inverters (i.e., inverters consisted of M P5 &M N6 and M P8 &M N9 in Figure 1b) are eliminated from Q B1 to S 3 by replacing the OR gate in the conventional topology with the NAND gate in the proposed structure, which helps to reduce the propagation delay of the clock signal and hence boost the maximum operating frequency. In addition, another two inverters (i.e., inverters made of M P11 &M N12 and M P12 &M N13 in Figure 1b) are saved from S 3 to S 4 in Figure 2b, owing to the co-design of the second NAND gate with the first TSPC gate of DFF 2 , which further decreases the path delay and increases the operating frequency. As a result, when the proposed prescaler operates under the divide-by-2 mode, S 3 is kept high and the prescaler is configured just the same as a fixed-modulus divide-by-2 divider. In other words, it achieves the highest possible speed using the same DFF, since there is no extra delay from the logic gate. As for the divide-by-3 mode, the total propagation delay is reduced by that of four inverters, thereby greatly increasing the maximum operating frequency of the prescaler.

Circuit Design
Electronics 2020, 9, x FOR PEER REVIEW 3 of 10 prescaler can be better understood by comparing the signal path between nodes QB1 and S4 in Figures  1b and 2b. Specifically, two inverters (i.e., inverters consisted of MP5&MN6 and MP8&MN9 in Figure 1b) are eliminated from QB1 to S3 by replacing the OR gate in the conventional topology with the NAND gate in the proposed structure, which helps to reduce the propagation delay of the clock signal and hence boost the maximum operating frequency. In addition, another two inverters (i.e., inverters made of MP11&MN12 and MP12&MN13 in Figure 1b) are saved from S3 to S4 in Figure 2b, owing to the codesign of the second NAND gate with the first TSPC gate of DFF2, which further decreases the path delay and increases the operating frequency. As a result, when the proposed prescaler operates under the divide-by-2 mode, S3 is kept high and the prescaler is configured just the same as a fixed-modulus divide-by-2 divider. In other words, it achieves the highest possible speed using the same DFF, since there is no extra delay from the logic gate. As for the divide-by-3 mode, the total propagation delay is reduced by that of four inverters, thereby greatly increasing the maximum operating frequency of the prescaler. In addition, the transistor MN7 is controlled by the MC1 signal. When the prescaler operates in the divide-by-2 mode, the first DFF stage and NAND logic are shielded, so that the current through this stage will be turned off, thereby reducing the static power consumption of the prescaler. The In addition, the transistor M N7 is controlled by the MC 1 signal. When the prescaler operates in the divide-by-2 mode, the first DFF stage and NAND logic are shielded, so that the current through this stage will be turned off, thereby reducing the static power consumption of the prescaler. The static power consumptions for the divide-by-2 mode and divide-by-3 mode are 217 µW and 436 µW, respectively.
The simulated waveforms of the internal nodes for the conventional and designed divide-by-2/3 prescalers under the divide-by-3 mode are shown in Figure 3. When the input frequency exceeds the maximum operating frequency, signal D 2 in Figure 1 is delayed into the next clock period due to the large delay of the OR and AND gates, resulting in a false logic high level of S 4 . Under such a circumstance, S 5 will drop below the threshold voltage (V DD /2) when the clock is low, causing a false level for Q B2 , as shown in Figure 3a. The waveforms of the conventional and designed structures are compared in Figure 3b, where the operating frequency is slightly below the maximum operating frequency of the conventional prescaler, to make sure that both structures work correctly. Thanks to the proposed new structure, the delay time from Q B1 to S 3 and from S 3 to S 4 is greatly reduced. Therefore, the maximum operating frequency of the proposed prescaler is much higher than the conventional one.
Electronics 2020, 9, x FOR PEER REVIEW 4 of 10 static power consumptions for the divide-by-2 mode and divide-by-3 mode are 217 μW and 436 μW, respectively. The simulated waveforms of the internal nodes for the conventional and designed divide-by-2/3 prescalers under the divide-by-3 mode are shown in Figure 3. When the input frequency exceeds the maximum operating frequency, signal D2 in Figure 1 is delayed into the next clock period due to the large delay of the OR and AND gates, resulting in a false logic high level of S4. Under such a circumstance, S5 will drop below the threshold voltage (VDD/2) when the clock is low, causing a false level for QB2, as shown in Figure 3a. The waveforms of the conventional and designed structures are compared in Figure 3b, where the operating frequency is slightly below the maximum operating frequency of the conventional prescaler, to make sure that both structures work correctly. Thanks to the proposed new structure, the delay time from QB1 to S3 and from S3 to S4 is greatly reduced. Therefore, the maximum operating frequency of the proposed prescaler is much higher than the conventional one.  Figure 2a also shows the block diagram of the proposed divide-by-4/5 prescaler by adopting the proposed divide-by-2/3 prescaler, a NOR logic and a fixed-modulus TSPC divide-by-2 divider. When the MC is logically low, the prescaler operates in the divide-by-5 mode, while the prescaler operates in the divide-by-4 mode if the MC is logically high. The positive output Q2 of the second stage is used as the input clock signal of the TSPC divide-by-2 divider. The modulus control signal of the 2/3 prescaler MC1 is generated by the negative output (QB3) of the divide-by-2 divider and modulus control signal of the MC through the NOR logic.  When the MC is logically low, the prescaler operates in the divide-by-5 mode, while the prescaler operates in the divide-by-4 mode if the MC is logically high. The positive output Q 2 of the second stage is used as the input clock signal of the TSPC divide-by-2 divider. The modulus control signal of the Electronics 2020, 9, 725 5 of 10 2/3 prescaler MC 1 is generated by the negative output (Q B3 ) of the divide-by-2 divider and modulus control signal of the MC through the NOR logic.
Corner simulations are preformed to further show the improvement of the proposed structure. The waveforms of some key nodes are simulated and analyzed under the same operating frequency as Figure 3b. The corner simulations of process, voltage and temperature (PVT) of node Q B2 for the divide-by-3 mode are shown in Figure 4. For the conventional structure, the output is incorrect under the worst case, while the proposed prescaler can work correctly. The process variation simulations for the divide-by-3 mode of node Q B2 are shown in Figure 5. For the conventional structure, the output is incorrect when the transistors are under a slow mode, while the temperature and supply voltage remain the same. The corner simulation waveform of node Q B1 , S 3 and S 5 of the proposed prescaler under divide-by-3 are shown in Figure 6. Compared with Figure 3b, there is no false level around the threshold voltage (in the red box) under each corner of the proposed prescaler. Therefore, the proposed structure is more PVT robust.
Electronics 2020, 9, x FOR PEER REVIEW 5 of 10 Corner simulations are preformed to further show the improvement of the proposed structure. The waveforms of some key nodes are simulated and analyzed under the same operating frequency as Figure 3b. The corner simulations of process, voltage and temperature (PVT) of node QB2 for the divide-by-3 mode are shown in Figure 4. For the conventional structure, the output is incorrect under the worst case, while the proposed prescaler can work correctly. The process variation simulations for the divide-by-3 mode of node QB2 are shown in Figure 5. For the conventional structure, the output is incorrect when the transistors are under a slow mode, while the temperature and supply voltage remain the same. The corner simulation waveform of node QB1, S3 and S5 of the proposed prescaler under divide-by-3 are shown in Figure 6. Compared with Figure 3b, there is no false level around the threshold voltage (in the red box) under each corner of the proposed prescaler. Therefore, the proposed structure is more PVT robust.   Corner simulations are preformed to further show the improvement of the proposed structure. The waveforms of some key nodes are simulated and analyzed under the same operating frequency as Figure 3b. The corner simulations of process, voltage and temperature (PVT) of node QB2 for the divide-by-3 mode are shown in Figure 4. For the conventional structure, the output is incorrect under the worst case, while the proposed prescaler can work correctly. The process variation simulations for the divide-by-3 mode of node QB2 are shown in Figure 5. For the conventional structure, the output is incorrect when the transistors are under a slow mode, while the temperature and supply voltage remain the same. The corner simulation waveform of node QB1, S3 and S5 of the proposed prescaler under divide-by-3 are shown in Figure 6. Compared with Figure 3b, there is no false level around the threshold voltage (in the red box) under each corner of the proposed prescaler. Therefore, the proposed structure is more PVT robust.

Measurement Results and Discussion
The proposed divide-by-2/3 and divide-by-4/5 prescalers are designed and fabricated in a 90nm CMOS technology. The conventional prescalers are also fabricated for comparison. Figure 7 shows the chip microphotograph, which includes a prescaler core, a fixed divider chain and DC pads for the power supply and modulus control. As shown in Figure 7b, for each prescaler, two 100-Ω resistors are used for the input biasing as well as input impedance, roughly matching to 50-Ω. In order to alleviate the influence of parasitic capacitance from the bonding pads on the output signal, a fixed divider chain is applied after the prescaler core to lower the output frequency by a factor of 64 for the divide-by-2/3 prescaler and a factor of 32 for the divide-by-4/5 prescaler. The cores of the divide-by-2/3 and divide-by-4/5 prescalers occupy a chip area of 20 × 35 μm 2 and 20 × 50 μm 2 , respectively. The measurements are carried out on an RF probe station, where the input signal is provided by the Agilent E8257D analog signal generator, and the output signals are measured using the Keysight N9030B signal analyzer.

Measurement Results and Discussion
The proposed divide-by-2/3 and divide-by-4/5 prescalers are designed and fabricated in a 90-nm CMOS technology. The conventional prescalers are also fabricated for comparison. Figure 7 shows the chip microphotograph, which includes a prescaler core, a fixed divider chain and DC pads for the power supply and modulus control. As shown in Figure 7b, for each prescaler, two 100-Ω resistors are used for the input biasing as well as input impedance, roughly matching to 50-Ω. In order to alleviate the influence of parasitic capacitance from the bonding pads on the output signal, a fixed divider chain is applied after the prescaler core to lower the output frequency by a factor of 64 for the divide-by-2/3 prescaler and a factor of 32 for the divide-by-4/5 prescaler. The cores of the divide-by-2/3 and divide-by-4/5 prescalers occupy a chip area of 20 × 35 µm 2 and 20 × 50 µm 2 , respectively. The measurements are carried out on an RF probe station, where the input signal is provided by the Agilent E8257D analog signal generator, and the output signals are measured using the Keysight N9030B signal analyzer.

Measurement Results and Discussion
The proposed divide-by-2/3 and divide-by-4/5 prescalers are designed and fabricated in a 90nm CMOS technology. The conventional prescalers are also fabricated for comparison. Figure 7 shows the chip microphotograph, which includes a prescaler core, a fixed divider chain and DC pads for the power supply and modulus control. As shown in Figure 7b, for each prescaler, two 100-Ω resistors are used for the input biasing as well as input impedance, roughly matching to 50-Ω. In order to alleviate the influence of parasitic capacitance from the bonding pads on the output signal, a fixed divider chain is applied after the prescaler core to lower the output frequency by a factor of 64 for the divide-by-2/3 prescaler and a factor of 32 for the divide-by-4/5 prescaler. The cores of the divide-by-2/3 and divide-by-4/5 prescalers occupy a chip area of 20 × 35 μm 2 and 20 × 50 μm 2 , respectively. The measurements are carried out on an RF probe station, where the input signal is provided by the Agilent E8257D analog signal generator, and the output signals are measured using the Keysight N9030B signal analyzer.  The measured input sensitivity curves of the divide-by-2/3 and divide-by-4/5 prescalers are compared with the conventional TSPCs, as shown in Figures 8 and 9, respectively. It can be seen from Figure 8 that the maximum operating frequency for the conventional divide-by-2/3 prescaler is 11.6 GHz for the divide-by-2 mode and 7.8 GHz for the divide-by-3 mode, respectively, which has been increased to 17 GHz and 15.9 GHz by utilizing the proposed structure. Furthermore, the maximum operating frequency of the proposed divide-by-4/5 prescaler also extends from 11 GHz to 15.3 GHz for the divide-by-4 mode and from 7.7 GHz to 14.2 GHz for the divide-by-5 mode, respectively.
Electronics 2020, 9, x FOR PEER REVIEW 7 of 10 The measured input sensitivity curves of the divide-by-2/3 and divide-by-4/5 prescalers are compared with the conventional TSPCs, as shown in Figures 8 and 9, respectively. It can be seen from Figure 8 that the maximum operating frequency for the conventional divide-by-2/3 prescaler is 11.6 GHz for the divide-by-2 mode and 7.8 GHz for the divide-by-3 mode, respectively, which has been increased to 17 GHz and 15.9 GHz by utilizing the proposed structure. Furthermore, the maximum operating frequency of the proposed divide-by-4/5 prescaler also extends from 11 GHz to 15.3 GHz for the divide-by-4 mode and from 7.7 GHz to 14.2 GHz for the divide-by-5 mode, respectively.   Table 1 summarizes the performance of this work and compares with the other state-of-the-art CMOS TSPC prescalers. As is shown in the table, the proposed design achieves a higher operating frequency, a wider frequency range and a considerable power consumption, which is suitable for modern communication systems. The measured input sensitivity curves of the divide-by-2/3 and divide-by-4/5 prescalers are compared with the conventional TSPCs, as shown in Figures 8 and 9, respectively. It can be seen from Figure 8 that the maximum operating frequency for the conventional divide-by-2/3 prescaler is 11.6 GHz for the divide-by-2 mode and 7.8 GHz for the divide-by-3 mode, respectively, which has been increased to 17 GHz and 15.9 GHz by utilizing the proposed structure. Furthermore, the maximum operating frequency of the proposed divide-by-4/5 prescaler also extends from 11 GHz to 15.3 GHz for the divide-by-4 mode and from 7.7 GHz to 14.2 GHz for the divide-by-5 mode, respectively.

Min. Input Power (dBm)
Input Frequency (GHz) Figure 9. Measured input sensitivity curves of the conventional and proposed divide-by-4/5 prescalers. Table 1 summarizes the performance of this work and compares with the other state-of-the-art CMOS TSPC prescalers. As is shown in the table, the proposed design achieves a higher operating frequency, a wider frequency range and a considerable power consumption, which is suitable for modern communication systems. Many works have been published concerning the improvement of TSPC DFFs [26][27][28][29] and single-phase clocked (SPC) DFFs [31] in recent years. The aim of work is to achieve the highest possible speed using the traditional TSPC DFF under the divide-by-2 mode, as there is no extra delay from the logic gate. Furthermore, the total propagation delay is reduced by that of four inverters as for the divide-by-3 mode.
Some references are about the design, optimization [13][14][15][16] and application [32,33] of the E-TSPC structure, while our paper focuses on the improvement of TSPC prescalers. Reference [33] combines the E-TSPC and TSPC structures. Compared with the E-TSPC topology, the amplitude and DC level of the input clock signal will have little influence on the power consumption of TSPC blocks, which are more PVT-robust. Therefore, our goal is to investigate TSPC prescalers with an extended operating frequency.

Conclusions
Two low-power high-speed TSPC divide-by-2/3 and divide by-4/5 prescalers are designed and implemented in a 90-nm CMOS technology. The logic gates incorporated between the DFFs of the conventional 2/3 prescaler are modified in order to reduce the extra propagation delay and increase the operating frequency. The proposed divide-by-2/3 and divide-by-4/5 prescalers can operate from 1 GHz to 17 GHz, and 1 GHz to 15.3 GHz, respectively, which can be used for the design of frequency synthesizers. The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler. The chip occupies an area of 20 × 35 µm 2 and 20 × 50 µm 2 for the proposed divide-by-2/3 and divide-by-4/5 prescalers, which is promising in the low-power and small-area design tendency.