Understanding of Polarization-Induced Threshold Voltage Shift in Ferroelectric-Gated Field Effect Transistor for Neuromorphic Applications

A ferroelectric-gated fin-shaped field effect transistor (Fe-FinFET) is fabricated by connecting a Pb(Zr0.2Ti0.8)O3-based ferroelectric capacitor into the gate electrode of FinFET. The ferroelectric capacitor shows coercive voltages of approximately −1.5 V and 2.25 V. The polarization-induced threshold voltage shift in the Fe-FinFET is investigated by regulating the gate voltage sweep range. When the maximum positive gate to source voltage is varied from 4 V to 2 V with a fixed starting negative gate to source voltage, the threshold voltage during the backward sweep is increased from approximately −0.60 V to 1.04 V. In the case of starting negative gate to source voltage variation from −4 V to−0.5 V with a fixed maximum positive gate to source voltage of 4 V, the threshold voltage during the forward sweep is decreased from 1.66 V to 0.87 V. Those results can be elucidated with polarization domain states. Lastly, it is observed that the threshold voltage is mostly increased/decreased when the positive/negative gate voltage sweep range is smaller/larger than the positive/negative coercive voltage, respectively.


Introduction
Following Moore's law, the footprint of a transistor in as integrated circuit has been aggressively scaled down, resulting in improved performance/power consumption/integrity of integrated chips (ICs). In order to keep the Moore's law alive, various steep switching devices featuring sub-60 mV/decade subthreshold slope (SS) have been proposed, resulting in overcoming the lower limit of SS (i.e., 60 mV/decade at 300 K), a.k.a., Boltzmann tyranny: tunnel field-effect transistor (TFET) [1], phase-transition FET [2,3], feedback FET [4,5], and negative capacitance FET (NCFET) [6]. Despite these advancements in transistors (especially for low-power applications), semiconductor societies have difficulties in realizing the Internet of Things (IoT) owing to the processing of enormous amounts of data [7,8]. Conventionally, von-Neumann-architecture-based computing systems have been used for processing large quantities of data, but such architectures encounter limitations in the realm of big data [9]. In recent years, the mimicking of biological brain synapses for neuromorphic systems has been widely investigated with the idea that these systems can process tremendous amounts of data at a faster transfer rate [10][11][12][13]. Non-volatile memory devices have been researched as synapse devices for the neuromorphic system, such as phase-change memory [14,15], resistive random-access memory [16], conductive-bridge random-access memory [17], and ferroelectric-gated FET (FeFET) [18]. Among these candidates, FeFET has been highlighted because FeFET can be fabricated by simply inserting a ferroelectric layer into the gate stack of a conventional MOSFET [19][20][21]. Having the same footprint as the conventional FETs, the FeFET can have non-volatile memory characteristics. FeFETs can mimic biological synapse characteristics as the ferroelectric domains are gradually switched by continuously applying a voltage, which leads to the threshold voltage shift and manipulation of the conductivity of FeFET [22][23][24].
Recently, ways to take advantage of hysteresis of FeFET for neuromorphic systems have been demonstrated (i.e. FeFET-based spiking neural networks (SNNs) [25,26] and oscillators [27]). Moreover, thanks to the CMOS-compatible device structure, an integrated ferroelectric-gated fin-shaped FET for neuromorphic applications has been introduced [28]. It has been also demonstrated that FeFETs can be utilized as multi-bit synapse devices by adjusting the number of ferroelectric domains [29]. From this point of view, the impact of domain switching on the operation of FeFET needs to be investigated to comprehend more deeply the operation of FeFET-based synapse devices. However, the experimental results have placed emphasis on the characteristics of neuromorphic synapse devices. Investigations on the polarization-induced threshold voltage shift are still lacking. Specifically, the effect of polarization switching from individual domains needed to be revealed. Therefore, in this study, the impacts of polarization behavior on the characteristics of a ferroelectric-gated fin-shaped FET (Fe-FinFET) are experimentally investigated by means of analyzing the input transfer characteristics. The Fe-FinFET used in this experiment was fabricated by connecting a Pb(Zr 0.2 Ti 0.8 )O 3 (PZT)-based ferroelectric capacitor to the gate region of a baseline FinFET. The threshold voltage in the backward sweep (V th_backward ) of the Fe-FinFET increases from −0.60 V to 1.04 V, when the maximum positive gate-to-source voltage (V GS_positive ) with a negative gate-to-source voltage (V GS_negative ) of −4V is decreased from 4 V to 1 V. On the other hand, when V GS_negative is varied from −4 V to 0 V with a fixed V GS_positive of 4 V, the threshold voltage in the forward sweep (V th_forward ) decreases from 1.67 V to 0.87 V. Those results are elucidated with polarization switching and coercive voltage in ferroelectric material.

Fabrication and Measurement
In this work, n-type enhancement mode FinFET is utilized as a baseline FET. The schematics of the Fe-FinFET are illustrated in Figure 1. The baseline FinFET has 80 nm, 30 nm, 40 nm, 5, 200 nm, and 1.4 nm channel length, fin width, fin height, number of fins, fin pitch, and equivalent oxide thickness, respectively. The fabrication process of the PZT ferroelectric capacitor used in this work is as follows: (i) a NdScO 3 substrate was prepared and (ii) a 20 nm-thick La 0.7 Sr 0.3 MnO 3 was deposited as the bottom electrode. Subsequently, (iii) a 60nm-thick Pb(Zr 0.2 Ti 0.8 )O 3 (PZT) ferroelectric film was deposited using a pulsed laser deposition technique. Lastly, (iv) 60 nm-thick Au/Ti/Au top electrodes were deposited and patterned. The flow of the aforementioned fabrication process is illustrated in Figure 2b. The Fe-FinFET was implemented by physically linking the PZT-based ferroelectric capacitor to the gate region of baseline FinFET with gold wire. Each measurement was done using the Keithley 4200A-SCS semiconductor parameter analyzer at 300 K. For the input transfer curve measurement, forward and backward gate voltage sweep are done in sequence.
In the measurement, the gate-to-source voltage is applied to the device from V GS_negative to V GS_positive (i.e., forward sweep), then the gate-to-source voltage is applied to the device from V GS_positive to V GS_negative (i.e., backward sweep). In this work, the ranges of the gate voltage sweep are varied in two opposite ways: (1) V GS_positive decreases from 4 V to 1 V with the fixed V GS_negative of −4 V. (2) V GS_negative increases from −4 V to 0 V with the fixed V GS_positive of 4 V. Note that V th_forward and V th_backward were extracted using the constant current method at 1.375 × 10 −7 A (i.e., 10 −7 A × (2H fin + W fin )/L fin ). The hysteresis width was calculated by subtracting V th_backward from V th_forward .
Electronics 2020, 9, 704 3 of 9 deposited using a pulsed laser deposition technique. Lastly, (iv) 60 nm-thick Au/Ti/Au top electrodes were deposited and patterned. The flow of the aforementioned fabrication process is illustrated in Figure 2b. The Fe-FinFET was implemented by physically linking the PZT-based ferroelectric capacitor to the gate region of baseline FinFET with gold wire. Each measurement was done using the Keithley 4200A-SCS semiconductor parameter analyzer at 300 K. For the input transfer curve measurement, forward and backward gate voltage sweep are done in sequence.  voltage can switch the polarization direction of only those domains which have a lower coercive voltage than the applied voltage [31][32][33][34][35]. This partial polarization switching can gradually change the conductivity of FeFETs for neuromorphic applications [36]. In order to investigate the partial polarization switching, we have fabricated a ferroelectric capacitor, and its measured capacitance (C)voltage (V) is drawn in Figure 2a. The positive and negative coercive voltage of the ferroelectric capacitor are ~2.25 and ~−1.5 V, respectively. Compared with previous results which show one sharp peak [22], the two peaks at the negative coercive voltage would have originated from aging effect. Although it casts doubt on the ferroelectricity, this device still shows the properties of a ferroelectric layer [see Figure S1 in Supplementary Information]. Figure 3 illustrates the measured input transfer curves of FeFET for various VGS_positive with the same VGS_negative. For all cases [i.e., (i), (ii), and (iii)], the VGS_negative (which is higher than the negative coercive voltage of ferroelectric capacitor for the FeFET) is identical, so that the initial polarization state is identical (i.e., the initial state is aligned upward). As a result, the Vth_forward of the three cases are almost identical. In the case of (i), the VGS_positive induces complete polarization switching, and, thereby, all the domains in the ferroelectric layer are switched to the downward direction. This should result in the Vth_backward being lower than the Vth_forward. The reason for this observation comes from the fact that the downward polarization (in addition to the vertical electrical field from the gate electrode) contributes to the accumulation of electrons when forming a channel. However, in the case of (ii) and (iii), the VGS_positive is not high enough to switch every domain, which results in partial polarization switching (i.e., partially downward). Therefore, the Vth_backward for case (ii) and (iii) is higher than the value for case (i).

Results and Discussion
The ferroelectric layer with a single domain has only two polarization states (i.e., upward or downward direction). When a voltage higher than the coercive voltage is applied, a polarization state can be inverted to the other state. However, most of practical ferroelectric layers have a multi-domain structure [30]. Each domain in the ferroelectric layer has its own coercive voltage because it has more or less doping concentration and grain size than the other domains. As a result, an externally applied voltage can switch the polarization direction of only those domains which have a lower coercive voltage than the applied voltage [31][32][33][34][35]. This partial polarization switching can gradually change the conductivity of FeFETs for neuromorphic applications [36]. In order to investigate the partial polarization switching, we have fabricated a ferroelectric capacitor, and its measured capacitance (C)−voltage (V) is drawn in Figure 2a. The positive and negative coercive voltage of the ferroelectric capacitor are~2.25 and~−1.5 V, respectively. Compared with previous results which show one sharp peak [22], the two peaks at the negative coercive voltage would have originated from aging effect. Although it casts doubt on the ferroelectricity, this device still shows the properties of a ferroelectric layer [see Figure S1 in Supplementary Information]. Figure 3 illustrates the measured input transfer curves of FeFET for various V GS_positive with the same V GS_negative . For all cases [i.e., (i), (ii), and (iii)], the V GS_negative (which is higher than the negative coercive voltage of ferroelectric capacitor for the FeFET) is identical, so that the initial polarization state is identical (i.e., the initial state is aligned upward). As a result, the V th_forward of the three cases are almost identical. In the case of (i), the V GS_positive induces complete polarization switching, and, thereby, all the domains in the ferroelectric layer are Electronics 2020, 9, 704 4 of 9 switched to the downward direction. This should result in the V th_backward being lower than the V th_forward . The reason for this observation comes from the fact that the downward polarization (in addition to the vertical electrical field from the gate electrode) contributes to the accumulation of electrons when forming a channel. However, in the case of (ii) and (iii), the V GS_positive is not high enough to switch every domain, which results in partial polarization switching (i.e., partially downward). Therefore, the V th_backward for case (ii) and (iii) is higher than the value for case (i).  Figure 3. This represents the partial polarization switching occurring in the ferroelectric layer, resulting in the threshold voltage shift. In the case of VGS_positive from 2 V to 1 V, the Fe-FinFET is not turned on due to the lack of gate voltage sweep range. Regardless of the VGS_positive in all the measurements, the Vth_forward values are almost identical when the device is turned on, because the initial polarization states are the same as described above. The Vth_forward and Vth_backward variation is characterized as a function of VGS_positive [see Figure 4c]. Figure 4b shows the hysteresis and subthreshold slope during backward voltage sweep (SSavg_backward) vs. gate voltage. As the hysteresis is decreased from ~2.51 to ~0.82 V due to the Vth_backward shift, the SSavg_backward increases from ~80 to ~462 mV/decade. This can be understood and explained using SS and load-line analysis in FeFETs [6,[37][38][39]. A detailed analysis is described in the Supplementary Information (see the Figure S2   In order to analyze the impact of partial polarization switching on the operation of synapse devices, a FeFET was fabricated and then measured with different V GS_positive values (i.e., from 4 to 1 V) for a fixed V GS_negative (i.e., −4 V) [see Figure 4a]. For 3-4 V of the V GS_positive , the situations are corresponding to the case of (i) shown in Figure 3 (i.e., complete polarization switching). Although the V GS_positive values are different (i.e., 3 V or 4 V), the V th_backward values are similar to each other. In reality, the V th_backward values for the positive gate voltages of 4, 3.5, and 3 V are approximately −0.60, −0.54, and −0.49 V, respectively. These measurement results indicate that there are few domains which have coercive voltages between 3 and 4 V in the ferroelectric layer. Conversely, for the case of the V GS_positive from 2.5 V to 2 V (which is comparable to the positive coercive voltage of~2.25 V), the V th_backward increases from approximately −0.02 to 1.04 V. This situation corresponds to either case (ii) or (iii), as shown in Figure 3. This represents the partial polarization switching occurring in the ferroelectric layer, resulting in the threshold voltage shift. In the case of V GS_positive from 2 V to 1 V, the Fe-FinFET is not turned on due to the lack of gate voltage sweep range. Regardless of the V GS_positive in all the measurements, the V th_forward values are almost identical when the device is turned on, because the initial polarization states are the same as described above. The V th_forward and V th_backward variation is characterized as a function of V GS_positive [see Figure 4c]. Figure 4b shows the hysteresis and subthreshold slope during backward voltage sweep (SS avg_backward ) vs. gate voltage. As the hysteresis is decreased from~2.51 to~0.82 V due to the V th_backward shift, the SS avg_backward increases from~80 to~462 mV/decade. This can be understood and explained using SS and load-line Electronics 2020, 9, 704 5 of 9 analysis in FeFETs [6,[37][38][39]. A detailed analysis is described in the Supplementary Information (see the Figure S2 Figure 5a shows the measured input transfer curves for various VGS_negative (i.e., from −4 to 0 V) with a fixed VGS_positive of 4 V. Contrary to the previous measurements adjusting VGS_positive, the Vth_negative is maintained regardless of the gate voltage sweep range. The reason for the observation shown in Figure 5 is that the polarization states during the backward sweeps are identical owing to the complete polarization switching from the fixed VGS_positive, whereas the Vth_forward decreases as the VGS_negative increases from −4 to 0 V. When the VGS_negative is changed from −4 to −1.5 V, the Vth_forward is almost unvaried within the range of ~1.82 to ~1.67 V [see Figure 5c]. This situation corresponds to the case of manipulating VGS_positive from 4 to 3 V. The unvaried Vth_forward means that there are few domains having a negative coercive voltage that is smaller than −3 V. The Vth_forward starts to further decrease as the VGS_negative becomes larger than −1.5 V (i.e., a similar value to the positive coercive voltage of approximately −1.5 V). The Vth_forward for the VGS_negative of −1 and -0.5 V are ~1.43 and ~0.87 V, respectively. The decrease in Vth_forward originates from the polarization state after the measurement immediately before (i.e., the case of VGS_negative of −1.5 V). After this measurement, the polarization states are not fully arranged to the upward direction due to some domains which have a negative coercive voltage smaller than −1.5 V. As a result, electrons can be assembled to form a channel at a gate voltage lower than the previously measured one. Similarly, in the case of VGS_negative of 0 V, the Vth_forward is decreased, but the current level becomes so high that the exact Vth_forward cannot be  Figure 5a shows the measured input transfer curves for various V GS_negative (i.e., from −4 to 0 V) with a fixed V GS_positive of 4 V. Contrary to the previous measurements adjusting V GS_positive , the V th_negative is maintained regardless of the gate voltage sweep range. The reason for the observation shown in Figure 5 is that the polarization states during the backward sweeps are identical owing to the complete polarization switching from the fixed V GS_positive , whereas the V th_forward decreases as the V GS_negative increases from −4 to 0 V. When the V GS_negative is changed from −4 to −1.5 V, the V th_forward is almost unvaried within the range of~1.82 to~1.67 V [see Figure 5c]. This situation corresponds to the case of manipulating V GS_positive from 4 to 3 V. The unvaried V th_forward means that there are few domains having a negative coercive voltage that is smaller than −3 V. The V th_forward starts to further decrease as the V GS_negative becomes larger than −1.5 V (i.e., a similar value to the positive coercive voltage of approximately −1.5 V). The V th_forward for the V GS_negative of −1 and −0.5 V arẽ 1.43 and~0.87 V, respectively. The decrease in V th_forward originates from the polarization state after the measurement immediately before (i.e., the case of V GS_negative of −1.5 V). After this measurement, Electronics 2020, 9, 704 6 of 9 the polarization states are not fully arranged to the upward direction due to some domains which have a negative coercive voltage smaller than −1.5 V. As a result, electrons can be assembled to form a channel at a gate voltage lower than the previously measured one. Similarly, in the case of V GS_negative of 0 V, the V th_forward is decreased, but the current level becomes so high that the exact V th_forward cannot be extracted using the constant current method at 1.375 × 10 −7 A. These V th_forward and V th_backward variations are plotted in Figure 5c. Figure 5b shows the well-known relationship between the hysteresis (from~2.26 to~1.32 V) and SS avg (from~101 to~416 mV/decade).
Electronics 2020, 9, 704 6 of 9 extracted using the constant current method at 1.375  10 −7 A. These Vth_forward and Vth_backward variations are plotted in Figure 5c. Figure 5b shows the well-known relationship between the hysteresis (from ~2.26 to ~1.32 V) and SSavg (from ~101 to ~416 mV/decade). From all the measurement data shown above, various parameters and characteristics for neuromorphic applications (e.g., pulse amplitude used for the function of "firing") can be acquired. This is because VGS_positive and VGS_negative are equivalent to the amplitude of pulse measurement, in terms of electrical effects, which is the usual method for investigating the characteristics of neuromorphic applications. To be specific, it can be deduced that, if this device is used as a synapse device, the maximum pulse amplitude should not exceed 3 V because it will not affect any polarization state [see Figure 4a]. It can also be found that the threshold voltage shift is originated from the ferroelectricity. This means that if the device shows the characteristics of FeFET (even though the fabrication process or materials are changed), the contents (i.e., the trend shown in Figures  4 and 5) in this work should be applicable. Furthermore, this externally connected device structure is useful when various properties of capacitors need to be investigated, because the capacitor can be simply replaced with other ones. For example, in an externally connected device structure, a sufficiently scaled-down ferroelectric capacitor, which has a few domains, can be used for investigating multi-bit neuromorphic systems without scaling down the baseline FET. On the other hand, in an integrated FeFET structure, the ferroelectric capacitor and baseline FET must be scaled down together to realize a few domains [23,24]. Likewise, using the externally connected device From all the measurement data shown above, various parameters and characteristics for neuromorphic applications (e.g., pulse amplitude used for the function of "firing") can be acquired. This is because V GS_positive and V GS_negative are equivalent to the amplitude of pulse measurement, in terms of electrical effects, which is the usual method for investigating the characteristics of neuromorphic applications. To be specific, it can be deduced that, if this device is used as a synapse device, the maximum pulse amplitude should not exceed 3 V because it will not affect any polarization state [see Figure 4a]. It can also be found that the threshold voltage shift is originated from the ferroelectricity. This means that if the device shows the characteristics of FeFET (even though the fabrication process or materials are changed), the contents (i.e., the trend shown in Figures 4 and 5) in this work should be applicable. Furthermore, this externally connected device structure is useful when various properties of capacitors need to be investigated, because the capacitor can be simply replaced with other ones. For example, in an externally connected device structure, a sufficiently scaled-down ferroelectric capacitor, which has a few domains, can be used for investigating multi-bit neuromorphic systems without scaling down the baseline FET. On the other hand, in an integrated FeFET structure, the ferroelectric capacitor and baseline FET must be scaled down together to realize a few domains [23,24]. Likewise, using the externally connected device structure, we expect that the polarization-induced threshold voltage shift in FeFET will facilitate decisions about various parameters in neuromorphic applications.

Conclusions
The threshold voltage shift characteristics of the Fe-FinFET with a PZT-based ferroelectric capacitor were studied to understand the impact of polarization state on the device operation. The PZT-based ferroelectric capacitor had approximately 2.25 V and −1.5 V of the positive coercive voltage and negative coercive voltage, respectively. The Fe-FinFET was measured with various gate-to-source voltage sweep ranges. Because of the partial polarization switching (i.e., partially downward), the V th_backward was increased from −0.60 to 1.04 V when the V GS_positive was decreased from 4 to 2 V for the same V GS_negative of −4 V. When the V GS_positive was adjusted to a value similar to the positive coercive voltage (i.e., 2.5 and 2 V), the V th_backward was increased to −0.02 and 1.04 V, respectively. When the V GS_negative was regulated from −4 to −0.5 V for the same V GS_positive of 4 V, the V th_forward was decreased from 1.67 to~0.87 V. Similarly, the V th_forward was decreased to~1.43 and~0.87 V when the V GS_negative was changed to a value similar to the negative coercive voltage (i.e., −1 and −0.5 V), respectively. From this research, it was proposed that the externally connected FeFET can contribute to the understanding of the operation of FeFET-based synapse devices in a different way, with the investigation of integrated FeFET-based synapse devices. For multi-bit neuromorphic applications, investigation of the synaptic characteristics of FeFET with sufficiently tiny ferroelectric capacitors needs to be implemented.