Implementation of Unbalanced Ternary Logic Gates with the Combination of Spintronic Memristor and CMOS

Haifeng Zhang 1, Zhaowei Zhang 1, Mingyu Gao 1, Li Luo 2, Shukai Duan 2, Zhekang Dong 1,3,* and Huipin Lin 1,3,* 1 College of electronic information, Hangzhou Dianzi University, Hangzhou 310018, Zhejiang, China; hfzhang0811@hdu.edu.cn (H.Z.); zzw0211@hdu.edu.cn (Z.Z.); mackgao@hdu.edu.cn (M.G.) 2 School of Artificial Intelligence, Southwest University, Chongqing 400715, China; lltaozi12@email.swu.edu.cn (L.L.); duansk@swu.edu.cn (S.D.) 3 College of Electrical Engineering, Zhejiang University, Hangzhou 310027, Zhejiang, China * Correspondence: englishp@hdu.edu.cn (Z.D.); linhuipin@hdu.edu.cn (H.P.)


Introduction
Over the past years, Moore's law seems to have stagnated as the demand for electronic devices to be scaled down has become increasingly difficult to be met [1]. The desire for new materials/mechanism-based devices that are compatible with the traditional complementary metal-oxide-semiconductor (CMOS) is realistic and attractive. The memristor, postulated by Leon Chua in 1971 [2] and physically implemented by a Hewlett Packard (HP) lab in 2008 [3], has become one of the remedies for addressing the continued scaling down of modern electronic circuits. As a passive nanoscale component, a memristor possesses many superior properties, including the nonvolatility, high density, continuous input/output property, threshold property, and variable conductivity [4][5][6]. All these above-mentioned advantages make the memristive device a powerful candidate in intelligent computation [7][8][9][10], with logic operation as an example [10].
So far, memristor-based logic implementation has been gaining considerable attention and many different design approaches have been successively developed [11][12][13][14]. Almost all the existing work mainly focuses on the investigation of binary logic. The work related to the memristor-based multi-value logic (MVL) implementation is relatively rare and incomplete. Compared with the binary

•
A flexible memristor-CMOS-based logic circuit was designed, which could perform the different ternary logic gates (i.e., the NAND, NOR, AND, and OR gates) by easily changing the polarities of the interconnected memristors.

•
Due to the participation of the spintronic memristor, the logic states can be stored in the memristor. That is, the logic computation and data storage are integrated into the proposed logic circuit, which opens up a new path to explore the new intelligent computation systems, in contrast to the classical von Neumann system with separated computation and storage configuration.

•
The CMOS switches installed in the reading circuit means the entire logic circuit has a sufficient load capacity, and the signal degradation issue can also be addressed effectively.
The rest of the paper is organized as below. The spintronic memristor with its resistance variation rule is discussed in Section 2. Based on this, a flexible memristor-CMOS logic circuit, which can perform four basic ternary logic gates, is presented in Section 3. Meanwhile, a brief comparison and analysis of six different ternary logic implementations are carried out in the same section. For verification, a series of circuit simulations (two case studies) with the relevant analysis are conducted in Section 4. Finally, Section 5 concludes the paper.

Spintronic Memristor
Different from the solid-state memristor [2,3], magnetic technology provides other possibilities to build up a memristive system. Wang et al. [21] proposed three possible physical structures of a spintronic memristor. The memristive effect can be realized using the spin-torque-induced magnetization switching or the magnetic-domain-wall motion. Compared to a solid-state thin-film device [2,3], the electrical behavior (describing the relationship between the memristance and the current passing through the memristor) can be controlled more flexibly. Meanwhile, among all the spintronic memristor models, the spin-valve memristor with magnetic-domain-wall motion could be the most suitable candidate due to its compact and simple structure [22,23]. Its three-dimensional (3D) structure and corresponding simplified circuit model is shown in Figure 1.  Figure 1a illustrates the basic structure and physical principle of a current in-plane (CIP) spintronic memristor. This device can be considered a long spin-value strip with the size of D (length) × z (width) × h (height). It consists of two up-down ferromagnetic layers called the free layer and reference layer, respectively. The free layer is divided by a domain-wall into two segments with opposite magnetization directions, where the domain wall motion is driven by spin-polarized current and the scattering of spin-polarized current depends on the position of the domain wall [25]; the reference layer is an integral whole with a fixed magnetization direction. Notably, resistance dependence on the relative orientation of two coupled magnetic layers is called giant magnetoresistance (GMR) and was described theoretically by Camley and Barnaś [26]. Specifically, the resistance per unit length of each segment completely depends on the relative magnetic directions of the free layer and the reference layer. Specifically, when the magnetic direction of the free layer is parallel (anti-parallel) to the reference layer, the resistance per unit length is low (high).
The mathematical expression for the resistance of a spintronic memristor can be written as [23]: (1) where rH and rL denote the highest and lowest resistance per unit length, respectively. The variable x represents the position of the domain wall, and its dynamic function is given as [23]: where η = ±1 denotes the polarity of the spintronic memristor. Γv is the domain wall velocity coefficient, and J and Jcr are the real-time and critical current density, respectively. Then, the critical current Icr can be calculated using Icr = Jcr·h·z. The domain wall movement occurs only when the realtime current density J is above the critical current density Jcr. Differentiating Equation (1) with respect to t gives the memristance variation rate as follows: where Δr denotes the difference between rH and rL, i.e., Δr = rH − rL. From Equation (3), if the real-time current density J is smaller than the critical current density Jcr (namely, J < Jcr), the memristance variation is equal to zero, the spintronic memristor can be deemed an ordinary resistor; otherwise (i.e., J ≥ Jcr), Equation (3) can be rewritten as: where V is the voltage applied to the spintronic memristor. By integrating both sides of Equation (4), Equation (1) can be rewritten as:  Figure 1a illustrates the basic structure and physical principle of a current in-plane (CIP) spintronic memristor. This device can be considered a long spin-value strip with the size of D (length) × z (width) × h (height). It consists of two up-down ferromagnetic layers called the free layer and reference layer, respectively. The free layer is divided by a domain-wall into two segments with opposite magnetization directions, where the domain wall motion is driven by spin-polarized current and the scattering of spin-polarized current depends on the position of the domain wall [25]; the reference layer is an integral whole with a fixed magnetization direction. Notably, resistance dependence on the relative orientation of two coupled magnetic layers is called giant magnetoresistance (GMR) and was described theoretically by Camley and Barnaś [26]. Specifically, the resistance per unit length of each segment completely depends on the relative magnetic directions of the free layer and the reference layer. Specifically, when the magnetic direction of the free layer is parallel (anti-parallel) to the reference layer, the resistance per unit length is low (high).
The mathematical expression for the resistance of a spintronic memristor can be written as [23]: where r H and r L denote the highest and lowest resistance per unit length, respectively. The variable x represents the position of the domain wall, and its dynamic function is given as [23]: where η = ±1 denotes the polarity of the spintronic memristor. Γ v is the domain wall velocity coefficient, and J and J cr are the real-time and critical current density, respectively. Then, the critical current I cr can be calculated using I cr = J cr ·h·z. The domain wall movement occurs only when the real-time current density J is above the critical current density J cr . Differentiating Equation (1) with respect to t gives the memristance variation rate as follows: where ∆r denotes the difference between r H and r L , i.e., ∆r = r H − r L . From Equation (3), if the real-time current density J is smaller than the critical current density J cr (namely, J < J cr ), the memristance variation is equal to zero, the spintronic memristor can be deemed an ordinary resistor; otherwise (i.e., J ≥ J cr ), Equation (3) can be rewritten as: Electronics 2020, 9, 542 4 of 14 where V is the voltage applied to the spintronic memristor. By integrating both sides of Equation (4), Equation (1) can be rewritten as: where ϕ is the magnetic flux flowing through the spintronic memristor and the flux thresholds (ϕ th1 and ϕ th2 ) are determined by the natural memristance boundary: R H = r H ·D and R L = r L ·D (commonly R H R L ). M 0 denotes the initial memristance at t = 0, and A = ∆r·η·Γ v /h/z is an auxiliary constant. From Equation (5), if the real-time current density J always satisfies J ≥ J cr , the total flux variation ∆ϕ can be calculated using: where M obj denotes the target memristor. Furthermore, assuming the applied voltage is a constant V con , the switching time ∆T can be computed using ∆T = ∆ϕ/V con .
To facilitate the circuit simulation in the subsequent sections, the corresponding Spice model of a spintronic memristor was built up. The relevant sub-circuit description is provided in Table 1.
Phase 2: Until the real-time current density satisfied J < J cr , the memristance tended to be steady. Figure 2b illustrates the memristance variation under a negative voltage pulse V−. Similarly, the memristance variation could be divided into two phases.
Phase 1: When 0 ≤ t ≤ 200 ns, the real-time current density satisfied J < J cr and the memristance remained at the initial value R H . Phase 2: Once the real-time current density satisfied J ≥ J cr (i.e., 200 ns ≤ t ≤ 400 ns), the memristance decreased to its lowest value R L within a short time. *******Charge computation ******* Echarge charge 0 value={SDT(I(Emem))} .ENDS spintronic memristor Notably, the memristance variation rule of the spintronic memristor, which is very important for the implementation of memristor-based multi-valued logic, is discussed through the use of PSpice circuit simulations (as shown in Figure 2, Version 16.5, Cadence, San Jose, CA, USA).

Implementation of Ternary Logic Gates
In this section, a specific description of the design process of a flexible memristor-CMOS hybrid circuit for the implementation of ternary logic gates (NAND, NOR, AND, and OR gates) is given.

Memristor-CMOS Hybrid Circuit
The memristor-CMOS hybrid circuit diagram for the implementation of ternary logic gates is provided in Figure 3. Note that the entire circuit can be divided into three parts: the leftmost box is the so-called initialization circuit, the middle box is the writing circuit, and the rightmost box provides the corresponding reading circuit.  . Vth1 = RL·Icr and Vth2 = RH·Icr were the voltage thresholds, and the initial memristance was set to M0 = RL. In each period, the memristance variation could be divided into two phases as follows: Phase 1: The real-time current density satisfied J ≥ Jcr, where the memristance increased while the real-time current density decreased.
Phase 2: Until the real-time current density satisfied J < Jcr, the memristance tended to be steady. Figure 2b illustrates the memristance variation under a negative voltage pulse V−. Similarly, the memristance variation could be divided into two phases.
Phase 1: When 0 ≤ t ≤ 200 ns, the real-time current density satisfied J < Jcr and the memristance remained at the initial value RH.
Phase 2: Once the real-time current density satisfied J ≥ Jcr (i.e., 200 ns ≤ t ≤ 400 ns), the memristance decreased to its lowest value RL within a short time.

Implementation of Ternary Logic Gates
In this section, a specific description of the design process of a flexible memristor-CMOS hybrid circuit for the implementation of ternary logic gates (NAND, NOR, AND, and OR gates) is given.

Memristor-CMOS Hybrid Circuit
The memristor-CMOS hybrid circuit diagram for the implementation of ternary logic gates is provided in Figure 3. Note that the entire circuit can be divided into three parts: the leftmost box is the so-called initialization circuit, the middle box is the writing circuit, and the rightmost box provides the corresponding reading circuit.

Reading circuit Writing circuit
Input voltages  In the writing circuit (as shown in Figure 3), M1 and M2 (labeled by the blue dashed box) are two identical spintronic memristors with the boundary resistances RL and RH. Namely, their resistances (R1 and R2) satisfy R1,2∈ [RL, RH]. The remaining memristor Ms (labeled by the red dashed box) is named the load memristor. Its resistance (Rs) varies from RSL to RSH, i.e., Rs∈ [RSL, RSH]. Notably, to realize different ternary logic gates, the three resistances should always satisfy Rs ≫ R1,2. V1 and V2 are two time-sequence inputs with the period T, and Vc is a constant voltage. In the initialization circuit, Vini = ±VDD denotes the initialization voltage for the resistance initialization. In the reading circuit, Vread In the writing circuit (as shown in Figure 3), M 1 and M 2 (labeled by the blue dashed box) are two identical spintronic memristors with the boundary resistances R L and R H . Namely, their resistances (R 1 and R 2 ) satisfy R 1,2 ∈[R L , R H ]. The remaining memristor M s (labeled by the red dashed box) is named the load memristor. Its resistance (R s ) varies from R SL to R SH , i.e., R s ∈[R SL , R SH ]. Notably, to realize Electronics 2020, 9, 542 6 of 14 different ternary logic gates, the three resistances should always satisfy R s R 1,2 . V 1 and V 2 are two time-sequence inputs with the period T, and V c is a constant voltage. In the initialization circuit, V ini = ±V DD denotes the initialization voltage for the resistance initialization. In the reading circuit, V read represents the reading voltage. Its value satisfies V read < R SL ·I cr such that the load memristance variation will not occur during the reading operation. R c1 , R c2 , and R c3 are three regular resistors.
Then, it can be concluded that a ternary logic operation can be realized using the proposed memristor-CMOS hybrid circuit within three steps, namely initialization, writing operation, and reading operation. The input voltages (V 1 and V 2 ) and the output voltage V out represent the input and output logic state variations, respectively. The specific realization process is provided in the next subsection.

NAND Gate
Theoretically, the NAND gate can be deemed a universal gate. Namely, every other gate function can be generated by successive implementations of NAND gates [10]. Hence, the specific realization of a ternary NAND gate is demonstrated below.
From Figure 3, the specific circuit diagram for the implementation of a ternary NAND gate is demonstrated in Figure 4. Based on the previous description, the entire operation is performed in three steps.
Electronics 2020, 9,542 6 of 15 represents the reading voltage. Its value satisfies Vread < RSL·Icr such that the load memristance variation will not occur during the reading operation. Rc1, Rc2, and Rc3 are three regular resistors. Then, it can be concluded that a ternary logic operation can be realized using the proposed memristor-CMOS hybrid circuit within three steps, namely initialization, writing operation, and reading operation. The input voltages (V1 and V2) and the output voltage Vout represent the input and output logic state variations, respectively. The specific realization process is provided in the next subsection.

NAND Gate
Theoretically, the NAND gate can be deemed a universal gate. Namely, every other gate function can be generated by successive implementations of NAND gates [10]. Hence, the specific realization of a ternary NAND gate is demonstrated below.
From Figure 3, the specific circuit diagram for the implementation of a ternary NAND gate is demonstrated in Figure 4. Based on the previous description, the entire operation is performed in three steps. Step 1: Initialization As the name suggests, the initialization is conducted by the initialization circuit (as shown in Figure 3). Based on the memristance variation rule, when the initialization voltage Vini = VDD, the upper transistor Tr3 turns off, while the lower transistor Tr4 turns on. In this situation, the voltage applied to the memristor is equal to −VDD and the resistance of the memristor will decrease. On the contrary, when the initialization voltage Vini = −VDD, the transistor Tr3 turns on and the lower transistor Tr3 turns off. The voltage applied to the memristor is equal to VDD and the memristance will increase. Before each ternary NAND operation, the memristors M1 and M2 need to initialize to their lowest value RL, and it is recommended that the memristor Ms1 is initialized to a median value RMid.
Step 2: Writing operation The writing operation is performed by the writing circuit. Based on Kirchhoff's current law (KCL), the current flowing in the writing circuit can be written as: Due to Rs1 ≫ R1, 2, the node voltage Vs can be approximately calculated using: For ternary logic operations, the inputs (V1 and V2) always have three states VH, VL, and VMid, representing the logic "2," logic "1," and logic "0," respectively. Then, the six possible cases can be summarized as follows: Step 1: Initialization As the name suggests, the initialization is conducted by the initialization circuit (as shown in Figure 3). Based on the memristance variation rule, when the initialization voltage V ini = V DD , the upper transistor Tr 3 turns off, while the lower transistor Tr 4 turns on. In this situation, the voltage applied to the memristor is equal to −V DD and the resistance of the memristor will decrease. On the contrary, when the initialization voltage V ini = −V DD , the transistor Tr 3 turns on and the lower transistor Tr 3 turns off. The voltage applied to the memristor is equal to V DD and the memristance will increase. Before each ternary NAND operation, the memristors M 1 and M 2 need to initialize to their lowest value R L , and it is recommended that the memristor M s1 is initialized to a median value R Mid .
Step 2: Writing operation The writing operation is performed by the writing circuit. Based on Kirchhoff's current law (KCL), the current flowing in the writing circuit can be written as: Electronics 2020, 9, 542 7 of 14 Due to R s1 R 1, 2 , the node voltage V s can be approximately calculated using: For ternary logic operations, the inputs (V 1 and V 2 ) always have three states V H , V L , and V Mid , representing the logic "2," logic "1," and logic "0," respectively. Then, the six possible cases can be summarized as follows: • Case a: When V 1 = V 2 = V H (logic "2"), the node voltage V s ≈ V H (From Equation (8)). The voltage applied to the load memristor M s1 is equal to V H − V c . Assuming V H − V c > R Mid ·I cr , the load memristance R s1 will go down to its lowest value R SL within a very short time.
The voltage applied to the load memristor M s1 is equal to V c − V L . Assuming |V c − V L | > R Mid ·I cr , the load memristance R s1 will sharply increase to its highest value R SH . • Case d: When V 1 = V L and V 2 = V H (or V 1 = V H and V 2 = V L ), the node voltage V s can be calculated using: According to the memristance variation rule, the node voltage V s will vary to R L /(R L +R H )·V H ≈ 0 (due to R H R L ). Similar to Case c, the load voltage is equal to V c − V L , and the load memristance R s1 will go up to its highest value R SH .

•
Case e: When V 1 = V L and V 2 = V Mid (or V 1 = V Mid and V 2 = V L ), the node voltage V s can be calculated using: Here, the voltage V Mid satisfies |V Mid |>R L · I cr , the node voltage V s will change to R L /(R L +R H )·V Mid ≈ 0. The load memristance will increase to the highest value R SH .

•
Case f: When V 1 = V H and V 2 = V Mid (or V 1 = V Mid and V 2 = V H ), the node voltage V s can be expressed as: Here, once the voltage V Mid satisfies |V H − V Mid |>R L ·I cr , the node voltage V s will change to R H /(R L +R H )· V Mid ≈ V Mid . Similar to Case b, the load memristance remains in its initial state, i.e., R Mid .
Step 3: Reading operation After writing operation, the reading operation is performed by the reading circuit. Based on the specific load memristance, three cases can be distinguished as follows.

•
Case I: When the load memristance R s1 = R SH , the node voltage V g can be calculated using: Electronics 2020, 9, 542 8 of 14 Assuming R SH R c1 , the node voltage V g ≈ 0. At this time, the transistor Tr 1 turns on, while the other transistor Tr 2 turns off. As a result, the output V out = V out1 = V DD = V H , denoting the logic "2."

•
Case II: When the load memristance R s1 = R Mid , the node voltage V g can be given as: Assuming R Mid = R c1 and R c2 = R c3 , the node voltage is equal to 0.5V read . At this time, transistors Tr 1 and Tr 2 both turn on, and the current flows through two resistors R c2 and R c3 . Correspondingly, the output voltage V out = V out2 = 0.5V DD = V Mid , which denotes the logic "1."

•
Case III: When the load memristance R s1 = R SL , The node voltage can be computed using: Assuming R c1 R SL , the node voltage V g ≈ V read . Contrary to Case I, the transistor Tr 1 turns off, while the other transistor Tr 2 turns on. The output V out = V out3 = V Gnd = V L , representing the logic "0." For the purpose of clarity, a summary of the information regarding the ternary NAND gate is collected in Table 2. It is clear that the input-output relationship of the presented logic circuit is consistent with the truth table of the NAND gate, which verifies the validity of the entire operation process. Table 2. A summary of the information of the ternary NAND gate.
Truth Table 1 Writing Operation Reading Operation 1 In 1,2 and Out denote the inputs and output of the NAND gate, respectively.
From Table 2, since both the input and output variables are represented as constant voltages, the signal degradation can be addressed in the presented logic circuit. Meanwhile, due to the existence of the CMOS in the reading circuit, the proposed logic circuit possesses a sufficient load capacity. These two advantages enable the ternary NAND gate circuit to be easily cascaded for the realization of some more complex ternary logic operations. In addition, the proposed double-input ternary NAND logic gate circuit can be further extended to realize the multi-input ternary NAND gate. The corresponding process description will not be repeated here due to the similarity with the double-input ternary NAND logic gate.

Other Ternary Logic Gates
Similarly, the proposed memristor-CMOS hybrid circuit can perform some other ternary logic gates, such as the NOR, AND, and OR gates. The corresponding circuit diagrams are exhibited in Figure 5. It is noted that, since the initialization circuit and reading circuit for all the above-mentioned ternary logic gates are the same (as shown in Figure 3), they are not provided in this part.  Figure 5. The writing circuit for the implementation of other ternary logic gates.
From Figure 5, these three ternary logic gates can be realized using the uniform circuit structure (i.e., the proposed memristor-CMOS hybrid circuit). Then, the operation steps (i.e., the initialization, writing operation, and reading operation) of these three ternary logic gates are the same as that of the two-input ternary NAND gate. In particular, during the initialization, the memristors M1 and M2 are both set to their highest state RH, and the load memristor Rs1 is initialized to a median value RMid. Furthermore, due to the same circuit structure, the KCL function of all three logic circuits (AND, OR, and NOR gates) can also be mathematically expressed using Equation (7) and Equation (8). Therefore, the specific process description of these three ternary logic gates is not provided in this part due to the similarity with the two-input ternary NAND gate.
Notably, the only difference among these logic circuits (NAND, AND, OR, and NOR gates) is the polarity of the memristor (i.e., the connection mode). Hence, Figure 5 provides the important polarity information of the interconnected memristors (or the memristor connection mode), which is necessary for the implementation of different basic ternary logic gates.
For simplicity, the overall information of these logic gates is collected in Table 3. Table 3. The overall information of the other ternary gates: AND, OR, and NOR gates.

Logic Functions
Truth VL, VMid, and VH represent the logic "0," logic "1," and logic "2," respectively. From Figure 5, these three ternary logic gates can be realized using the uniform circuit structure (i.e., the proposed memristor-CMOS hybrid circuit). Then, the operation steps (i.e., the initialization, writing operation, and reading operation) of these three ternary logic gates are the same as that of the two-input ternary NAND gate. In particular, during the initialization, the memristors M 1 and M 2 are both set to their highest state R H , and the load memristor R s1 is initialized to a median value R Mid . Furthermore, due to the same circuit structure, the KCL function of all three logic circuits (AND, OR, and NOR gates) can also be mathematically expressed using Equation (7) and Equation (8). Therefore, the specific process description of these three ternary logic gates is not provided in this part due to the similarity with the two-input ternary NAND gate.
Notably, the only difference among these logic circuits (NAND, AND, OR, and NOR gates) is the polarity of the memristor (i.e., the connection mode). Hence, Figure 5 provides the important polarity information of the interconnected memristors (or the memristor connection mode), which is necessary for the implementation of different basic ternary logic gates.
For simplicity, the overall information of these logic gates is collected in Table 3. Table 3. The overall information of the other ternary gates: AND, OR, and NOR gates. Table  Initialization Writing Operation Reading Operation
From Table 3, the input and output of these three logic circuits are all constant voltages and their relationships are all consistent with the corresponding truth table, which verifies the validity of the entire scheme.

Comparison and Analysis
In this subsection, five existing ternary logic implementations (i.e., the CMOS based logic [17], CNTFET based logic [18], the memristor-CNTFET based logic [20], pure memristor-based logic [16], and memristor-as-driver (MAD) logic [12]) are introduced for comparison purposes. The corresponding information (including circuit construction, input and output mode, load capacity, cascaded capacity, robustness, and functionality) is collected in Table 4. From Table 4, the circuit structure of the proposed method (i.e., method 1) is fixed and uniform compared with the other five competitors. That is, for the existing ternary logic implementation, different logic gates always need different circuit diagrams, which may lead to additional fabrication costs. Then, different from the pure memristor-based method (i.e., method 5) and the MAD method (i.e., method 6), the input and output logic state variables of the proposed method are both constant voltages, which is beneficial for addressing the signal degradation issue. Meanwhile, due to the participation of the CMOS switches, the proposed ternary logic circuit has a sufficient load capacity. Notably, based on the above two advantages, the proposed ternary logic can be used for the implementation of some more complicated logic functions with the cascaded configuration (i.e., the easily-cascaded feature). Furthermore, except for the CMOS-based method (i.e., method 2) and the CNTFET-based method (i.e., method 3), the initialization is necessary for the other four methods (including the proposed ternary logic), which may lead to a relatively big time delay. However, the robustness of methods 2 and 3 is not as good as the other competitors. Specifically, for methods 2 and 3, the logic operation and storage are two independent and parallel processes. That is, if the power is switched off during the logic operation, all the memory contents are erased immediately. For the other four ternary logic implementations, the logic states can be stored in the memristors (i.e., the non-volatility). Furthermore, method 2 is highly sensitive to the transistor dimensions, and method 3 suffers from the "charge pile-up" issue in the channel that may affect the performance of on/off switching. In addition, the proposed method can implement all the basic ternary logic gates, while methods 2 and 3 just provide the circuit diagrams of the ternary NOR gate and NAND gate.

Circuit Simulations and Analysis
To verify the validity and effectiveness of the entire scheme, a series of circuit simulations with the relevant analysis were conducted. The entire process description is provided below.

Experimental Environment
The experiment platform was a desktop workstation with a Core i7-6700 processor, 16 GB DDR4 RAM, and a Windows 10 OS. As with the other existing memristor-based logic implementation [12,16,20], the circuit experiments were also performed using PSpice (Version 16.5, Cadence, San Jose, CA, USA) and Matlab software (R2014a, MathWorks, Natick, MA, USA).

Parameter Selection
Based on the previous description, the parameter selection (including the device parameters and stimulation parameters) is very important for the realization of the ternary logic gates. Considering the above-mentioned constraint conditions and the device characteristics of the spintronic memristor, the parameters were chosen and are collected in Table 5. Table 5. Technical parameters for the implementation of ternary logic. Notably, the device parameters of the spintronic memristors (shown in Table 5) are all common values that have been proved to be valid in the literature [21]. Meanwhile, the (threshold) voltages and current densities are suitable for CMOS technology [27]. All the constraint conditions are achieved in this experiment.

Simulation Results and Analysis
Based on the given technical parameters, two case studies were investigated to verify the effectiveness of the proposed circuit. The specific results and the corresponding analysis are provided below.

Case Study 1
In case study 1, the ternary NAND, NOR, AND, and OR gates were realized using the proposed hybrid memristor-CMOS logic circuit. Figure 6 illustrates the simulation results of four basic ternary logic gates, i.e., the NAND gate (the first two rows), the NOR gate (the second two rows), the AND gate (the third two rows), and the OR gate (the last two rows). In 1 (the green solid line) and In 2 (the red dashed line) represent the input signals during the writing operation, and the purple solid line represents the obtained output logic states. Here, W(i, j) and R(o) denote the writing operation and reading operation, respectively. The variables i, j, and o represent the logic states of the input and output signals. The obtained input-output relationships were consistent with the corresponding truth tables (as shown in Tables 2 and 3), and the response time was very short (nanosecond scale). Both of these demonstrate the validity and effectiveness of the proposed memristor-CMOS based circuit diagram.
Then, the memristance variation during a ternary NAND operation is exhibited in Figure 7. The green solid line and the brown dashed line represent the resistance of memristors M 1 and M 2 , respectively, and the blue solid line denotes the resistance of the load memristor M s1 . The memristance variation was in accordance with the theoretical analysis in Section 3. Meanwhile, when the power cut off, the output logic state could be stored in the load memristor M s1 in the resistance form. Therefore, the robustness of the proposed circuit could be sufficiently guaranteed. Then, the memristance variation during a ternary NAND operation is exhibited in Figure 7. The green solid line and the brown dashed line represent the resistance of memristors M1 and M2, respectively, and the blue solid line denotes the resistance of the load memristor Ms1. The memristance variation was in accordance with the theoretical analysis in Section 3. Meanwhile, when the power cut off, the output logic state could be stored in the load memristor Ms1 in the resistance form. Therefore, the robustness of the proposed circuit could be sufficiently guaranteed.   Then, the memristance variation during a ternary NAND operation is exhibited in Figure 7. The green solid line and the brown dashed line represent the resistance of memristors M1 and M2, respectively, and the blue solid line denotes the resistance of the load memristor Ms1. The memristance variation was in accordance with the theoretical analysis in Section 3. Meanwhile, when the power cut off, the output logic state could be stored in the load memristor Ms1 in the resistance form. Therefore, the robustness of the proposed circuit could be sufficiently guaranteed.

Case Study 2
To demonstrate that the proposed logic circuit could perform some complicated ternary logic functions, a series of circuit simulations were conducted in this case study. The specific cascaded ternary logic function and the relevant simulation results are provided below. Figure 8a demonstrates the specific schematic diagram and the corresponding truth table, the ternary logic function and the final circuit simulation results are provided in Figure 8b. Based on the obtained input-output relationship, it is clear that the proposed memristor-CMOS circuit could perform this cascaded ternary logic function. In particular, the final input-output relationship was the same as that of the ternary NOR logic gate. Namely, the ternary logic function could be rewritten as:

Case Study 2
To demonstrate that the proposed logic circuit could perform some complicated ternary logic functions, a series of circuit simulations were conducted in this case study. The specific cascaded ternary logic function and the relevant simulation results are provided below. Figure 8a demonstrates the specific schematic diagram and the corresponding truth table, the ternary logic function and the final circuit simulation results are provided in Figure 8b. Based on the obtained input-output relationship, it is clear that the proposed memristor-CMOS circuit could perform this cascaded ternary logic function. In particular, the final input-output relationship was the same as that of the ternary NOR logic gate. Namely, the ternary logic function could be rewritten as: Function 1 = In 1 + In 2 · In 1 ·In 2 = In 1 + In 2 (15) Notably, Equation (15) was also established for the binary logic.

Case Study 2
To demonstrate that the proposed logic circuit could perform some complicated ternary logic functions, a series of circuit simulations were conducted in this case study. The specific cascaded ternary logic function and the relevant simulation results are provided below. Figure 8a demonstrates the specific schematic diagram and the corresponding truth table, the ternary logic function and the final circuit simulation results are provided in Figure 8b. Based on the obtained input-output relationship, it is clear that the proposed memristor-CMOS circuit could perform this cascaded ternary logic function. In particular, the final input-output relationship was the same as that of the ternary NOR logic gate. Namely, the ternary logic function could be rewritten as: In In In +In (15) Notably, Equation (15) was also established for the binary logic.  Table   In1 Output

Conclusions
This study mainly investigated memristor-based unbalanced ternary logic implementation. Specifically, the spintronic memristor with its unique memristance variation rule was briefly discussed. Then, a hybrid memristor-CMOS based circuit was designed for the implementation of the basic ternary logic gates (including the NAND, NOR, AND, and OR gates). Compared with the existing ternary logic implementations, the proposed method had advantages in terms of circuit construction, response time, robustness, functionality, load capacity, and cascaded capacity. Finally, all these above-mentioned merits were verified by a series of circuit simulations.

Conclusions
This study mainly investigated memristor-based unbalanced ternary logic implementation. Specifically, the spintronic memristor with its unique memristance variation rule was briefly discussed. Then, a hybrid memristor-CMOS based circuit was designed for the implementation of the basic ternary logic gates (including the NAND, NOR, AND, and OR gates). Compared with the existing ternary logic implementations, the proposed method had advantages in terms of circuit construction, response time, robustness, functionality, load capacity, and cascaded capacity. Finally, all these above-mentioned merits were verified by a series of circuit simulations.