Minimum Distance Optimization with Chord Edge Growth for High Girth Non-Binary LDPC Codes

Short or moderate-length non-binary low-density parity-check (NB-LDPC) codes have the potential applications in future low latency and high-reliability communication thanks to the strong error correction capability and parallel decoding. Because of the existence of the error floor, the NB-LDPC codes usually cannot satisfy very low bit error rate (BER) requirements. In this paper, a low-complexity method is proposed for optimizing the minimum distance of the NB-LDPC code in a progressive chord edge growth manner. Specifically, each chord edge connecting two non-adjacent vertices is added to the Hamiltonian cycle one-by-one. For each newly added chord edge, the configuration of non-zero entries corresponding to the chord edge is determined according to the so-called full rank condition (FRC) of all cycles that are related to the chord edge in the obtained subgraph. With minor modifications to the designed method, it can be used to construct the NB-LDPC codes with an efficient encoding structure. The analysis results show that the method for designing NB-LDPC codes while using progressive chord edge growth has lower complexity than traditional methods. The simulation results show that the proposed method can effectively improve the performance of the NB-LDPC code in the high signal-to-noise ratio (SNR) region. While using the proposed scheme, an NB-LDPC code with a quite low BER can be constructed with extremely low complexity.


Introduction
The design of efficient short codes has attracted widespread interest due to the emergence of applications requiring high reliability and low latency data transmission [1,2]. The low-density parity check (LDPC) codes, which were first proposed by Gallager et al. [3] and rediscovered by MacKay and Neal [4,5], have performance close to the Shannon limit as the code length approaches infinity [6]. For short or moderate code lengths, non-binary low-density parity-check (NB-LDPC) codes exhibit better error-correction capabilities than binary LDPC codes in certain cases [7,8]. The construction of NB-LDPC codes can adopt algebraic or graph theory methods. The algebraic methods for constructing non-binary quasi-cyclic LDPC codes that are based on finite Euclidean geometric planes and array masks were studied by Zhou et al. [9], Huang et al. [10] and Peng et al. [11]. The codes that were constructed by these methods can be effectively encoded and they have excellent performance on the Additive White Gaussian Noise (AWGN) channel. The design methods of non-binary protograph-based LDPC codes with excellent performance were studied by Divsalar et al. [12], Dolecek et al. [13] and Wang et al. [14].
The design of an LDPC code with excellent performance in the high signal-to-noise ratio (SNR) region is challenging due to the presence of the error floor. It has been found that the error floor is largely attributed to the effect of error-prone graph structures in the Tanner graph of the code, such as stopping sets and trapping sets [15][16][17]. Therefore, much work has been devoted to the with variable nodes of the degree of two and the Hamiltonian graph representation of these codes are described. Subsequently, the cycles and the FRC of the cycles are introduced, which are the foundations of the proposed design method. Finally, the method proposed by Poulliat et al. [15] that improves the error floor while using the algebraic properties of cycles and stopping sets is briefly presented.

Parity-Check Matrix and Hamiltonian Graph
The NB-LDPC code that is defined on the high-order Galois field with a sparse parity-check matrix is generally described by a Tanner graph. Furthermore, an NB-LDPC code with a variable node degree of two can be represented using a simple graph obtained by omitting the variable nodes in its Tanner graph. Consider a graph G(V, E) with neither loops nor multiple edges, where V represents a non-empty set of vertices and E represents a set of edges. The Hamiltonian cycle in graph G is a cycle that passes once through all of the vertices in graph G, and the Hamiltonian graph denotes a graph with at least one Hamiltonian cycle. The Hamiltonian graph forms of an NB-LDPC code are presented in Figure 1a. For a three-regular graph with eight vertices, the original vertex is taken as a check node, a vertex is inserted as a variable node on each edge of the graph, and the non-zero elements of the Galois field GF(q), where q is the order of the field, are added to the edges connecting these two types of nodes. Subsequently, the parity-check matrix and Tanner graph of the NB-LDPC code that is shown in Figure 1b,c, respectively, can be obtained. If the Hamiltonian graph has the regular vertex degree of d c , then a (2, d c )-regular LDPC code can be constructed with the variable node degree of 2 and check node degree of d c in the associated Tanner graph.   In Figure 1, the representation of the cycle is given. In the Tanner graph, a cycle represents a closed-loop that consists of different vertices and edges, and the cycle length is the number of edges or vertices that it contains. The girth g denotes the length of the shortest cycle in the entire graph. The vertices in the Hamiltonian graph correspond to check nodes, and the actual length of the cycle is twice the number of passed vertices. The shortest cycle length in the Hamiltonian graph that is shown in Figure 1 is four, and the corresponding Tanner graph has a girth of eight. Section 2.2 describes the influence of girth and cycles on the performance of the code in detail.
The NB-LDPC code that is constructed based on the Hamiltonian graph can not only obtain good girth characteristics, but also be implemented with the linear encoding. Many efficient encoding structures have been developed while using the recursive encoding methods that are suitable for particular graphs [22][23][24]. In these methods, the matrix mapped from the Hamiltonian cycle can be modified, as shown in Equation (1).
Let [s, p] be a legal codeword, where s = [s 0 , s 1 , · · · , s n−m−1 ] and p = [p 0 , p 1 , · · · , p m−1 ] are the information symbol vector and check symbol vector, respectively. The NB-LDPC code with [H I , H P ] as the parity-check matrix can be encoded by the recursive method that includes the following steps: Step1 In the above steps, u = [u 0 , u 1 , · · · , u m−1 ] is the intermediate result, and u = H P · p T = H I · s T . The vector u can be calculated according to the matrix H I and the information symbol vector s. The (m − 1) non-zero elements α k 1,0 , α k 2,0 , · · · , α k m−1,0 in the matrix H P are stored to calculate each check symbol p i in the described recursive steps. The method described requires less calculation and storage resources when compared with traditional encoding methods. Therefore, the NB-LDPC code with the parity-check matrix in the form shown in Equation (1) can be efficiently encoded in a recursive manner.

Cycle and Cycle Cancellation
The cycle in the Tanner graph is related to the sub-optimality of the iterative decoding. The length of the shortest cycle where a node is located represents the shortest path or minimum number of iterations a node's message needs to travel back to the node itself. When the number of iterations increases, the message propagates to other parts of the graph. Therefore, enlarging the girth of an LDPC code helps to improve the iterative decoding performance. Figure 2a shows a Hamiltonian graph that is composed of 26 vertices and 26 chord edges, and it can be used to derive a parity-check matrix with a code rate of 1/2. In this figure, the shortest cycle length is six, i.e., the girth of the derived parity-check matrix is 12.
Although there are no short cycles in the parity-check matrix constructed while using the high-girth Hamiltonian graph, in the case of an improper configuration of non-zero entries, the existence of cycles can generate low-weight codewords, thereby reducing the minimum distance and introducing a higher error floor. Fortunately, it is possible to prevent the cycle from generating low-weight codewords by ensuring that the determinant value of the matrix corresponding to the cycle is not equal to zero, which means that the cycle is cancelled [15]. Let α 1 , α 2 , · · · , α l be the non-zero elements of Galois field GF(q) related to a cycle of length l, and the matrix form of the cycle is equivalent to the l 2 × l 2 square matrix that is expressed in Equation (2).
The determinant of C d is given by The multiplication and addition operations are all defined on Galois field GF(q). Subsequently, the FRC of the cycle can be expressed as Furthermore, by applying the addition property of the finite field, the FRC is equivalent to Figure 2b shows the FRC of a cycle of length 12. Therefore, a cycle can avoid the generation of low-weight codewords by appropriately configuring its corresponding non-zero elements to satisfy the FRC.

Optimization Method of Minimum Distance Based on the Binary Image
A method of selecting and configuring non-zero elements that is based on binary images for optimizing NB-LDPC codes with the column weight of two was proposed by Poulliat et al. [15]. Based on the minimum distance of the equivalent binary code, the non-zero entries in each row were carefully selected, which proved to improve the performance in the waterfall region. Furthermore, the structure of the relevant Tanner graph was considered to lower the error floor. For the parity-check matrix of a code, the columns defining the minimum distance are located on symbols belonging to the shortest cycles and the associated stopping sets. Therefore, a method using the algebraic properties of cycles and stopping sets was given for improving the minimum distance of the binary image of the code.
Specifically, an iterative and row-wise optimization procedure was performed for the purpose of the cycle cancellation and the stopping set mitigation. Assume that R and S denote the set of optimized non-zero entries for a row and the set of the smallest stopping sets with good minimum distance, respectively. The length of the cycle was assumed to lie in the range from the girth g to a given length l max . The cycle optimization process is as follows.
Initialization: randomly select elements from set R and its permutations as the rows of the check matrix, and define A as the row label set of the parity-check matrix H to be optimized.
Step 1: initialize A as all row labels of matrix H.
Step 2: randomly select a row label a in A.
Step 3: select the element from R and its permutation for ath row that maximizes the number of cancelled cycles of length l, where l indicates the length of the shortest cycles that have not been cancelled.
Step 4: remove a from A. If all cycles of length l satisfy the FRC, then l = l + 2, and go to Step 1; otherwise, judge whether there are elements in set A; and, if there are some of them, go to Step 1; otherwise, go to Step 2.
End of cycle optimization: when no more cycles can be cancelled, the cycle optimization process ends.
After the cycle cancellation process, the process that is described above was used to optimize the cycles with length greater than l max continuously from the perspective of the stopping set. In order to optimize the stopping set, the selection criterion of non-zero elements for a row was to maximize the number of cancelled loops and the minimum distance of the stopping set.
In the cycle optimization method that was proposed by Poulliat et al. [15], a row of non-zero elements are temporarily determined based on the number of cycles associated with the row that do not meet the FRC. The idea of iterative optimization can cancel cycles to a large extent. However, all cycles related to the selected row need to perform the FRC check, which means that a large number of cycles should be checked repeatedly, increasing the complexity. According to the characteristics of ultra-sparse graphs, a method for configuring non-zero entries with the progressive chord edge growth is proposed in this paper, which can effectively reduce the number of FRC checks.

Minimum Distance Optimization Using Progressive Chord Edge Growth
Based on the high-girth graph [22][23][24] and a set of optimized non-zero entries that are associated with a row [15], a method of configuring non-zero entries in the manner of progressive chord edge growth is proposed to increase the minimum distance of NB-LDPC codes. The non-zero elements are selected for each chord edge based on the FRC of the cycles. Only those cycles containing the newly-added chord edges are checked, which effectively reduces the number of cycles that need to perform a FRC check. Furthermore, a simple variant of the proposed method is applied to optimize the NB-LDPC codes with an efficient encoding structure.

Proposed Progressive Chord Edge Growth (PCEG) Method
Assume that, in the Hamiltonian graph G that is composed of m vertices and n edges, the associated parity-check matrix is expressed as H = [H I , H P ].Let the sets of vertices and edges composing the Hamiltonian graph be V= {v 1 , v 2 , · · · v m } and E= {e 1 , e 2 , · · · e n } respectively, where v i (i = 1, 2, · · · , m) and e j (j = 1, 2, · · · n) correspond to the ith row and jth column in matrix H, respectively. The first m edges in E, which construct set E C , form a Hamiltonian cycle with a length of 2 × m. The remaining edges in E denote chord edges that connect two non-adjacent vertices in the Hamiltonian graph in turn. The process of progressive chord edge growth of a 26-vertex Hamiltonian graph is illustrated in Figure 3, where M 27 a , M 28 a , · · · , M 52 a represent the total number of cycles, and M 27 c , M 28 c , · · · , M 52 c represent the number of the cycles associated with the newly added chord edge. Although the cycles included in the Hamiltonian graph are complex globally, the cycles related to the newly added chord edge are limited from the perspective of the progressive chord edge growth. As mentioned before, this paper considers cycles with a length l having the value from girth g to a given length l max . In the process of progressive chord edge growth, the number of cycles that do not satisfy the FRC in the cycles introduced by the newly added chord edge is denoted as N l≤l max j .
The proposed non-zero element configuration method for making the cycles meet the FRC will be described in detail in the following.
According to the order of growing chord edges, the allocation of non-zero elements is divided into two main steps. One is the selection of non-zero elements in set E C , and the other is the selection of non-zero elements that correspond to each chord edge. Figure 4 shows the specific process of configuring non-zero entries with progressive chord edge growth.
During the initialization process, the non-zero elements on the Hamiltonian cycle are determined. Because there is no short cycle in E C , the non-zero elements chosen from set R of optimal row entries [15] can be randomly configured. Specifically, two randomly selected elements from R are assigned to two non-zero positions that correspond to vertex v i on the Hamiltonian cycle. The set of unselected non-zero elements corresponding to vertex v i is denoted as R(v i ), and the number of elements in R(v i ) is denoted as n(v i ).
After selecting the corresponding non-zero elements on the Hamiltonian cycle, the non-zero elements of each chord edge are determined, in turn, according to the remaining optional non-zero elements set R(v i ) for each vertex. Starting from edge e m+1 , the two vertices that are connected by edge e m+1 are denoted as v ). Subsequently, the number N l≤l max m+1 of cycles not satisfying the FRC among all of the cycles related to edge e m+1 are determined. Finally, the configurations that satisfy N l≤l max m+1 = 0 are retained, and the configuration of non-zero entries that correspond to the next chord edge e m+2 is performed. This process continues until the configuration of the non-zero entries of the last chord edge is completed.
Based on the Hamiltonian graph consisting of m vertices and n edges, the design process of the NB-LDPC codes in the proposed progressive chord edge growth manner is summarized, as follows.
Initialization: randomly select non-zero elements from the optimized row set R, assign them to the non-zero positions corresponding to the Hamiltonian cycle, and initialize the index of the chord edge j = m + 1.
Step 1: add the chord edge e j to the Hamiltonian cycle, and obtain the subgraph G j composed of the Hamiltonian cycle and the added (j − m) chord edges.
Step 2: according to the remaining optional non-zero elements of the vertices connected to the chord edge e j , select the non-zero elements corresponding to the chord edge e j , in order that the cycles with the length not greater than l max in the subgraph G j related to the chord edge e j all satisfy the FRC.
Step 3: if there is no non-zero element that meets the condition, go to the initialization process; otherwise, judge whether the chord edge index j is equal to n, and if j = n, go to Step 4; otherwise, j = j + 1, and go to Step 1; Step 4: from all of the non-zero element configurations that meet the conditions, select the configuration that violates less FRC criterion, and finally obtain the optimized parity-check matrix of the NB-LDPC code.  In the configuration of the non-zero entries for each chord edge, there are some subtle points that need further explanation. First, if there is no configuration that meets N l≤l max j = 0 after traversing all optional non-zero elements of edge e j , the non-zero elements that correspond to E C are re-allocated and the non-zero elements are re-configured from the first chord edge. Second, if there are multiple choices for configuring the non-zero entries corresponding to the last chord edge, that is, multiple parity-check matrices satisfying N l≤l max n = 0 are obtained, then the FRC check will be performed on the cycles with a cycle length that is greater than l max , and the matrix that has the minimum number of cycles not satisfying the FRC is selected. Third, if there are a large number of candidate configurations of non-zero entries for a chord edge, then one candidate configuration is randomly reserved, which is, the non-zero elements that are related to the added chord edges are fixed. This effectively prevents excessive memory usage due to the rapid increase in the number of optional configurations.

Progressive Chord Edge Growth Optimization for Efficient Encoding
The proposed method for configuring non-zero entries in a progressive chord edge growth manner can be used to generate NB-LDPC cycle codes with an arbitrary size, as long as a Hamiltonian graph is provided. After slight modification, the proposed method can also be applied to construct NB-LDPC codes with linear-time-encoding.
Based on the study by Chen et al. [24], a parity-check matrix with a bidiagonal structure in the last m columns and α 0 in the principal diagonal can be efficiently encoded. Therefore, the proposed method can be used to construct NB-LDPC codes with low encoding complexity after two minor modifications. The first one is to modify the Hamiltonian graph, so that it can be mapped to a matrix with a bidiagonal structure, which is, the Hamiltonian graph after disconnecting the first vertex and edge e m is mapped to be the parity-check base matrix. The second is to modify the non-zero element configuration corresponding to the Hamiltonian cycle. When selecting non-zero elements of the Hamiltonian cycle, the non-zero entry corresponding to edge e j and vertex v j is fixed as α 0 , and the non-zero entries that correspond to edge e j and vertex v j+1 are randomly selected from R. These two modifications are applied to the initialization step in the method described in Section 3.1, thereby enabling the designed code to have an efficient encoding structure.

Complexity Analysis and Design Examples
In this section, the method for constructing NB-LDPC codes while using the progressive chord edge growth strategy is comprehensively analyzed. The complexity of the method is first analyzed in terms of the number of cycles and the number of candidate configurations for each chord edge. Subsequently, several examples of NB-LDPC codes constructed using the proposed method are shown. The distribution of cycles that do not meet the FRC is counted, and the performance of the designed codes is evaluated through computer simulation.

Complexity Analysis
This paper aims to design a method for configuring non-zero entries that are based on the FRC of a cycle, thus optimizing the global minimum distance of the NB-LDPC codes. For finite length codes, optimizing the allocation of non-zero entries in the parity-check matrix is a complicated permutation and combination problem. In addition, the number of cycles in the graph associated with the code is large, even for the ultra-sparse code, which increases the time complexity of the optimization process. In this subsection, the Hamiltonian graph shown in Figure 2 is first taken as an example to analyze the complexity of the proposed method in detail. The number of check nodes and number of chord edges are both 26, and the maximum cycle length considered is 16. Furthermore, when considering the design complexity of high code rate NB-LDPC codes, a more general discussion is provided to evaluate the complexity for designing NB-LDPC codes with any code rate.
First, with the proposed method, the number of candidate non-zero entries for each chord edge is limited. The proposed method traverses the optional non-zero entries of each chord edge in a spanning tree manner and deletes nodes that do not satisfy the conditions. As the chord edge increases, a large number of branches that do not meet the criteria are deleted, thus avoiding the exponential growth of the number of branches. The number of branches is further reduced by applying the idea of grouping truncation. That is, after completing the configuration of non-zero entries for a certain chord edge, one of the candidate configurations of non-zero entries is randomly reserved. For comparison, Figure 5 also shows the number of candidate configurations for each row while using the iterative and row-wise optimization method that was proposed by Poulliat et al. [15]. Because the degree of the check node is four, a set of non-zero entries derives 24 different permutations. In the case of using three different sets of non-zero entries, there are 72 different permutation options for each row. Obviously, the number of considered configurations in the proposed method is much smaller than that by Poulliat et al. [15]. Second, the proposed method for allocating non-zero entries in the progressive chord edge growth manner can effectively reduce the number of cycles that need FRC check compared with similar optimization methods. Figure 6 shows the number of associated cycles for processing each chord edge. The number of cycles that require FRC check gradually increases to about 140 as the chord edge grows while using the proposed method, while the number of considered cycles for each row using the scheme designed by Poulliat et al. [15] is about 240. Applying the progressive chord edge growth strategy, the FRC check is only performed on the cycles that contain the newly added chord edge in the current sub-graph instead of the cycles containing the selected chord edge in the entire graph. Therefore, the number of associated cycles increases as the chord edge grows. Using the iterative and row-wise method, the cycles containing the selected check node in the entire graph are FRC checked, which results in the uniform distribution of the number of considered cycles for optimizing each row. For the last chord edge, the FRC check is performed on the cycles, including the chord edge in the entire graph, and the number of the cycles is still smaller than the number of cycles that are related to a row. This is due to the fact that the column weight of the LDPC code is generally smaller than the row weight, so the number of cycles that are related to a column is smaller than the number of cycles related to a row. The total number of cycles that need FRC check is shown in the legend part of Figure 6. It can be seen that, when compared with the iterative and row-wise optimization method, the proposed method reduces the number of cycles requiring the FRC check from 6634 to 884.
Above, the complexity of the proposed method is analyzed in terms of the number of candidate configurations for each chord edge and the number of cycles that require the FRC check. Combining these two aspects, the number of FRC checks is counted, as shown in the Figure 7. The number of FRC checks performed while using the proposed method is quite small. For the example given, a total of 477,688 FRC checks are required for completing one time optimization of the entire parity-check matrix using the scheme proposed by Poulliat et al. [15], while only 11,810 FRC checks are required using the proposed progressive chord edge growth method. Therefore, the proposed method has much lower complexity.  Using the above analysis steps, the design complexity of the proposed method for higher code rate NB-LDPC codes is further analyzed. Table 1 shows the complexity of the optimization for the NB-LDPC code with a code rate of 3/4 and code length of 96 symbols. The row weight d c and column weight d v of the adopted base matrix are eight and two, respectively. First, using the method proposed by Poulliat et al. [15], the number of candidate configurations for non-zero elements in each row is the number of permutations of d c elements. For the case of d c = 8, there are 40,320 permutations. The number of rows of the base matrix is 24, and the number of permutations for all rows is 40,320 × 24, which is, 967,680. The non-zero elements of 72 chord edges need to be configured while using the proposed scheme; however, the total number of candidate configurations is less than the iterative and row-wise method. Subsequently, the number of cycles that need to perform FRC check is compared. In the manner of progressive chord edge growth, the cycles for each added chord edge are different. Using the row-wise optimization, there are a large number of cycles that are repeatedly processed when considering that the cycles are in the entire graph. Therefore, fewer cycles need to be checked using the proposed method. Finally, Table 1 lists the number of FRC checks. The number of FRC checks for each row or each chord edge is the result of multiplying the number of cycles to be processed and the number of candidate configurations for each row or each chord edge. It can be seen that more FRC checks are required for the case of a larger check node degree, and the number of FRC checks using the proposed method is lower than that of the iterative and row-wise optimization. In general, for the design of NB-LDPC codes with arbitrary code length and code rate, it is difficult to accurately calculate the number of candidate configurations for non-zero elements in each row or chord edge without specific operations. Nevertheless, the application of truncation can prevent a sharp increase in the number of candidate configurations. As far as the cycles are concerned, the number of related cycles while using the proposed scheme is less than that of the iterative and row-wise optimization, due to the idea of progressive chord edge growth avoiding the repeated processing of cycles. Therefore, the proposed method has lower complexity, even if the number of chord edges is larger than that of rows in the case of high code rate.

Design Examples
Several examples of finite-length NB-LDPC codes constructed using the proposed method are presented. All of the codewords are simulated on a binary input additive white Gaussian noise (AWGN) channel while using binary phase shift keying (BPSK) modulation, and decoded by the fast Fourier transform belief propagation (FFT-BP) algorithm [6]. The maximum number of iterations is set to be 50. In addition, all of the simulations terminated with 50 erroneous codewords (frames).

Example 1.
Based on the Hamiltonian graph with 26 vertices that are shown in Figure 2, the NB-LDPC codes with a code length of 312 bits and a code rate of 1/2 defined on GF(64) are constructed. The local minimum Hamming distance that is associated with a check node is used as a criterion to determine the set of non-zero entries for each row. One set of non-zero entries over GF(64) provided by Poulliat et al. [15] is applied to the proposed method. The non-zero entry set R = {α 37 , α 22 , α 9 , α 0 }, with a minimum distance of 3 and a weight enumerator coefficient of 20, is selected. Subsequently, the proposed method is performed to configure the non-zero entries for the parity-check matrix. The proposed method and a simplified version of the proposed method are, respectively, used to construct NB-LDPC codes. These two versions are called PCEG and S-PCEG, respectively. For the design example using the S-PCEG method, after completing the search for the non-zero entries of the sixth chord edge, one candidate configuration is reserved. In addition, the proposed method is applied to the optimization of the NB-LDPC code with an efficient encoding structure that was proposed by Chen et al. [24]. Based on the same basic graph and non-zero elements, NB-LDPC codes are randomly constructed for comparison. Table 2 shows the cycle distributions of the constructed codes. The girths of these NB-LDPC codes are all 12, and the numbers of cycles with lengths from 12 to 20 that do not satisfy FRC are listed. Using the proposed method, the cycles less than 20 in length are cancelled, which improves the performance to a certain extent. For cycles with a length of 20, the number of cycles not meeting FRC is further reduced. The similar effect of cycle cancellation is obtained in the parity-check matrix with an efficient encoding structure [24].  Figures 8 and 9 shows the performance simulation results of different constructed codes. Because there is no short cycle not satisfying the FRC, the codes constructed by the proposed method have performance advantages in the high signal-to-noise ratio (SNR) region when compared with the codes constructed randomly with the same code parameters. The proposed method has the potential to construct NB-LDPC codes that meet the requirements of low bit error rate (BER) or frame error rate (FER). Applying the proposed method to the NB-LDPC code with an efficient encoding structure proposed by Chen et al. [24], an NB-LDPC code with low encoding complexity and superior performance can be constructed.
Furthermore, the performance of the code constructed while using the proposed method under different decoding iterative number is analyzed, as shown in Figure 10. It can be observed that, when the iteration number is larger than 20, the code can achieve significant error correction performance. Therefore, 20 iterations may be proper for our designed codes and 10 iterations is not so enough. Thus, in this design, we suggest use 20 iterations, which can achieve a relatively good trade-off of performance and latency. When considering the trade-off between decoding complexity (or decoding latency) and error correction performance, 20 iterations are feasible for the proposed codes.

Example 2.
In order to analyze the feasibility of the proposed method for constructing NB-LDPC codes with different code rates, the NB-LDPC codes with the code length of 576 bits are constructed, and their code rates are 1/2 and 3/4, respectively. The check node degree of the codes with the code rate of 1/2 is four, and the check node degree of codes with the code rate of 3/4 is eight. For codes with the code rate of 1/2, based on the positions of non-zero entries in the parity-check matrix that was provided by Helmling et al. [25], the proposed method is performed to configure a non-zero value for each position. The NB-LDPC code that was provided by Helmling et al. [25], which has been designed using the cycle optimization proposed by Poulliat et al. [15], is compared with the designed code. In addition, two codes with the same parameters are randomly constructed for comparison. For codes with the code rate of 3/4, one set of optimized non-zero element set {α 0 , α 6 , α 13 , α 21 , α 28 , α 36 , α 44 , α 54 } [26] is used for the non-zero entries that are associated with each check node. The non-zero positions of codes with the same code rate are the same, and the non-zero values are different.
The cycle distributions of the NB-LDPC codes with the two code rates are given in Tables 3 and 4. It can be seen that the proposed method cancels all the cycles less than 20 in length for the codes with the code rate of 1/2. The girth of the codes with a code rate of 3/4 is six and the maximum considered cycle length is 12. The proposed method cancels all cycles with the length of less than 12 and greatly reduces the number of cycles with the length of 12 that do not satisfy the FRC criterion. Figures 11 and 12 show the corresponding performance simulation results. It can be observed that the codes with more cancelled cycles can obtain better performance. Table 3. Cycle distributions of NB-LDPC codes over GF(64) with the code length of 576 bits and the code rate of 1/2.

Conclusions
A low-complexity method that is based on progressive chord edge growth is developed for the configuration of non-zero entries, which can construct NB-LDPC codes with a low error floor. All of the candidate configurations of non-zero entries are traversed for each chord edge in turn, and the configurations that make the cycles in the current subgraph meet the FRC are retained. For a chord edge with a large number of eligible configurations, the limitation on the number of these configurations effectively reduces the memory usage. In addition, a slightly modified version of the proposed method is used to construct the NB-LDPC code with an efficient encoding structure. The analysis results show that the proposed method requires fewer FRC checks than the traditional cycle cancellation method, thus achieving lower complexity. Several design examples prove that our method can construct NB-LDPC codes with a large number of cancelled short cycles, thus effectively lowering the error floor. For future investigation, the idea of the proposed progressive chord edge growth may be applied to the optimization of other structures in NB-LDPC codes.

Conflicts of Interest:
The authors declare no conflict of interest.