Improved Finite Set-Predictive Torque Control of PMSM Fed by Indirect Matrix Converter with Discrete Space Vector Modulation

: This study presents ﬁnite set-predictive torque control (FS-PTC) with discrete space vector modulation (DSVM) for indirect matrix converter (IMC)-fed permanent magnet synchronous motors (PMSMs). The implementation of FS-PTC with DSVM in an IMC requires high computation time due to the large number of synthesized voltage vectors (VVs). To reduce computation time caused by considering all VVs, a new preselection strategy is proposed to reduce the computational numerations from 37 to 6 VVs. The proposed algorithm can reduce torque and ﬂux ripples and achieve robust characteristics against parameter variations. Additionally, the increased degree of VVs can improve the correlation between the rectiﬁer and inverter sides of the IMC. The e ﬀ ectiveness of the proposed method is veriﬁed by simulation and experimental results.


Introduction
AC/AC power converter systems without a capacitive or inductive DC-link have become more attractive recently in high-performance motor drive applications due to their high efficiency and low weight and volume. There are various topologies for these AC/AC systems reported in the literature [1], of which, the matrix converter (MC) is one of the most attractive AC/AC converter topologies. The MC has many prominent features, including a unity power factor at the input terminal, sinusoidal input and output current, and increased power density. MCs fall into two main categories: direct matrix converters (DMCs) and indirect matrix converters (IMCs) [2][3][4][5][6][7][8][9]. Compared with DMCs [2,3], IMCs have distinguishing attributes such as simple implementation, safe commutation, and bidirectional power flow capabilities. IMCs have two stages of operation: the current source rectifier (CSR) stage and a voltage source inverter (VSI) stage [7]. Nevertheless, unlike with back-to-back converters, the CSR and VSI stages do not have decoupled control because there is no intermediate capacitor [9]. Hence, if the VSI is not well-controlled, the performance of the CSR and VSI stages can deteriorate.
Several control techniques have been reported in the literature for the VSI stage of an IMC [9][10][11][12]. Among these control methods is the finite set-model predictive control (FS-MPC), which is grouped into two main schemes: finite set-predictive current control (FS-PCC) [12] and finite set-predictive torque control (FS-PTC) [9]. The FS-PCC technique was first introduced by [13] for a system comprising a resistance and inductance load, in which the cost function is the error difference among the reference and forecasted values of the output current. Several studies of this method have been applied to the

Modulation Technique for Grid-Side Control of IMC
The CSR is responsible for regulating the AC source from the grid side using a simple modulation method to offer a unity power factor. Figure 2 depicts the space-vector diagram of the CSR, which comprises six regions (I-VI) with six active vectors (V1-V6) and three passive vectors (V7-V9), applied according to the switching pattern of the CSR to represent the rectified DC voltage. A commutation example of CSR is when the reference current ( I  ) lies in Sector I, as illustrated in Figure 2. The reference current I  in this case is determined by the adjacent active vectors, V1 and V6.
Hence, the top switch of the u-phase (SuT) is clamped during the whole sampling cycle. Meanwhile, the bottom switches of the v-phase and w-phase (SvB and SwB) are switched on within part of the sampling cycle in turns. Thus, the line-to-line voltages (−vwu and vuv) of the grid input are applied to the DC link in sequence. For this purpose, duty ratios (dx, dy) must be calculated to find the turn-on time of the v-phase and w-phase. Initially, the reference current can be expressed as: [ , , ] [cos , cos , cos ] where Im indicates the value of the reference current vector. u  , v  , and w  are the phase angles of each current vector ( u I  , v I  , w I  ), respectively. Because the two voltage vectors (V1 and V6) are used to generate the reference current vector, the upper u-phase switch is held within the sampling interval. Consequently, the duty ratios (dx and dy) of the lower v-and u-phase switches are defined as:

Modulation Technique for Grid-Side Control of IMC
The CSR is responsible for regulating the AC source from the grid side using a simple modulation method to offer a unity power factor. Figure 2 depicts the space-vector diagram of the CSR, which comprises six regions (I-VI) with six active vectors (V 1 -V 6 ) and three passive vectors (V 7 -V 9 ), applied according to the switching pattern of the CSR to represent the rectified DC voltage. A commutation example of CSR is when the reference current (I * ) lies in Sector I, as illustrated in Figure 2. The reference current I * in this case is determined by the adjacent active vectors, V 1 and V 6 . Hence, the top switch of the u-phase (S uT ) is clamped during the whole sampling cycle. Meanwhile, the bottom switches of the v-phase and w-phase (S vB and S wB ) are switched on within part of the sampling cycle in turns. Thus, the line-to-line voltages (−v wu and v uv ) of the grid input are applied to the DC link in sequence. For this purpose, duty ratios (dx, dy) must be calculated to find the turn-on time of the v-phase and w-phase. Initially, the reference current can be expressed as: where I m indicates the value of the reference current vector. θ u , θ v , and θ w are the phase angles of each current vector (I * u , I * v , I * w ), respectively. Because the two voltage vectors (V 1 and V 6 ) are used to generate the reference current vector, the upper u-phase switch is held within the sampling interval. Consequently, the duty ratios (d x and d y ) of the lower vand u-phase switches are defined as: The average amount of DC voltage (v DC.avg ) obtained from the CSR commutation is necessary to modulate the output voltage in the VSI of the IMC. Hence, based on Equations (1) and (2), v DC.avg can be computed using the line-to-line voltage and the duty ratios as: where φ i = θ u − ρ u . ρ u and v m are the phase and magnitude of the grid VV, respectively. φ i is the power factor angle. The same processes in Equations (2) and (3) used to find the averaged voltage can be applied for the other CSR sectors. Notably, the maximum voltage transfer ratio, which equals 0.866, can be obtained as the phases of the grid and reference currents are equaled. Table 1 presents where Im indicates the value of the reference current vector. u  , v  , and w  are the phase angles of each current vector ( u I  , v I  , w I  ), respectively. Because the two voltage vectors (V1 and V6) are used to generate the reference current vector, the upper u-phase switch is held within the sampling interval. Consequently, the duty ratios (dx and dy) of the lower v-and u-phase switches are defined as:

Fundamental FS-PTC of PMSM
The discretized equations of PMSM for stator flux space-vector λ s (k) and torque T e are calculated based on the following expressions: where indicates the permanent magnet flux linkage, L s signifies the stator self-inductance, p is the number of pole pairs, and T e is the electrical torque. Thus, the predicted stator flux linkage can be derived as: where v s = v sα v sβ is the stator voltage, and R s indicates the stator resistance. Hence, the predicted stator current can be given as: where: where ω r is the rotor speed of the motor, and T s is the sampling time. According to Equation (8), the electromagnetic torque can be predicted based on the predicted value of flux and current as: where k and k + 1 signify the current and forecasting sampling discrete cycles, respectively. The 2L-VSI consists of eight VVs, which are classified into six active VVs (v 1 -v 6 ) and two zero VVs (v 0 and v 7 ), as displayed in the space vector voltage illustration of Figure 3a. To determine the optimal VV amongst the candidate VVs, designing an appropriate cost function is required as below: where T * is a torque reference and λ * is the flux reference at the kth sampling cycle. Q is the weighting factor.
Electronics 2020, 9, x FOR PEER REVIEW 5 of 18 (8) where k and k + 1 signify the current and forecasting sampling discrete cycles, respectively. The 2L-VSI consists of eight VVs, which are classified into six active VVs (v1-v6) and two zero VVs (v0 and v7), as displayed in the space vector voltage illustration of Figure 3a. To determine the optimal VV amongst the candidate VVs, designing an appropriate cost function is required as below: (9) where T  is a torque reference and   is the flux reference at the kth sampling cycle. Q is the weighting factor.

Proposed FS-PTC For An IMC-Fed PMSM
As previously mentioned, the VSI side of the IMC is similar to the well-known two-level VSI. Thus, it has a limitation in the switching vectors (i.e., the eight VVs, as shown in Figure 3a). However, if a single switching vector is used for the full sampling interval, this will result in a variable switching frequency and an increase in flux and torque ripples. Additionally, the VV cannot be generated with whole sampling time Ts into the inverter side of the IMC circuit to ensure safe commutation and optimized utilization of the rectified averaged DC-link voltage. Because neither the CSR nor the VSI has decoupled control due to the elimination of the capacitor, carrier-based PWM modulation is used to correlate between the rectified DC-link voltage and output voltage of the inverter. Notably, the slopes of the carrier signal for the inverter side are altered in every sampling interval due to the deviation of the averaged DC voltage.
To achieve a stable output voltage within a sampling cycle, the switching arrangement of the power converter must associate the switching patterns of the CSR and VSI stages. Hence, to eliminate the limitation in the switching vectors in the conventional inverter stage of the IMC and to avoid the commutation problem, the DSVM strategy is proposed to increase virtual VVs and, hence, to enlarge the voltage degrees of freedom for FS-PTC of PMSM.

Synthesis of Virtual Voltage Vectors
In this study, a DSVM strategy can be applied using [19]. Hence, the space vector diagram (SVD) is grouped into concentric hexagonal diagrams (CHDs) with various sized VVs. Each CHD consists of several generated virtual VVs in addition to the real VVs. The number of virtual VVs in each CHD relies on its index digit, as provided in the following mathematical expression:

Proposed FS-PTC for an IMC-Fed PMSM
As previously mentioned, the VSI side of the IMC is similar to the well-known two-level VSI. Thus, it has a limitation in the switching vectors (i.e., the eight VVs, as shown in Figure 3a). However, if a single switching vector is used for the full sampling interval, this will result in a variable switching frequency and an increase in flux and torque ripples. Additionally, the VV cannot be generated with whole sampling time T s into the inverter side of the IMC circuit to ensure safe commutation and optimized utilization of the rectified averaged DC-link voltage. Because neither the CSR nor the VSI has decoupled control due to the elimination of the capacitor, carrier-based PWM modulation is used to correlate between the rectified DC-link voltage and output voltage of the inverter. Notably, the slopes of the carrier signal for the inverter side are altered in every sampling interval due to the deviation of the averaged DC voltage.
To achieve a stable output voltage within a sampling cycle, the switching arrangement of the power converter must associate the switching patterns of the CSR and VSI stages. Hence, to eliminate the limitation in the switching vectors in the conventional inverter stage of the IMC and to avoid the commutation problem, the DSVM strategy is proposed to increase virtual VVs and, hence, to enlarge the voltage degrees of freedom for FS-PTC of PMSM.

Synthesis of Virtual Voltage Vectors
In this study, a DSVM strategy can be applied using [19]. Hence, the space vector diagram (SVD) is grouped into concentric hexagonal diagrams (CHDs) with various sized VVs. Each CHD consists of several generated virtual VVs in addition to the real VVs. The number of virtual VVs in each CHD relies on its index digit, as provided in the following mathematical expression: In Equation (10), Γ represents the quantity of CHDs. Figure 3b illustrates the proposed SVD with real VVs and synthesized virtual VVs when Γ is 2. The number of VVs is computed according to Equation (10), which equals 37 VVs. The yellow and black dots imply the real and virtual VVs, respectively. Obviously, it is shown that the SVD is partitioned into 12 regions (i.e., SC(1)-SC (12)). In each region, there are six VVs, including a zero-VV.
The real and virtual VVs in the stationary αβ plane are given by: where v DC.avg represents the computed DC-link voltage of the inverter stage, x and y signify the values of each coordinate for each SVD region, and the coefficients (a 1 , a 2 . . . a 6 ) are attained from Table 2 [18]. Figure 4 illustrates the coordinate values of αβ VVs in regions SC(4), SC(5), and SC(6) when Γ = 2. SC(1) In Equation (10),  represents the quantity of CHDs. Figure 3b illustrates the proposed SVD with real VVs and synthesized virtual VVs when  is 2. The number of VVs is computed according to Equation (10), which equals 37 VVs. The yellow and black dots imply the real and virtual VVs, respectively. Obviously, it is shown that the SVD is partitioned into 12 regions (i.e., SC(1)-SC (12)). In each region, there are six VVs, including a zero-VV.
The real and virtual VVs in the stationary  plane are given by: where vDC.avg represents the computed DC-link voltage of the inverter stage, x and y signify the values of each coordinate for each SVD region, and the coefficients (a1, a2 … a6) are attained from Table 2 [18].

Predicted Voltage Vectors
The calculation burden in the prediction stage rises due to the increase in virtual VVs, which also leads to a very large sampling time. Thus, a control approach to lessen the large computation requirement on the microcontroller or digital signal processor (DSP) is necessary.
To lower the number of VVs and, hence, the calculation burden, a computation reduction approach for selecting optimal VVs is proposed by taking into account the flux and torque errors like in the DTC strategy. The prediction vectors in Figure 3b (i.e., proposed SVD) are selected using the sign of the torque error (T err = T * − T e ), flux error (λ err = λ * − |λ s |), and the angle of the stator flux (ϑ). The flux position is calculated based on the αβ stator flux as: To enhance the performance of the prediction, the number of flux positions is split into 12 sectors, as presented in Figure 5. Each flux position is within 30 • . After attaining the required sector, the optimal region of the SVD for each flux position is determined to further decrease the computation burden according to Table 3. To clarify this preselection strategy, an example of the selection of VVs of the SVD region when the stator flux vector is positioned at ϑ(2) is shown in Figure 6. In this flux position, there are four optimal voltage regions depending on the flux and torque errors to satisfy the reduction and increase in torque and flux similar to the DTC. For instance, if λ err < 0 and T err < 0, the VVs in the optimal SVD region 7 are selected. If λ err ≥ 0 and T err < 0, the VVs in the optimal region 6 on the proposed SVD are chosen. In the same way, the optimal SVD region 12 is selected when λ err ≥ 0 and T err ≥ 0 are assured. However, the selection of SVD region 11 in ϑ(2) is ensured if λ err < 0 and T err ≥ 0 are satisfied. Electronics 2020, 9, x FOR PEER REVIEW 8 of 18  Hence, only six VVs are taken into account rather than 37. The 2L-VSI consists of eight VVs   Hence, only six VVs are taken into account rather than 37. The 2L-VSI consists of eight VVs during the calculation and prediction process. It is worth noting that only VVs in the selected SVD region are produced. In this way, the possible VVs are constrained, which substantially reduces the computation burden on the DSP.

Delay Compensation
To compensate for the delay in the experimental implementation, the voltage vectors at instant k+2 for forecasting the variables (i.e., ( 2), k  o i ( 2), k  s λ and ( 2) e T k  ) are computed in the cost function rather than time instant k + 1. Thus, to obtain the optimal VV among the generated six VVs in the chosen SVD region, a cost function needs to be constructed as: Finally, when the optimal VV v opt in the  plane is attained depending on the selected SVD region, it needs to be sent to the carrier-based modulation in the next sampling time. Hence, only six VVs are taken into account rather than 37. The 2L-VSI consists of eight VVs during the calculation and prediction process. It is worth noting that only VVs in the selected SVD region are produced. In this way, the possible VVs are constrained, which substantially reduces the computation burden on the DSP.

Delay Compensation
To compensate for the delay in the experimental implementation, the voltage vectors at instant k+2 for forecasting the variables (i.e., i o (k + 2), λ s (k + 2), and T e (k + 2)) are computed in the cost function rather than time instant k + 1. Thus, to obtain the optimal VV among the generated six VVs in the chosen SVD region, a cost function needs to be constructed as: Finally, when the optimal VV v opt in the αβ plane is attained depending on the selected SVD region, it needs to be sent to the carrier-based modulation in the next sampling time.

Overall Control Algorithm for VSI Stage
The complete control process of the proposed FS-PTC with DSVM of PMSM fed by an IMC can be summarized in the following sequences:

1.
Obtain the averaged DC-link voltage v DC.avg from the CSR stage.

2.
Estimate the motor variables: stator flux and electrical torque.

3.
Predict the stator current, stator flux, and torque by the application of the optimal VV. 4.
Obtain the optimal SVD region according to the electrical torque and flux errors at the specified flux angle based on Table 3.

5.
Calculate the VVs in the αβ frame using the rectified voltage v DC.avg based on the selected SVD region using Equations (11) and (12), and according to the coefficients in Table 2. 6.
Predict the stator flux, stator current, and torque taking into consideration one step forward to eliminate the delay. Then, the calculated VVs from the selected SVD region are evaluated using the cost function in Equation (14). 7.
Choose the optimal VV v opt that reduces the cost function objectives to use at the next sampling cycle for synchronization with CSR and modulation using a carrier-based PWM. Figure 7 shows the complete control for the proposed PTC for the IMC-fed PMSM.
6. Predict the stator flux, stator current, and torque taking into consideration one step forward to eliminate the delay. Then, the calculated VVs from the selected SVD region are evaluated using the cost function in Equation (14). 7. Choose the optimal VV v opt that reduces the cost function objectives to use at the next sampling cycle for synchronization with CSR and modulation using a carrier-based PWM.

Modulation Strategy for VSI of IMC
As stated earlier, the VSI and CSR stages of IMC have to be correlated using a carrier-based PWM to attain safe commutation and stable output voltages for each sampling cycle. The commutation of the CSR stage always occurs because the zero voltage vectors in the inverter stage are used [7]. Therefore, the switching vectors of the CSR and VSI stages are managed to attain the zero DC-link current commutation at the rectifier stage. In this way, a safe commutation can be obtained without a complicated multistep commutation.
The PWM outputs to the inverter are produced by two modulation signals for each phase compared with the triangular carrier. It is worth mentioning that the two modulation signals are determined using the duty cycles (dx and dy) in the CSR stage, vDC.avg, and optimal reference voltages (Va * , Vb * , and Vc * ) of each phase obtained by the proposed FS-PTC. The detailed information about the modulation approach for the VSI of an IMC using the carrier-based PWM can be found in [7]. Hence, the modulation signals (VaT * and VaB * ) for the top and bottom legs of the α-phase are given as:

Modulation Strategy for VSI of IMC
As stated earlier, the VSI and CSR stages of IMC have to be correlated using a carrier-based PWM to attain safe commutation and stable output voltages for each sampling cycle. The commutation of the CSR stage always occurs because the zero voltage vectors in the inverter stage are used [7]. Therefore, the switching vectors of the CSR and VSI stages are managed to attain the zero DC-link current commutation at the rectifier stage. In this way, a safe commutation can be obtained without a complicated multistep commutation.
The PWM outputs to the inverter are produced by two modulation signals for each phase compared with the triangular carrier. It is worth mentioning that the two modulation signals are determined using the duty cycles (d x and d y ) in the CSR stage, v DC.avg , and optimal reference voltages (V a * , V b * , and V c * ) of each phase obtained by the proposed FS-PTC. The detailed information about the modulation approach for the VSI of an IMC using the carrier-based PWM can be found in [7]. Hence, the modulation signals (V aT * and V aB * ) for the top and bottom legs of the α-phase are given as: where v sn is the zero-sequence component (referred to as offset voltage) of the three optimal reference voltages, which is given by: A similar calculation of modulation signals can be applied to the other optimal reference voltages (V b * and V c * ). Finally, the modulated signals are compared with the PWM carrier and sent to the IMC inverter.

Simulation Results
The proposed FS-PTC of the PMSM fed by an IMC was simulated using PSIM software. The motor and LC filter parameters are given in Table 4. The reference flux was set to 0.58. The simulation configuration is similar to the schematic depicted in Figure 1. For the simulation of the complete control system, the sampling interval was designed as 100 µs in line with the experiment. Hence, due to the commutation process [7], the switching frequencies of the CSR stage and VSI stage are 10 and 20 kHz, respectively. It is worth mentioning that the conventional FS-PTC can cause unsafe commutation in the indirect matrix converter because it only involves a single switching state during the entire sampling cycle. Hence, for the sake of investigation of the proposed FS-PTC of the PMSM fed by an IMC, a comparison is performed between Γ = 1 and Γ = 2. For better identification, PTC-SVD-1 represents Γ = 1, in which the number of VVs is 13, and PTC-SVD-2 represents Γ = 2, which indicates the number of VVs is 37. The PTC-SVD-1 is closer to the conventional FS-PTC in terms of the number of VVs. Both PTC-SVD-1 and PTC-SVD-2 methods are investigated under the same weighting factor for fair comparison. Figure 8 depicts the simulation results for the output voltage of the CSR stage in the IMC circuit. Initially, the input three-phase line-to-line voltages (v uv , v vw , and v wu ) from the AC grid are rectified as explained in Section 2 to produce a fictitious DC-link voltage (v DC ), which can be averaged as shown in the subplot of the averaged DC-link voltage v DC.avg . The v DC.avg is computed depending on the duty ratios dx and dy, whereas v DC is produced by the modulation of the CSR stage. The average voltage is utilized by the inverter side in the IMC to control the PMSM.  Figure 10b. In addition, it can be observed that the PTC-SVD-2 has more stable flux and fewer current distortions compared to the PTC-SVD-1 method. When the stator inductance Ls changed to 60% of nominal   Figure 10b. In addition, it can be observed that the PTC-SVD-2 has more stable flux and fewer current distortions compared to the PTC-SVD-1 method. When the stator inductance L s changed to 60% of nominal inductance for both methods, the torque ripple reduced with higher increase in the flux ripple and current distortion as shown in Figures 9b and 10b. Changing the L s to 160% of nominal value results in increasing the torque ripple and reduction of flux ripple and current distortions, as shown in Figures 9c  and 10c. Nevertheless, the proposed PTC-SVD-2 in Figure 10b,c shows a better performance and higher robustness under parameter variation compared to the results of PTC-SVD-1.   Figure 11 shows the FFT waveforms of the A-phase current output (i a ) at 300 rpm for the PTC-SVD-1 and PTC-SVD-2 methods, respectively. It can be observed that the PTC-SVD-2 has fewer harmonic, particularly below 5 kHz, due to the larger number of candidate virtual VVs. From both spectral waveforms, it is obvious that the switching frequency is constant at 20 kHz as shown by the 1st harmonic component for both PTC methods. Notably, the switching frequency of the inverter of the IMC is twice that of the CSR due to the commutation process [7].  Figure 11 shows the FFT waveforms of the A-phase current output (ia) at 300 rpm for the PTC-SVD-1 and PTC-SVD-2 methods, respectively. It can be observed that the PTC-SVD-2 has fewer harmonic, particularly below 5 kHz, due to the larger number of candidate virtual VVs. From both spectral waveforms, it is obvious that the switching frequency is constant at 20 kHz as shown by the 1st harmonic component for both PTC methods. Notably, the switching frequency of the inverter of the IMC is twice that of the CSR due to the commutation process [7].   Figure 12 illustrates the dynamic torque performance of PTC-SVD-1 and PTC-SVD-2 methods when the torque reference was stepped from 1 to 10 Nm at a speed load of 300 rpm. It can be observed that the torque performance in the proposed PTC-SVD-2 was slightly faster than that in the PTC-SVD-1 method. Moreover, the proposed PTC-SVD-2 method has reduced toque ripple at both torque references compared to the PTC-SVD-1 method.
Electronics 2020, 9, x FOR PEER REVIEW 13 of 18 Figure 12 illustrates the dynamic torque performance of PTC-SVD-1 and PTC-SVD-2 methods when the torque reference was stepped from 1 to 10 Nm at a speed load of 300 rpm. It can be observed that the torque performance in the proposed PTC-SVD-2 was slightly faster than that in the PTC-SVD-1 method. Moreover, the proposed PTC-SVD-2 method has reduced toque ripple at both torque references compared to the PTC-SVD-1 method.

Implementation and Experimental Results
The performance of the FS-PTC for the IMC-fed PMSM was implemented using a DSP (TMS320C28346) and a field-programmable gate array (FPGA). Figure 13 presents the experimental setup, which involves the PMSM coupled with the loading induction machine (IM), a power board, and a control board. The power board comprises the CSR and VSI using the IGBT and gate drivers.

Implementation and Experimental Results
The performance of the FS-PTC for the IMC-fed PMSM was implemented using a DSP (TMS320C28346) and a field-programmable gate array (FPGA). Figure 13 presents the experimental setup, which involves the PMSM coupled with the loading induction machine (IM), a power board, and a control board. The power board comprises the CSR and VSI using the IGBT and gate drivers. The IM was used as a load controlled by a commercially available YASUKAWA inverter. The AC source rectification and proposed FS-PTC with the DSVM algorithms for the IMC-fed PMSM was written on the DSP using C programming language. Moreover, the PWM block for both CSR and VSI was programmed using VDHL in the FPGA. The optimal VV is sent to the PWM block in the FPGA to create and feed the three control signals to the VSI. The parameters utilized in the experiment were similar to those provided in Table 4. The LC-filter parameters were empirically selected from the available sets of equipment. Similar to the simulation, the sampling interval of the DSP for both the CSR and VSI stages was 100 µs for the whole proposed control approach under the same weighting factor. Figure 15a,b shows the experimental results of the electrical torque, flux, and current for the PTC-SVD-1 and PTC-SVD-2, respectively. The computation of torque ripple (T ripple ) and flux ripple (λ ripple ) for all control methods, as indicated in the figures, was performed during steady-state operation, as in [32]. Both methods were at steady-state operation at a speed of 200 rpm with 3.0 Nm. The PTC-SVD-2 showed superior performance in terms of torque and flux ripple reduction as indicated by the averaged torque and flux ripples in Figure 15. In addition, the output stator current in the PTC-SVD-2 has less ripple and distortion compared to PTC-SVD-1.  Figure 14 presents the experimental results for the input grid voltages for the u-phase voltage (vun) and v-phase voltage (vvn). The third phase, the w-phase voltage (vwn), is not shown due to the limitation of the measuring equipment. By utilizing the CSR stage, the input grid voltage was rectified to generate the average value of the DC voltage vDC.avg. As previously mentioned, vDC.avg is calculated based on the duty ratios dx and dy.  Figure 14 presents the experimental results for the input grid voltages for the u-phase voltage (v un ) and v-phase voltage (v vn ). The third phase, the w-phase voltage (v wn ), is not shown due to the limitation of the measuring equipment. By utilizing the CSR stage, the input grid voltage was rectified to generate the average value of the DC voltage v DC.avg . As previously mentioned, v DC.avg is calculated based on the duty ratios dx and dy. Figure 14 presents the experimental results for the input grid voltages for the u-phase voltage (vun) and v-phase voltage (vvn). The third phase, the w-phase voltage (vwn), is not shown due to the limitation of the measuring equipment. By utilizing the CSR stage, the input grid voltage was rectified to generate the average value of the DC voltage vDC.avg. As previously mentioned, vDC.avg is calculated based on the duty ratios dx and dy.  ) for all control methods, as indicated in the figures, was performed during steady-state operation, as in [32]. Both methods were at steady-state operation at a speed of 200 rpm with 3.0 Nm. The PTC-SVD-2 showed superior performance in terms of torque and flux ripple reduction as indicated by the averaged torque and flux ripples in Figure 15. In addition, the output stator current in the PTC-SVD-2 has less ripple and distortion compared to PTC-SVD-1.    Figure 16 depicts the experimental results of the dynamic torque performance for the PTC-SVD-1 and PTC-SVD-2 methods as the torque reference was stepped from 1 to 5 Nm. It is evident that the proposed PTC-SVD-2 has a faster torque dynamic performance than that of the PTC-SVD-1 method. Moreover, the averaged torque ripples indicated in PTC-SVD-2 are lower than those in PTC-SVD-1 for both torque references.  Figure 16 depicts the experimental results of the dynamic torque performance for the PTC-SVD-1 and PTC-SVD-2 methods as the torque reference was stepped from 1 to 5 Nm. It is evident that the proposed PTC-SVD-2 has a faster torque dynamic performance than that of the PTC-SVD-1 method.
Moreover, the averaged torque ripples indicated in PTC-SVD-2 are lower than those in PTC-SVD-1 for both torque references.  Table 5 shows a comparison between the conventional FS-PTC, PTC-SVD-1, and PTC-SVD-2 in terms of number of predicted vectors for cost function evaluation, possibility of implementation in IMC, and computation burden. It can be seen that the conventional FS-PTC has the smallest computation burden, however it does not guarantee safe implementation for the IMC. The computation time of PTC-SVD-1 is slightly smaller than that of PTC-SVD-2, however, the PTC-SVD-2 has better performance in terms of output waveform quality and robustness. Table 5. Comparison between conventional FS-PTC, PTC-SVD-1, and PTC-SVD-2.

Conclusions
This study presented an improved FS-PTC for a high-performance indirect matrix converter-fed PMSM drive. The indirect matrix converter does not require a DC-link capacitive element, which can reduce the volume and size of the PMSM drive. The conventional FS-PTC can cause unsafe commutation for the rectifier stage in the indirect matrix converter because it only applies a single switching state during the entire sampling period. Thus, the DSVM-based PTC methods, PTC-SVD-1 (13 VVs) and PTC-SVD-2 (37 VVs), were compared in the simulation and experimental results using the proposed selection method. From these results, the PTC-SVD-2 achieved better steady-state and dynamic torque performances compared to PTC-SVD-1. Additionally, the PTC-SVD-2 showed more robust characteristics against parameter variations than PTC-SVD-1. This improvement can be attributed to the increased number of virtual voltage vectors in the prediction process. In both PTC-SVD methods, the switching frequency of the inverter was constant and twice that of the sampling frequency due to the correlation between the inverter and rectifier stage of the converter. The  Table 5 shows a comparison between the conventional FS-PTC, PTC-SVD-1, and PTC-SVD-2 in terms of number of predicted vectors for cost function evaluation, possibility of implementation in IMC, and computation burden. It can be seen that the conventional FS-PTC has the smallest computation burden, however it does not guarantee safe implementation for the IMC. The computation time of PTC-SVD-1 is slightly smaller than that of PTC-SVD-2, however, the PTC-SVD-2 has better performance in terms of output waveform quality and robustness. Table 5. Comparison between conventional FS-PTC, PTC-SVD-1, and PTC-SVD-2.

Conclusions
This study presented an improved FS-PTC for a high-performance indirect matrix converter-fed PMSM drive. The indirect matrix converter does not require a DC-link capacitive element, which can reduce the volume and size of the PMSM drive. The conventional FS-PTC can cause unsafe commutation for the rectifier stage in the indirect matrix converter because it only applies a single switching state during the entire sampling period. Thus, the DSVM-based PTC methods, PTC-SVD-1 (13 VVs) and PTC-SVD-2 (37 VVs), were compared in the simulation and experimental results using the proposed selection method. From these results, the PTC-SVD-2 achieved better steady-state and dynamic torque performances compared to PTC-SVD-1. Additionally, the PTC-SVD-2 showed more robust characteristics against parameter variations than PTC-SVD-1. This improvement can be attributed to the increased number of virtual voltage vectors in the prediction process. In both PTC-SVD methods, the switching frequency of the inverter was constant and twice that of the sampling frequency due to the correlation between the inverter and rectifier stage of the converter. The computation time is reduced using the preselection strategy based on the flux and torque demands for each positioned flux sector without the need for voltage vector lookup tables.