Hot Carrier Stress Sensing Bulk Current for 28 nm Stacked High-k nMOSFETs

This work primarily focuses on the degradation degree of bulk current (IB) for 28 nm stacked high-k (HK) n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs), sensed and stressed with the channel-hot-carrier test and the drain-avalanche-hot-carrier test, and uses a lifetime model to extract the lifetime of the tested devices. The results show that when IB reaches its maximum, the ratio of VGS/VDS values at this point, in the meanwhile, gradually increases in the tested devices from the long-channel to the short ones, not just located at one-third to one half. The possible ratiocination is due to the ON-current (IDS), in which the short-channel devices provide larger IDS impacting the drain junction and generating more hole carriers at the surface channel near the drain site. In addition, the decrease in IB after hot-carrier stress is not only the increment in threshold voltage VT inducing the decrease in IDS, but also the increment in the recombination rate due to the mechanism of diffusion current. Ultimately, the device lifetime uses Berkley’s model to extract the slope parameter m of the lifetime model. Previous studies have reported m-values ranging from 2.9 to 3.3, but in this case, approximately 1.1. This possibly means that the critical energy of the generated interface state becomes smaller, as is the barrier height of the HK dielectric to the conventional silicon dioxide as the gate oxide.


Introduction
With the continuous scaling of complementary metal-oxide-semiconductor (CMOS) technology, there are many benefits to metal-oxide-semiconductor field-effect transistors (MOSFETs), including an increasing number of devices in integrated circuits, not only providing impressive electrical performance of the device, but also decreasing the entire power consumption. However, the shorter channel length and thinner gate dielectric thickness of the MOSFET increase the OFF-current including the gate leakage and source/drain (S/D) punch-through effect, and relatively influencing the threshold voltage (V T ), short channel effect, and reliability issues [1,2]. In terms of reliability, the device lifetime will be reduced by hot carrier injection (HCI) [3,4]. The most common physical model for HCI is the lucky carry model built by Hu et al. [5]. Berkeley's model can derive the device lifetime with bulk current (or called substrate current (I SUB )). The model is shown in Equation (1).
where τ is the device lifetime, I DS is the drain-to-source current, I SUB is the substrate current, and the acceleration factor m = φ it /φ i , where φ it is the critical hot carrier energy required to create an interface state of approximately 3.7 eV and φ i is the minimum hot carrier energy required to create an impact ionization of approximately 1.3 eV for the poly-gate and Si-SiO 2 interface. The hot carrier effect can be classified into two types: Channel-hot-carrier (CHC) and drain-avalanche-hot carrier (DAHC) tests [6]. The CHC effect means that the carriers near the drain terminal are accelerated by the lateral electric field and travel through the channel [7][8][9][10][11][12], as shown in Figure 1. The quoted references related to hot-carrier (HC) effects are listed in Table 1. Studies have shown that the maximum I SUB (I SUB_max ) is at V DS = V GS [13,14]. As V DS > V GS , the depletion region near the drain site is increased. As the carriers in the channel travel through this region, they are accelerated and energized to become hot carriers. These hot carriers may generate extra electron-hole pairs [15] in the channel, especially in the depletion region of the drain size. This phenomenon is called impact ionization. The generated electron may inject into the gate or drain terminal, and the generated holes trend to the substrate, as shown in Figure 2. The results demonstrate that the I SUB_max value is located at V GS = V DS /3~V DS /2 [16,17], called the DAHC effect.  In particular, while the thickness of the silicon dioxide (SiO 2 )-based gate dielectric approaching its physical limitation, at the 45 nm-node-technology generation [18][19][20], is below 15 Å, gate leakage due to the direct tunneling effect cannot be tolerated at the OFF-current specification. Using the stacked high-k (HK) dielectric (HfO x /ZrO y /HfO z (HZH)), replacing the conventional SiO 2 in gate engineering or halo implants and lightly doped-drain (LDD) technology in the surface channel is a couple of attractive metrologies to promote the drive current and decrease the leakage in nano-node process technology [21]. Table 1. The comparison of quoted references [7][8][9][10][11][12]17,22] in the former and present process technologies.

Purpose Stress Method Specifications
Takeda et al. [7] Probing the DAHC injection and the substrate current-induced hot-electron injection (SCHE) under submicron process with gate dioxide. In this study, we used a HK-stack and metal gate (MG) as the n-MOSFET structure to analyze the variation in substrate current under hot carrier stresses [22]. In Equation (1), the severity of hot carrier injection is observed by the degradation in the substrate current, related to the issues of device lifetime. The other interesting event is to expose the relationship between channel lengths and substrate currents in nano-node n-MOSFETs. In addition, we used different stress conditions to probe the impact of substrate current, and investigated the τ × I DS /W vs. The I SUB /I DS model extracts the slope parameter m in Equation (1). In this study, V T extraction was followed the constant current methodology. To accelerate the process and circuit development in yield and reliability analysis in the nano-node era, the technology computer-aided design simulator is an appropriate choice as an assistant [23][24][25].

Concise Process Flow and Stress Conditions
In this study, the schematic tested devices on 28 nm HK/MG wafers fabricated from the United Microelectronics Corporation (UMC) are used to perform the related extraction and analysis, as shown in Figure 3. After the standard cleaning, an interfacial layer (IL) of SiO x of approximately 9 Å was grown thermally to play a buffer between the surface channel and HK material and resist the nitrogen free radical to arrive at the surface channel to form the silicon nitride. Subsequently, the HK material was deposited as HZH by atomic layer deposition (ALD) technology [26][27][28]. In sequence, the devices were processed with the decoupled plasma nitridation (DPN) treatment to retard the amount of oxygen vacancies [29,30]. The treatment process employed the annealing temperature (700 • C) and nitrogen concentration (8%) after accomplishing an HK layer. The other key processes include an Si-based substrate, channel implantation, S/D engineering, interfacial layer, barrier metal, and low-resistivity Al metal gate. The metal gate was adopted in the gate-last (GL) process technology [31]. This technology provides several good functions to reduce the threshold voltage, gate electrode resistance, power consumption, and gate delay. The detailed 28 nm HK/MG process flow with the GL process can be referred to Wang et al. [21]. The basic electrical characteristics and stress tests were performed using a Keithley 4200 Semiconductor Characterization System. The test conditions can be divided into two parts. The first part is that the I SUB is measured with different channel lengths to observe the impact of the channel length change. The measurement conditions are listed in Table 2. The second part is related to the measurement of the HC degradation test. In these stresses, different stress voltages and channel lengths were applied to sense and analyze the most serious stress method, either CHC or DAHC stress [32]. The measurement conditions are presented in Table 3 with the V T extraction metrology following the constant current measurement.

The Relationship between the Channel Length and I SUB
The I SUB -V GS curves of n-MOSFETs were measured for different channel lengths, as shown in Figure 4. When the tested device was in the OFF state, the increment in absolute value of gate voltage at the negative V GS axis increased the I SUB because of the gate-induced drain leakage effect [33]. However, as the tested device was operated in the ON state, the gate voltage increased, inducing an increment in I SUB . This effect points to the fact that the average carriers in short channels are hotter and have more energy to create an impact ionization event. Thus, the rate of increase in I SUB with the shorter channel-length device is higher than the increase in I DS . As the channel length of the tested device decreases, the lateral electric field increased, and the I DS increases, resulting in an impact ionization rate (I SUB /I S ), where I S is the current sensed at the source terminal, which increases, as shown in Figure 4a. While the channel length decreased, the maximum I SUB with the increase in V GS increases, generating a higher impact ionization rate, as shown in Figure 4b. The possible ratiocination indicates that the gate voltage increases, indicating a stronger vertical field, to attract more inversion electrons to recombine the holes in the longer channel length.

I SUB and V T Degradation after HC Stresses
The stress conditions in the CHC stress mode are listed in Table 3. Figure 5 illustrates that the short channel device causes serious degradation owing to the larger horizontal field from the drain site to the source node, and the higher stress voltage can also increase the device degradation in the I SUB aspect. In summary, the most obvious degradation for I SUB is set at the tested device W/L = 0.5/0.03 µm and the stress voltage at V GS = V DS = 1.6 V. The other degradation index V T shifts with different channel lengths, and the different stress voltages are shown in Figure 6. The V T shift observed at L = 0.03 µm and the stress voltage V GS = V DS = 1.6 V are the worst [34][35][36]. However, as the stress condition is at the higher gate field, the distribution of V T shift at L = 0.03 µm and 0.11 µm is similar, as shown in Figure 6b,d, but not at the lower field, as shown in Figure 6a,c. This speculation is that the capability of trap repair in the lower field is better in the channel, and so is the longer device. Following the research results of Huang et al. [37], they denoted that the drain current in the nano-MOSFETs covers the drift and diffusion currents, fitting well in simulation and measured electrical current-voltage characteristics. In this reference, the carrier conduction in the channel is similar to that in a p-n junction. The entire current flow in the p-n junction is mainly dominated by the diffusion mechanism. Therefore, a reasonable speculation of the decrement in I SUB after HC stress is not only the increase in V T indirectly causing the decrease in I DS , but also the increase in the recombination rate arising from the diffusion current, especially for the nano-node devices. As the channel length is less than 0.04 µm, this consequence is more distinct regardless of the HC stress method.  In the DAHC stress mode, the stress conditions are similar to the CHC stress. The slight difference is that the gate voltage is defined by the V GS at the maximum I SUB . The test results show that the maximum I SUB does not appear in the short-channel device (L = 0.03 µm). Therefore, the discussion will only focus on the tested devices with L = 0.07 µm and L = 0.11 µm. Figure 7 shows that the most serious degradation of I SUB is at L = 0.07 µm and the stress voltage V DS = 1.6 V. The V T shift is shown in Figure 8. The worst degradation is at L = 0.07 µm and the stress voltage V GS at I SUB_max and V DS = 1.6 V. After the DAHC stress, the substrate current is similarly decreased by the increase in V T , causing a decrease in I DS and an increase in the recombination rate from the diffusion current.
By observing the amount of V T shift with CHC and DAHC tests, the value of V T -shift with the CHC test is higher than that with the DAHC test. This phenomenon is similar to that reported in [32]. As deep analysis, because of the low gate field, the distribution trends of V T shift vs. stress time are not the same, which are different from the consequences under the CHC stress. However, the decrease trends of substrate current both before and after the HC stresses seem compatible.

HC Lifetime Model for n-MOSFETs
The τ × I DS /W vs. I SUB /I DS model [5,16] is adopted into these tested devices, as in Equation (1). The model can effectively explain the correlation between I SUB and lifetime (τ). When the I SUB increases, the lifetime decreases. This indicates that when the I SUB is larger, the HC effect and the device degradation become serious. The slope of the predicted line, m, is 1.1, as shown in Figure 9, compared with the former research m ranging from 2.9 to 3.3 for SiO 2 . The decrement in m-value means that the interface states become easier to generate due to the HK structure. According to references [38,39], the work function of polygrain Al is 4.13 eV and the band offset of HfO 2 compared to Si is 1.5 eV. The affinity of Si is 4.05 V. The barrier height between gate Al and HfO 2 is approximately 1.58 eV, close to the critical hot carrier energy, requiring the creation of an interface state φ it , as shown in Figure 10. If we adopt the φ i = 1.3 eV minimum hot carrier energy to create an impact ionization in the Si-based surface channel, the ratio of φ it /φ i representing the theoretical m-value is approximately 1.2, which is very close to the extracted m parameter 1.1.
After stress, the subthreshold swing SS is changed, related to the change in interface integrity between the IL and Si-based channel. The ∆SS (SS value after stress-SS value before stress) is equal to where k is Boltzmann's constant, T is the absolute temperature, q is the unit charge, C it is the equivalent interface-state capacitance per area = qD it , D it is the interface state density, N it is the interface state number per area with integration of D it in the energy band, and C ox is the gate capacitance per area. The threshold voltage change, ∆V T , after stress contains the change in the oxide trap in the gate dielectric and the interface state on the surface channel, as shown in Equation (3). ∆Q f covers the qN it change q∆N it and qN ot change q∆N ot , where N ot is the oxide trap number per area in the gate dielectric.
Using Equations (2) and (3), ∆N it and ∆N ot can be decoupled after hot carrier stress. These two amounts also explain the degradation level of the oxide trap and interface trap state for a tested device under a long-time operation, as shown in Figure 11 with W/L = 1/0.03 µm under different plasma nitridation treatments [21,39,40]. ∆N it or ∆N ot with different nitridation treatments exposes the different historical trends in hot carrier stress. In addition, in terms of the test consequences, the V T -shift with CHC stress is more serious than that with DAHC, as shown in Figure 12. Even though the observed I SUB_max occurs well under DAHC stress conditions, the major degradation mechanism still comes from the interface state and/or oxide trap generation [41][42][43][44]. Moreover, the generation of the interface state near the IL is also possibly due to the channels strained, which could be more relevant to reduce the bonding energy than that on the top of the HK layer. Due to the CHC stress mode owing to the higher gate voltage generating more interface states and oxide traps, the V T -shift in the worst case under the view of I SUB_max can be effectively demonstrated to be attributed to the V GS = V DS stress condition, not at V GS traditionally located at one-third to one-half V DS [5].

Conclusions
In this work, we observe that the maximum substrate current and the ratio of I SUB /I s before the HC stress increased as the channel length of the tested devices was shorter. After the HC stress, the I SUB_max decreased, especially for the deep nano-node channel-length device because of the increase in V T indirectly degrading the I DS and the increase in the recombination rate from the diffusion current as the channel length entered the nano-node level. Through the longer stress time, this phenomenon was more obvious, which also contributed to the V T shift. Even though the observed I SUB_max occurred well under DAHC stress conditions, the major degradation mechanism still came from the interface state and/or oxide trap generation. The other consistent agreement was to extract the HC lifetime with Berkley's model, still available in HK/MG n-MOSFETs, deposited with ALD technology, but the values of acceleration factor m were different from the gate dioxide or oxy-nitride. Ultimately, the HC stress is indeed and still a good gauge or application in nano-node device reliability tests or process splits in the optimal adjustment of front-end processes, such as channel implementation, growth of the gate dielectric, or HK dielectric deposition with nitridation treatment.