Thermal Stress Reduction of Power MOSFET with Dynamic Gate Voltage Control and Circulation Current Injection in Electric Drive Application

: While operating an electric drive under different load conditions, power switch devices experience thermal stress which provokes wear-out failures and compromises lifetime. In this paper, a model-based dynamic gate voltage control strategy is proposed to reduce the thermal stress by shaping the proﬁle of conduction losses. Thermal stability criteria are investigated, which limit the gate voltage operating range; thus, current focalization and associated local heat up are avoided. After that, simulations and lifetime estimation are conducted for performance evaluation in two different operation scenarios, which show promising results at high speed operation conditions. Furthermore, a current injection method is applied for low-speed operating conditions to improve the compensation effort. This method is experimentally veriﬁed by using a custom proof-of-concept gate driver that supplies an adjustable three-level gate voltage. A three-phase electric drive is prototyped, on which power cycling tests are conducted. The junction temperature is measured and the results conﬁrm the thermal control method.


Introduction
In aerospace and traction applications, the electric drive system can adopt multi-phase machines and power converters that comprise more power switch devices to achieve fault-tolerant operation [1]. In linear motion control applications, such as the wafer stage of a lithography machine, a multiplicity of power switches is incorporated to meet high efficiency and high precision requirements [2]. Therefore, the lifetime of power switches significantly influences the availability of the power converters.
Failure mechanisms of power switch devices are typically categorized as either catastrophic or aging failures. Catastrophic failures happen in short time periods, which range from microto milliseconds. Root causes of such failures are semiconductor-die related abnormal events, which include among others overvoltage, overcurrent, short circuit, unclamped inductive switching and overtemperature [3]. Moreover, single event effects such as cosmic radiation induced failure happens when the device is hit by energetic particles during the off state, and concentrated amounts of charge are deposited which enables current flowing [4]. Furthermore, abnormal events due to instabilities are thoroughly studied in [5], which indicates that the nonuniform distribution of some internal parameters, such as gate resistance and breakdown voltage, can provoke current filament and thermal runaway. Protection schemes such as derating and fault detection methods are applied to improve the system reliability [6]. To the contrary, aging failures take years to happen and root causes

Power MOSFET Model Description
To describe and analyze the power MOSFET characteristics, a physics based analytical model is required. The original 2nd order model is proposed in [17], which performs relatively accurate in the linear region. This model has been improved in [18] to account for the linear behavior of the transfer curve at high current and gate voltage, whereas the electron mobility is reduced as a result of a high transverse electric field. Moreover, to incorporate the effect of carrier diffusion due to nonuniform channel dopant density, separate linear and saturation transconductance with different values are used.
The MOSFET model used in this work adopts the structure proposed in [19,20], which represents the drain current by paralleled channel currents. They are described by the low current I mosL , that is conducted in the corners of MOSFETs cell, and the high current I mosH , that is conducted by the main portion of the MOSFET cell, respectively. The corner regions of the MOSFET cell have a lower threshold gate voltage and transconductance compared to the main portion, which results in earlier turn-on and lower channel current. The MOSFET drain current I d is then expressed as The detailed expression of the channel currents are represented as follows: Low current in corner regions: High current in the main channel: where V pinL = (V gs − V thL )/P vf , V pinH = (V gs − V thH )/P vf , and y = 2K lin /(2K lin − P vf × K p ).
And temperature dependent parameters are described as: The model is synthesized such that the channel current and its first derivative are continuous at the pinch-off voltage points (i.e., V pinL and V pinH ). An additional channel-length modulation parameter λ proposed in [21] is adopted to account for the MOSFET static behavior in the saturation region, which provides a more precise estimation of the switching transient.
The parameter extraction methods have been investigated in [19][20][21], where the Levenberg-Marquardt (LM) method with a high fitting accuracy is applied in this work. The LM method is a combination of the Gauss-Newton method and Gradient Descent Method, and generally applied for solving nonlinear least square regression problems. This method adaptively varies the parameter update step to approach the local minimum, at which the optimized parameter value is achieved [21][22][23]. The method is implemented in Matlab and the algorithm is illustrated in Figure 1. The algorithm starts with a given initial parameter set h 0 , and calculates the errors r(h) between the measurement data y and the model f (h, X). In this case, the vector matrix y of dimension m represents the measured drain current I d , the matrix X represents the input variables (V ds , V gs ) and h are the parameters used in (2) and (3). To find the parameter set h that minimize the sum of squares of the errors 2 , with row element y j and x j of y and X, the LM method calculates the changes of the parameter set ∆h iteratively based on the damping factor λ, the jacobian matrix J and a identity matrix I. The update step is then evaluated and dynamically adapted by varying λ according to ρ(∆h) and a user-defined factor ε as illustrated in Figure 1. When the criteria matched, the changes of the parameter set ∆h is compared with the step tolerance ε 2 (in this case ε 2 = 10 −6 ). If ∆h < ε 2 , the parameter value is optimized, otherwise the algorithm updates h for next iteration. By implementing this algorithm, the parameter values are extracted and listed in Table 1. The measurement data of the IV-characteristics at 25 • C and 150 • C obtained from the data sheet are used for model fitting. The fitted model and the original data are then illustrated in Figure 2, where the model shows good accuracy compared to the measurement data. To quantify the fitting accuracy, discrepancies between the model and measured IV-characteristics at each gate voltage are calculated by finding the root-mean-square deviation (RMSD) with: and the results are included in Table 2.

Dynamic Gate Voltage Control with Low Frequency Current
While the frequency ω o of a sinusoidal load current I load (t) ranges around few tens Hertz, the junction temperature profile follows the shape of power losses, which is determined by the square of the drain current and varies at twice the load frequency. To reduce the junction temperature swing ∆T J of a power MOSFET, this power loss profile has to be controlled. During on-state, the power losses P con depend on the duty cycle d(t), drain-source voltage V ds and drain current I d (i.e., I d = I load ). Therefore, by adjusting V ds (t) with a proper gate voltage V gs (t) during the conduction stage, fluctuations of P con and the corresponding junction temperatue ∆T J profile caused by a varying load current can be stabilized and minimized. However, because of the thermally unstable behavior of MOSFET under low gate-voltage operation, nonuniform current distribution among MOSFET cells occurs, which provokes current focalization and thermal runaway. In the next paragraphs, the adjustable gate voltage control method and countermeasures to the associated thermal instabilities will be detailed.

Gate Voltage Derivation
By taking the model accuracy and complexity into account, a simplified Hefner model in [18] is used to derive an analytical expression of the gate voltage. This model can be described by During the conduction stage, the MOSFET operates in the linear region and therefore the fitting method only takes the linear region data into account to improve the local fitting accuracy. The parameters of both 25 • C and 150 • C are extracted by the LM fitting method, and the results are listed in Table 3. The fitted model and the original data are depicted in Figure 3, where the model shows good accuracy in the linear region and relatively larger discrepancy in the saturation region.   It is worth noting that the extracted parameter values in Table 3 might be physically inviable, for instance, the gate threshold voltage V th is too large at 25 • C and close to zero at 150 • C. In spite of this, the gate voltage V gs (t) can be derived based on this model, since discrepancies listed in Table 4 are very small, which shows its capability of providing a precise numerical description. Table 4. Discrepancies between the model and measured data.

Measurements Model
Next, the average conduction losses produced during switching cycle k at period time T s with duty cycle d(t) are set to a constant P const by with P const = Max [ P con,T s (t)]. The gate voltage V gs,T s (t) is then obtained by solving the simultaneous equations consisting of (7) and the linear region part of (6), which is indicated by the intersections in Figure 3a,b, yielding while |I d (t)| > I min (t), and I min (t) = (K lin P const /d(t)) 2 2K p 1 3 . However, the simultaneous equations have no solution when |I d (t)| ≤ I min (t), and the corresponding pinch-off voltage V pin (I d (t)) can be applied to maximize the compensation efforts [12]. By solving the simultaneous equations consisting of (7) and the saturation region part of (6), V pin (I d (t)) is expressed as

Thermal Stability Criterions
By observing Figure 3a,b, a relatively high drain-source voltage V ds is required while the drain current I d is low to achieve constant conduction losses. However, operating in such a condition might trigger secondary breakdown, which commonly occurs in the minority carrier devices like BJTs. Because the minority carrier density is proportional to the intrinsic carrier density, which possesses a positive temperature coefficient (PTC) property. For majority carrier devices, like MOSFETs are generally immune from this issue [24].
Despite this, failures are observed from the last generation power MOSFET devices while operating with low gate voltage. In [16], test results of a trench power MOSFET reveal its thermal instability while operating in the saturation region (i.e., linear mode). As a result of the high transconductance and negative temperature coefficient (NTC) property of gate threshold voltage (i.e., dV th /dT J < 0), MOSFET channel resistance has a NTC property (i.e., dI d /dT J > 0) at low gate voltage and low current level, which provokes current focalization and thermal runaway [25][26][27].
Thermal stability criteria has been usually investigated, whereas large scale integration (LSI) MOSFETs are studied at high temperature concerning their temperature dependent parameters and the corresponding thermal instability [28,29]. In addition, power MOSFETs operate in the saturation region as a constant current source is studied in [30]. A so-called temperature compensation point (TCP) is defined as the intersection of the transfer curve at different junction temperatures, on which dI d /dT J = 0. Above the TCP, the MOSFET current has a negative dI d /dT J . In other words, the MOSFET saturation current decreases at higher junction temperature, which balances the current among MOSFET cells. On the contrary, if operating the MOSFETs below the TCP with a low gate voltage, inhomogeneous current distribution occurs and the cooling capability should be enhanced to prevent thermal runaway.
However, in order to achieve high power processing efficiency, for instance in motor drive applications, power MOSFETs operate in the linear region during conduction stage, yet previous little work has been devoted to thermal stability in this region. In this work, the gate voltage is decreased or increased according to the drain current to achieve constant conduction losses. Therefore, the operation range should be constrained to the positive temperature coefficient (PTC) areas, which is illustrated in Figure 3c,d. On each IV-characteristic curve of different gate voltage, the TCP that separates the NTC and PTC areas is defined as the thermally stable boundary condition. The gate voltage V gs,TCP at the TCP is derived by setting the linear region current of (6) as follows which gives: Moreover, by complying to (11), thermal instabilities cannot be fully eliminated as parameter drifting occurs in the manufacturing stage and aging process, which causes model inaccuracy. Therefore, to improve the system robustness, operation margins are incorporated in the gate voltage derivation process (A1) in Appendix A, which gives Therefore, to operate in the PTC area, the dynamic gate voltage V gs (t) has to be larger than (12), and synthesized by taking the larger one of (8) and (12) as because V gs,TCP (I d (t)) ≥ V pin (I d (t)) always holds while |I d (t)| ≤ I min (t).
It is claimed in [5], that instabilities are hard to avoid by using protection circuits because there is no clear external evidence when they occur. As proposed in [31], online temperature monitoring via a embedded thermal sensor that using a PN junction of the power MOSFETs could be a possibility to counteract thermal runaway, however by properly constraining the gate voltage as discussed above, thermal runaway will not occur in the first place.

Dynamic Gate Voltage Control with High Frequency Current
When a motor drive operates at high speed (generally between a few hundreds to thousand Hertz), the junction temperature T J is determined by the load profile I L instead of the instantaneous current, since the phase current frequency then becomes significantly higher than the thermal cut-off frequency of T J . In the next paragraphs, the gate voltage control method is modified to accommodate such high speed operation scenario.
By applying a sinusoidal load current I load (t) at a frequency of ω o , with the duty cycle d(t) that is modulated with index d and d 3 for the 1st the 3nd order harmonic, respectively. The RMS current in a load cycle T L can be derived as and the duty cycle By following the method developed in Section 3, the conduction loss produced in each load cycle T L is set to a constant by with P const = Max P con,T L (t) . Similar to (8), the gate voltage V gs,T L (t) is then found to be while I L (t) 2 > I min (t), and I min (t) = (K lin × P const ) 2 2K p 1 3 .
To operate the power MOSFETs in the PTC area, the gate voltage has to be larger than (12), and therefore by combining with (16), it can be synthesized as: where V gs,TCP (I L (t)) = nI L (t) and V gs,TCP (I L (t)) ≥ V gs,TCP (I d (t)) always holds.

Electric Motor Drive Application
In this section, load-profile based system-operation principles and the associated dynamic gate-voltage control methods are introduced. In the next paragraphs, case studies and simulations are conducted to evaluate the system performance. Moreover, to enhance the compensation efforts at low speed, a circulation current injection method is developed.

Electro-Thermal Model
To verify the proposed gate voltage control method, an electro-thermal model (ETM) of the power MOSFET is built up and illustrated in Figure 4. According to (1), the ETM encompasses two voltage dependent current sources, which represent the low current I mosL and high current I mosH . The power switch contains three parasitic nonlinear capacitors C gd , C gs and C ds respectively, which depend on the drain-source voltage V ds [32]. The dependency is described by look-up tables. The equivalent thermal network is simulated with a third order network, where parameters are obtained from data sheets.

Case 1: Electric Drive of Rotating Machine under High Speed Operation
In a high speed operation scenario, simulations are conducted by using PLECS in the Matlab Simulink environment with a load condition of 200 Hz and varying amplitude I L (t). It can be observed from (17) that after measuring the load current I L (t) (i.e., phase current), the gate voltage control scheme can be readily applied to each power MOSFETs in an electric motor drive. Instead of a conventional gate driver that produces two-level pulses, a dynamic gate driver is proposed to generate a three-level gate signal. This gate signal starts with a high voltage stage (18 V for this case) for a fast switching performance, followed by the adjustable gate voltage V gs (t) during the conduction stage to adjust the conduction losses. In Figure 5, the system operation principle shows that its implementation can be readily realized by merely integrating three dynamic gate drivers. Other aspects, such as the power converter topology, modulation method, and control scheme (i.e., field-oriented-control in this case) will not be affected. By observation of Figure 6a, the dynamic gate voltage V gs (t) of switch Cu, as obtained from (17), follows the envelope of load current and is always higher than the required level V gs,TCP (I loadC (t)) to operate the switch Cu in the PTC area. After that, the corresponding junction temperature response of switch Cu is then obtained from the electro-thermal model in Figure 4. Simulations with a conventional two-level gate signal under the same load conditions are conducted to obtain the junction temperature for reference. Temperature swings ∆T J at different load transitions are depicted in Figure 6b, and the values are listed in Table 5. The power losses increase slightly as expected, however, the overall system efficiency is merely affected while operating with high output power (i.e., 4262 W in this case).

Case 2: Electric Drive of Linear Machine under Low Speed Operation
Low speed operation scenarios, for instance a lithography machine require large current during acceleration to achieve high propulsion force for fast motion control. Therefore, an electric motor drive contains six half-bridge legs is implemented in Figure 7, where the load currents are conducted by paralleling switches. Although increasing the total part counts, switch power losses and junction temperature are reduced. The junction temperature in this case follows the load current profile, because of the current frequency is lower than the thermal cut-off frequency of T J . By applying (13), the gate voltage V gs (t) of switch Cu is obtained based on the load current I loadC (45 A and 10.4 Hz in this case). To analyze the system performance, simulations are conducted by using the control scheme proposed in Figure 7, and the results are depicted in Figure 8. By observation of Figure 8a, part of V gs (t) is clipped to the value of V gs,TCP to avoid entering the NTC region. The conduction losses are illustrated in Figure 8b,c. It can be observed that, by adopting the three-level gate signal, the conduction losses profile P dyn is raised and flattened compared to P re f , where the conventional two-level gate signal pulse are applied. As shown in Figure 8d and Table 6, the junction temperature response T J,dyn indicate similar ∆T J but higher average temperature T J,avg with respect to T J,re f . There are two reasons behind this behavior: on one hand, the thermal capacitance of the chip die is quite small and therefore temperature drops immediately while power losses become lower; on the other hand, gate voltage is not allowed to be lower than V gs,TCP and the thermal compensation efforts are largely reduced as a consequence. It worth noting that, while V gs (t) = 18 V, the system efficiency drops to 88.8% compared to 97.6% in Table 5 obtained at high speed operating condition. This is due to relatively small back-emf at low speed and consequently lower output power. To improve the compensation efforts under low speed operation, the proposed motor drive containing six half-bridge legs and interconnected inductors is implemented in Figure 9. Figure 9. System operation principle of the circulation current injection method.
Two interconnected inductors are used to circulate high frequency current between two half-bridge legs. The circulation current frequency ω cir should be above 20 times of the load current frequency ω o for sufficient compensation resolution. The circulation currents flow within the power converter itself and are not influencing the three-phase load current. Therefore, the inductor currents of phase C can be expressed as where I(t) = 1 2 I loadC (t) = I l (t) × cos(ω o t), and I l (t) = 1 2 I L (t).
By following Equation (18), the inductor currents of other phases can be described similarly. To regulate the three-phase load current in a dq synchronously rotating reference frame [33], a PI controller and space-vector modulation are adopted. For controlling the circulation current, a proportional-resonant (PR) controller with a resonant frequency ω cir (i.e., 8 kHz in this case) is applied in the stationary reference frame [34] as: While conducting the circulation current, the drain current equals to the corresponding inductor current, and the RMS value of the drain current I d,rms,T J (t) of the switch Cu in each circulation current period T J can be represented as where as the duty cycle D cu (t) = d(t) + (L × ω cir × I cir (t) × cos(ω cir t + π/2)) (2V dc ) . Similar to (7), the conduction losses produced during each circulation current period T J are set to a constant P const by with P const = Max P con,T L (t) .
The gate voltage V gs (t) is then found to be (22) In order to operate the power MOSFETs in the PTC area, the gate voltage has to suffice V gs (t) ≥ V gs,TCP (I d (t)). (23) Following the derivation steps from (A2)-(A4) in Appendix A, the minimum circulation current amplitude I cir (t) has to satisfy In addition, by following the steps from (20) to (24), the circulation currents of other phases and gate voltages of the rest of switches can be derived similarly. By using the control scheme in Figure 9, simulations are conducted with load current of 45 A, 10.4 Hz and results are illustrated in Figure 10.  Figure 10a shows the inductor current I Lδ5 of phase C, which consists of half of the load current with frequency of 10.4 Hz and the circulation current with a frequency of 8 kHz. Therefore, a higher switching frequency (40 kHz in this case) is required to regulate the circulation current and thus producing more switching losses. The gate voltage V gs (t) obtained from (22) is depicted in Figure 10b, which suffices the requirement of (23) to operate the power MOSFET in the PTC area. As shown in Figure 10c, by applying V gs (t), the conduction losses profile P cir+dyn is flattened compared to P cir , in the interval where no circulation occurs. The junction temperature responses are compared in Figure 10d, and details are listed in Table 7. It can be observed that, the junction temperature swing is significantly reduced down to 4.2 K by compromising the system efficiency, which results from higher losses due to the circulation current and higher switching frequency. In addition to that, low output power at low speed operation is another factor that reduces the system efficiency. Therefore, the thermal stress related failures will be avoided and lifetime is expected to increase. It is worth noting that this current injection method is only specified for applications with large current variation and consequently higher ∆T J , and critical requirement on the lifetime, such that efficiency can be compromised. It is worth noting that, the gate voltage is calculated based on the obtained MOSFET parameters in Table 3, which are fitted from the data-sheet. In other words, open-loop junction temperature control is applied by adjusting the gate voltage. As an inherent property of the loop-open controller, the controller output (i.e., V gs ) will be influenced in case of device parameter drifts. Therefore, a model-based closed-loop temperature control is recommended by adding a real-time temperature observer to improve the system performance. In terms of the controller safety robustness, thermal runaway is avoided by incorporating operation margins in (A1), (A3) and (A4) in Appendix A, which ensures the PTC operation of the power MOSFETs.

Lifetime Estimation
Lifetime considering thermal stress is generally estimated based on the linear damage accumulation principle [35]. If the same failure mechanism is shared within a full thermal stress profile, all stress levels can be added up to calculate the total accumulated damage (AD) as: where N f i represents the number of cycles to failure at stress ∆T Ji , and n i is the number of cycles accumulated at this stress level. The end of life can be expected when AD reaches one. The number of cycles to failure N f under a certain stress can be estimated by an empirical equation Activation energy E a = 9.89 × 10 −20 J, Boltzmann-constant k B = 1.38 × 10 −23 J × K −1 , A c = (650, 790 K) −α , and α = −4.67. (26) The parameters are obtained from [36] by testing the DCB based transfer molded TO-247 package. It is worth noting that the parameters are fitted for a temperature swing ∆T J that is larger than 110 K, which exceeds the simulated value of ∆T J in our case. Despite this, to compare the system performance with different compensation methods, a rough lifetime estimation based on these parameters is still highly meaningful. When using different package technologies, the value of α or A c changes, however, similar results can be expected if the empirical model in (26) holds.
By analyzing the simulation results obtained from the above cases, a lifetime estimation is conducted of which the results are listed in Tables 8 and 9. The lifetime is improved by a factor of four while operating in the above high speed case by using the gate voltage control method, and more than 10 5 times while adopting both the circulation current injection and gate voltage control method in the low speed case. In [37], power cycling tests of IGBT transistors indicate that the lifetime can strongly increase while ∆T J becomes very small, that meaning (26) does not agree with measurement results. This is because the thermomechanical stress will mainly cause reversible elastic deformation at low ∆T J , and in that case the absolute temperature has a large impact on the lifetime. Therefore, the lifetime estimation of the last case in Table 9 can be inaccurate, however with negligible ∆T J , the thermal stress related number of cycle to failures are expected to be significantly increased. Table 8. Lifetime estimation and system efficiency for case 1.

Experimental Verification
In Figures 11 and 12a, a proof-of-concept for a three-level gate driver is shown. It is operated to trigger the power MOSFET with a switching frequency f s of 10 kHz. The gate signal is generated by first activating the turn-on FET to produce a short high voltage V h stage (+18 V for 1.2 µs in this case) for fast switching, thus avoiding extra voltage harmonic distortions on the load side. The voltage V h is selected to has a reasonable large amplitude depends on the MOSFET type, which enables fast switching and not destroying the gate. To accommodate higher f s , the width of the +18 V stage can be adjusted and its duration should be at least longer than the minimum required switching-on time. During the on-state, the power op-amp is enabled to adjust the gate voltage level to V gs (t) for controlling the conduction losses. The conduction stage duration t cond of the gate signal is expressed by t cond = d(t)/ f s -1.2 µs. At last, the turn-off FET with a lower gate resistance is switched on for switching off the power MOSFET.
A saturation detection scheme is developed, which monitors the on-state drain-source voltage drop to guarantee a safe operation of the transistor. A protection circuit is implemented, which compares the drain-source voltage with two different voltage levels. When V ds is higher than the low level, the gate voltage will be switched back to +18 V to prevent saturation, such that no hard stops would occur, and when cross conduction happens, the power MOSFET will be switched off by Soff for short circuit or over current protection. To conduct the power cycling test, a 3 kW electric motor drive presented in Figure 12b is built up, where the phase current and gate voltage regulation algorithms are implemented by using the Arduino DUE controller. The on-state drain-source voltage V ds,on is measured by a voltage clamping circuit, and it can be observed from Figure 13a,b that, V ds,on increases from 0.6 V to 1 V when reducing the gate voltage from 18 V to 13 V. As a temperature sensitive electric parameter (TSEP), a look-up table in Figure 13c, which contains the on-state resistance R ds,on (18 V) measured under 18 V gate voltage is used for the junction temperature estimation. In order to acquire R ds,on (18 V), a periodical 18 V gate signal illustrated in Figure 13a is produced for every 1 ms to measure the V ds,on . At the center of the 18 V gate signal, a trigger signal is generated by the controller to initiate the logging function of the oscilloscope. After that, the electric motor drive is driven by a 50 Hz three-phase current with a load profile I L (t) as depicted in Figure 13d for power cycling. The gate voltage profile V gs (t) is then regulated based on I L (t), with its amplitude changes from 18 V to 13 V. Junction temperature is estimated at last, which shows a reduction of 34.3% of the temperature swing by applying the proposed method. PSfrag replacements

Conclusions
In this paper, an extensive analytical power MOSFET model and the corresponding parameter extraction methods are introduced. Based on the presented model, a method is proposed to dynamically adjust the conduction losses for thermal stress reduction and lifetime enhancement of the power MOSFETs, by a novel dynamic gate driver. After that, thermal stability criteria are investigated to confine the gate voltage range, such that current focalization and the associated local heat up problems are prevented. The system performance and lifetime estimation are evaluated under different operation scenarios of an electric motor drive, which suggests an improvement of lifetime with a factor of four by hardly compromising the system efficiency at the high speed case. In addition, for applications that have a critical requirement on the lifetime, a circulation current injection method is applied to enhance the compensation efforts at low speed operation case, which significantly reduces the junction temperature swing down to 4.2 K. For experimental verification, a dynamic gate driver that supplies an adjustable gate voltage is realized. At last, power cycling tests are conducted on a three-phase electric motor drive prototype and the results show a reduction of 34.3% of the temperature swing, which confirms the thermal control method.  The gate voltage at TCP is derived by setting the derivative of the linear region current in (6) over temperature to zero.
which gives K lin 2K sat V ds = V gs,TCP − V th − n + θ 1 + θ × (V gs,TCP − V th ) −1 , To improve the system robustness, operation margins are added as follows: By reforming the equation of the linear region current in (6), V ds is expressed as:, , whereas V gs,TCP − V th 2 ≥ 2CI d K trvlin with C = K lin K p and K trvlin = K lin 1 + θ · (V gs − V th ) .
By plugging the V ds expression into the above inequality, we have: Finally, the gate voltage at TCP is derived as: To satisfy the above inequality, two conditions are required.