Comparative Performance and Assessment Study of a Current-Fed DC-DC Resonant Converter Combining Si, SiC, and GaN-Based Power Semiconductor Devices

: This paper focuses on the main reasons of low e ﬃ ciency in a current-fed DC-DC resonant converter applied to photovoltaic (PV) isolated systems, comparing the e ﬀ ects derived by the overlapping time in the gate-signals (gate-source voltage) combining silicon (Si), silicon carbide (SiC), and gallium nitride (GaN)-based power devices. The results show that unidirectional switches (metal–oxide–semiconductor ﬁeld-e ﬀ ect transistors (MOSFETs) plus diode) present hard switching as a result of the diode preventing the MOSFET capacitance of being discharged. The e ﬀ ectiveness of the converter was veriﬁed with a 200-W prototype with an input voltage range of 0–30.3 V, an output voltage of 200 V, and a switching frequency of 200 kHz. The reduction losses by applying GaN versus Si and SiC technologies are 66.49% and 53.57%, respectively. Alternatively, by applying SiC versus Si devices the reduction loss is 27.84%. Finally, according to the results, 60% of losses were caused by the diodes on both switches.


Introduction
Photovoltaic (PV) energy has received a great attention in research and industry because it is one of the most efficient and effective solutions to the environmentally friendly sources [1]. It can be classified into isolated systems and interconnected systems. Isolated systems represent those applications that store energy in battery banks, and the interconnected systems supply the generated energy by the PV panel to the electrical grid, satisfying standards as appropriate.
The interconnected systems represent one of the most studied applications, generally, they are represented by five stages. The first stage allows a low-frequency ripple. The second stage increases the voltage level from the PV according to the inverter specifications. The third and fourth stages represent the decoupling capacitor and the inverter, which has to fulfill three functions: 1. to shape the current into a sinusoidal waveform, 2. to invert the current into an AC current, and 3. if the PV array voltage is lower than the grid voltage, the PV array voltage must be boosted with an additional element. This last point is important because there must be no reverse energy to the DC source. Finally, the fifth stage filters the sinusoidal signal. and GaN power devices. Section 3 shows the experimental results. Section 4 presents a study of the power losses originating from the commutations and the overlap of the unidirectional switches used. Finally, Section 5 presents the conclusions.

Current-Fed DC-DC Resonant Converter and Power Devices
Based on [32], there are different configurations of CFRC. For this work, the studied current inverter is the two current sources resonant inverter. The resonant inductor of the parallel resonant tank is changed by a transformer to obtain galvanic isolation. The sinusoidal signal obtained from the parallel resonant tank is rectified with a full-bridge rectifier and filtered with an LC filter.
An important characteristic in a CFRC is that the current source must be short-circuited. The time in both switches (S 1 and S 2 ) during the short-circuit is named overlapping. In this time, the parallel resonant tank is isolated to the rest of the circuit. To obtain this isolating, it is necessary to use unidirectional switches to prevent the flow of AC current to the DC side of the inverter [33]. To establish unidirectional switches, it is possible to use two arrays: the first one by a diode in series with a MOSFET and the second one by an IGBT.
The general characteristics of both arrays have been discussed and compared before [34][35][36]. Basically, the primary disadvantage of IGBT is related to the operational frequency, since it can only operate in frequency ranges of up to 150 kHz. On the other hand, the array configured by a MOSFET in series with a diode partially solves the switching frequency problem. However, the primary problem with this configuration is the increase in parasitic capacitances (MOSFET and diode), which represent a substantial increase in power loss. Therefore, a selection of the semiconductor devices to be used in the experimental stage should be performed.
Considering remarks and because the motivation to use resonant converters is the relation of higher power/weight and power/size ratios, the arrangement to allow operation at a high switching frequency needs to be considered. In this manner, not only the large passive elements need to be considered in the converter design, but also the efficiency target and thermal design. Therefore, Figure 1 shows the CFRC studied. The topology shown in Figure 1 is comprised of four stages: the first stage consists of two current sources (L 1 and L 2 ) and a DC voltage source (V DC ), the second stage by a parallel resonant tank (L Primary and C R ) with magnetic isolation derived by L Primary , where L Primary is coupled to L Secondary (from part A to B), the third stage by a full-wave rectifier (D 3 -D 6 ), and the fourth stage by the decoupling elements (C c and L c ). The operation of the circuit is as follows: the two inductors L 1 and L 2 provide the two current sources to the parallel resonant tank, the unidirectional switches S 1 and S 2 short-circuit the current sources periodically in order to feed the parallel resonant tank formed by the transformer (composed by L Primary and L Secondary ) and the resonant capacitor C R with a square current waveform. The parallel resonant tank filters this waveform and applies a sinusoidal voltage waveform to the full-bridge rectifier (D 3 , D 4 , D 5 and D 6 ). The rectified signal is filtered by L C and C C and it is applied to the load (R LOAD ). One important characteristic of the CFRC (Figure 1) is the need to have an overlapped control, because if there is no overlapping control between M 1 and M 2 , the inductance (L 1 ) would be charged by the current i L1 (t), and the current i L2 (t) from the second inductance (L 2 ) would flow directly through the resonant tank. Under the dual condition, i L1 (t) would flow through the resonant tank and i L2 (t) through L 2 . However, if there is no overlapped control, i L1 (t) and i L2 (t) could be canceled, although not completely, producing a considerable increase in the losses on the unidirectional switches. Furthermore, the resonant tank and the components used need to be carefully selected, since these parameters directly affect the overlap signals in S 1 and S 2 . Additionally, the high frequency transformer is a critical part of the resonant converter. Its design affects efficiency, weight, and dimension of the whole topology. This fact is important to improve the efficiency of the topology. Considering these statements, a brief comparison of different semiconductor devices should be performed. As a result of the advancement in the field of power semiconductor technologies [37][38][39], SiC MOSFETs, SiC junction gate field-effect transistors (JFETs), SiC Schottky barrier diodes, and gallium nitride (GaN) transistors provide a valuable opportunity to obtain high efficient performance with compact size. Part of the primary characteristics in all power semiconductor devices are related to the operating at high power, high frequency, and high temperature. In fact, many works have been reported in the literature analyzing the physical breakdown mechanisms, modeling, characterizations, and the trade-off characteristics between the breakdown voltage and the on-resistance of Si, SiC, and GaN-based power semiconductor devices [40][41][42][43]. As a result of these studies, some characteristics are shown in Table 1. The capacity to achieve high switching frequency in every semiconductor is directly proportional to its drag-velocity. The speeds present in GaN devices are more than twice the speed in Si components, achieving commutations at much higher frequencies. However, a negative characteristic by GaN devices in comparison with Si and SiC is less thermal conductivity [44][45][46], which means the heat generation of SiC devices can be easily dissipated as compared to GaN. From the previous characteristics, one of the key behaviors to compare with these power devices in a CFRC is the overlap stage control. In this way, a brief study of this condition is presented below.
Overlap in Gate-Signals of M 1 and M 2 To determine the effect of the overlap, an initial simulation study is developed under the following considerations: (1) time delay proposed between the turn on of M 1 and M 2 is 0.49, this value was taken because T D must be as close as 0.5, with the aim of not having such a long overlap; (2) a quality factor of the resonant tank is sufficiently high to filter all the current harmonics, except the fundamental; (3) all inductors and capacitors are lossless; (4) D 3 , D 4 , D 5 , and D 6 are ideal diodes; and (5) unidirectional switches were performed by SiC diodes (C4D08120) and SiC MOSFETs (C2M0160120D), because of their improvements for AC-DC and DC-DC converters. These devices can operate with reduced conduction and switching losses over higher frequencies, and higher temperatures minimize the requirements for the passive components and reduce cooling demands [47][48][49]; however, the performance given by SiC power devices will be compared with Si and GaN. The switching frequency (F sw ) was considered to be 200 kHz. The simulation results in Figure 2 created in PSpice ® show the key waveforms of S 1 (Figure 2a Table 3. Design methodology.

Parameter Symbol Equation Value
Load  Figure 2, when the overlap begins (gate-signal in M 1 and gate-signal in M 2 are in the on-state), the current i S1 decreases to zero, and the current i S2 increases. This behavior is related to the charge and discharge of the internal stray capacitances of D 1 and D 2 .
In this sense, when S 2 is in the on-state, M 2 can be modeled by its output parasitic capacitance in parallel with its parasitic resistance, and D 2 as a parallel made up of the same diode and its stray capacitance. Furthermore, Figure 3 shows the hard switching in D 1 and M 1 caused by the effect given by the overlap. In this manner, to determine the converter performance effects, based on Figure 3, three modes are proposed considering the current and voltage waveforms of S 1 and S 2 ; therefore, the first mode (MODE A from t 0 to t 2 ) performs a fall-rise of i s1 and a rise-fall of i s2 , the second mode (MODE B from t 2 to t 3 ) represents the time when i s1 keeps its value and i s2 is zero, and the third mode (MODE C from t 3 to t 4 ) represents the dual condition of MODE B.  From Figure 3 and based on times t 0 to t 4 , the equivalent circuits are obtained, as shown in Figure 4. In these circuits, an equivalent resistance (R equ ) was considered as the load in the resonant tank, where R equ represents the R LOAD seen from L r . Then, based on the operation, MODES are shown during the overlap and equivalent circuits in Figures 3 and 4, respectively. The modes A, B, and C are detailed below: Time t 0 -t 1 (Figure 4a): this time starts when the gate-signal in M 2 is in the on-state, thereby the overlap starts. During this time, i S1 decreases to zero (and remains at 0 A) and i S2 increases its value the same as the input current (I L ). Moreover, since S 2 is in the on-state, the diode D 1 can be modeled as a parallel by the same diode and its stray capacitance C D1 , and M 1 by a drain-source resistance R DSON M1 . In this moment, the voltage of the stray capacitance in D 1 (V CD1 ) can be represented as shown in Equation (1).
where V RES is the voltage of the resonant tank, V DSM1 represents the voltage drain-source in M 1 , V DSM2 the voltage drain-source in M 2 , and V D2 the forward voltage in D 2 . Furthermore, in this time, there is a "charge" condition in C D1 which generates an increase of switching losses in S 1 until the voltage in D 1 reaches its forward voltage. Time t 1 -t 2 : It represents the instant when i S1 increases and i S2 decreases its value, turning on S 1 , and modeled D 2 as a parallel by D 2 and its stray capacitance C D2 , and M 2 by a drain-source resistance R DSON M2 (Figure 4b). In this time, the voltage of the stray capacitance in D 2 (V CD2 ) can be represented as shown in Equation (2), where V D1 represents the forward voltage in D 1 .
Time t 2 -t 3 : In MODE B (Figure 4c), M 1 and M 2 are in the on-state. Furthermore, i s1 stays constant and i s2 stays at 0A, modeling D 2 and M 2 the same as from t 1 to t 2 . On the other hand, there is no current in S 2 but there is a voltage in D 2 , increasing the power losses. Moreover, the voltage of the stray capacitance in D 2 (V CD2 ) can be represented the same as Equation (2).
Time t 3 -t 4 : MODE C starts (Figure 4d), the gate-signal in M 1 is in the off-state, and thus the overlap is finished. Furthermore, M 2 is in the on-state and i s2 is increasing. During this time, S 1 is in the off-state after finishing the discharging process, which causes the stored energy to be lost not only in M 2 but also in D 2 . Additionally, as a result of M 1 in the off-state, V RES will be split in D 1 and M 1 with a complementary voltage in D 2 . In fact, V CD2 can be modeled as shown in Equation (3).
From Figures 3 and 4, the behavior given by the recovery time in D 1 and D 2 during their shutdown states causes D 1 and D 2 to be in the on-state even when M 1 and M 2 are in the off-state, which indicates that if the complete switch is analyzed, the MOSFET and diode do not share the same shutdown time. Furthermore, in MODE A, i S2 increases, and the stray capacitance in D 1 is discharging, causing i S1 to decrease to zero, then, the current i S1 increases its value because the current i S2 decreases. This current will be zero, until the voltage in D 2 is zero again.
In this sense, when the voltage in D 2 is zero, the current i S2 will increase, therefore, this is the main reason to generate hard switching in the complete switch. On the other hand, the power losses achieved in the simulation by S 1 plus S 2 are 31 W with a global efficiency of 62% and a time delay between gate-signals of 0.49. It is important to estimate the applied overlap. Therefore, Figure 5 shows the overlap to consider in the analysis. From Figure 5, D is the applied duty cycle, the time delay between the gate-signals of M 1 and M 2 (V GSM1 and V GSM2 ), and represents the overlap time when M 1 and M 2 are in the on-state. As mentioned, T T is defined in Equation (4) and T D is defined in Equation (5).
Replacing (4) into (5) and considering that the energy transferred to the load depends on the duty cycle, the selected duty cycle of the resonant tank is 0.5.
To assess the combination of power semiconductor devices in the unidirectional switch and to verify Equation (7) based on the parameters and design methodology described above, three different converters are designed combining Si-MOSFET and diode (first array), SiC-MOFET and diode (second array), and GaN-transistor SiC-diode (third array). The power devices are selected based on the stress level calculations as well as the similarity in the electrical ratings between the Si and SiC devices (as a result of the reduced drain to source voltage in the GaN-transistor), parasitic capacitances, current rating, switching speed, on-resistance, maximum junction temperature, and following the primary comparison between the characteristics of every device [50,51], mainly focused in the work presented in [52]. Therefore, Table 4 shows the specifications of each power device used in the design. Table 4. Characteristics of the power semiconductor devices.

Model
Device Characteristics Material  According to Figure 6 and considering T D = 0.5, a global efficiency and total power losses (switching plus conduction) in S 1 plus S 2 of 86% and 27 W were performed by the Si-MOSFET and Si-diode combination. Furthermore, SiC-MOSFET plus SiC-diode performed an efficiency and power losses in S 1 plus S 2 of 92.7% and 14 W, respectively. Finally, the performance given by the combination of GaN-transistor plus SiC-diode were similar to the combination of SiC-MOSFET plus SiC-diode with an efficiency of 94% and power losses in S 1 plus S 2 of 11 W.

EPC2007C Transistor
Moreover, the performance given by the overlap dramatically affects the efficiency of the whole converter, thus, it is suggested to take into account an overlapped control in a CFRC since the problems associated with the discharging of the transistor output the capacitance (C out ). When the switch voltage increases, the MOSFET (M 1 ) C out is charged via D 1 to the peak value of the switch voltage, and then remains at that voltage until the transistor turns on. At this time, the capacitance C out is discharged through the transistor, resulting in switching loss. According to Figure 6, with T D estimated to be 0.5, the power losses in S 1 plus S 2 and global efficiency performed by SiC-MOSFET plus SiC-diode were 14 W and 92.7 %, which performance is reasonably similar in comparison with the combination of GaN-transistor plus SiC-diode. In this way, the complete simulation results achieved from the DC-DC resonant converter performed by SiC-MOSFET plus SiC-diode are presented in Figure 7. The key waveforms from the resonant tank in Figure 7 show the previously calculated overlap of M 1 and M 2 . Alternatively, both the input current (i Re ) and voltage (V Re ) at the resonant tank show a condition close to resonance since both signals are in phase. Furthermore, the output voltage (V r ) is 207 V, which indicates that the parameters proposed in Table 2 have a relative error of 1.42% between them and the simulation results.
On the other hand, with the aim to compare the performance and conditions given for the topology, a comparison of a non-overlapped ( Figure 8a) and overlapped control (Figure 8b) was made, focusing its attention on v S1 and i S1 . From Figure 8a, with a non-overlapped control, not only the voltage and current on S1, but also the resonance condition will be dramatically affected, causing negative voltages, as shown in Figure 8a. This issue would affect the entire efficiency because an overlap control provides a ramp shift signal to the ramp generator in response to a detection signal that indicates activity of the switches in the power stage. The ramp shift signal adjusts the first and second ramp signals relative to each other so as to minimize any gap and any overlap between the first and second ramp signals.
In this way, to have a good relation overlap-efficiency, an important point to consider is to work with an overlapped control to have optimal conditions, as shown in Figure 8b. Furthermore, Figure 8b shows less power losses as a result of the less current peaks obtained in comparison with the non-overlapped behavior presented in Figure 8a. Tables 2 and 3, the experimental prototype was elaborated. For experimental results, power devices used in the different combinations are shown in Table 4. Inductors were designed based on the Kg methodology [53], the PWM control optimized for high switching frequency, and the drivers used were UC3825 and MIC4452, respectively Furthermore, T D = 0.5 was considered. The elaborated prototype is shown in Figure 9. Developing the experimental prototype at maximum power, the experimental results under different combinations of power devices are briefly described below by applying the OHMITE Rheostat RRS250E as a resistive load, which can be operated at a maximum ohmic and power value of 250 Ω and 500 W, respectively:

Overlap and Performed Efficiency by Si-Based Power Devices
For the first analysis, Figure 10 shows the overlapping signals (gate-source voltage) between M 1 and M 2 . From Figure 10, the performance given for silicon devices presents disturbances in the gate-signal modulation derived by the parasitic capacitance of each MOSFET. This noise will be reflected in the resonant tank. Moreover, S 1 and S 2 will be affected because of the reverse recovery current of D 1 and D 2 , which will be reflected in the drain current of M 1 and M 2 .
Additionally, it is well-known that Si power devices present a greater variation of non-linearity behavior of the output capacitance, whereas the low voltage part of the output capacitance increases due to higher area specific density. The high voltage part of the output capacitance decreases with the area shrink factor of the device, increasing the power losses and consequently affecting the overall performance of the converter. In this way, there is a need to study the performance given by new power devices technologies that permit a reduction of the high voltage part of the output capacitance leads to significant lower energy values being stored in it, because turning off Si devices with lossless would require to turn off the channel current before the voltage significantly rises across the device. The shape of the output capacitance, being charged by the full load current, will determine the voltage waveform. Conversely, the gain in the energy stored in the output capacitance, being dissipated as heat in hard switching applications during turn-on, is hence correlated to an increase of switching frequency. On the other hand, the overlapped signal in Figure 10 shows an operation frequency of ≈200 kHz, considering a duty cycle of 50%. In contrast, another important parameter is to determine the electrical efficiency; therefore, Figure 11a shows the input (Pin) and output power (Pout) as well as the efficiency (Figure 11b) obtained in the implemented topology. According to the results, the converter efficiency is 83% and the loss is 32.8 W, which are significant. Additionally, as a result of the efficiency obtained with an optimized T D = 0.5, all losses were calculated to assess the electrical performance in all elements. To evaluate the passive elements, references [54] and [55] were used. In the case of capacitors, the loss is primarily from the equivalent series resistance (ESR), which is typically provided in the datasheet. Finally, the total power losses in MOSFETs are composed of switching and conduction losses; on the other hand, the total power losses in diodes are the sum of conduction, reverse, and switching losses. In this manner, Table 5 presents the total power losses on all elements of the experimental prototype, which parts of the estimated results were obtained from [34,36,55]. From Table 5, S 1 and S 2 present the higher total power losses, which indicates a similarity with the analysis presented in Section 2. Alternatively, in order to determine the distribution of power losses on the unidirectional switch, a study is presented in Section 4.

Overlap and Performed Efficiency by SiC-Based Power Devices
The second converter was developed by applying the second array of power devices. Figure 12 shows the gate-source voltage. Compared with Si devices, the overlap presented shows a reasonably better performance. The results show less disturbances in the gate-signal modulation derived by the parasitic capacitance of M 1 and M 2 , since SiC devices present vertical current flow from the top surface to the bottom surface and have a blocking pn-junction with injection of bipolar carriers in reverse operation. In this sense, the reverse recovery charge is more than one magnitude lower than in corresponding silicon devices. The results from Figure 12 make SiC components very suitable for applications with continuous hard commutation of the body diode as shown in the efficiency obtained (Figure 13b) according to the input and output power (Figure 13a). Furthermore, since the output capacitance is lower than in Si-based power devices, the stored energy in the output capacitance is comparable to GaN HEMTs semiconductors.
According to the results, the CFRC presents an incremented efficiency of 4% in comparison with Si devices. This results in 87% efficiency and losses of 26 W, which are quite significant. The distribution of these power losses is described in Table 6.   From Table 6, the performance given by SiC power devices presents a better performance in comparison with Si-based power technology. In fact, the percentage power reductions in comparison with the first array are shown in Table 7.  Table 7, the components with the highest change are S 1 and S 2 with a considerable reduction of 27.84%, which results will be compared in Section 4.

Overlap and Performed Efficiency by GaN-Transistor and SiC-Diode
The third CFRC is designed considering the third array. Alternatively, since the topology under study is capable to works on a switching frequency of up to 200 kHz, a considerable reduction of the total power losses on the switch is not expected as a result of the reduction of the parasitic capacitance in the GaN-transistor. In this sense, the overlapping signals between M 1 and M 2 are shown in Figure 14. Based on Figure 14, the overlap signals in M 1 and M 2 show a better performance by applying GaN-transistors because of the zero reverse recovery charge, which starts when the drain voltage falls below the sum of the gate potential and the threshold voltage, thus creating a reverse channel. This unique characteristic makes GaN-transistors the first choice for applications with continuous switching on a reverse biased device such as in half-bridge or full-bridge configurations. However, GaN power devices represent the best solution for high switching frequency applications. In this way, SiC power devices have similar efficiency and qualities by applying the same switching frequency in the CFRC presented in this work as shown in Figure 15. According to Figure 15, the converter has an efficiency of 89% and losses of approximately 21.34 W. The power losses distribution is presented in Table 8. From Table 8, the performance given by the combination of GaN-transistor and SiC-diodes presents a better performance in comparison with Si and SiC-based power technologies.
In this way, the power reduction percentage in comparison with Si and SiC power devices are shown in Tables 9 and 10, respectively. From the comparison presented in Table 9, there is a considerable power reduction percentage as a result of the hybrid combination of GaN-transistor plus SiC-diode. Moreover, from the comparison in Table 10, the components with the highest change are S 1 and S 2 with a reduction of 21.43%. On the other hand, not only the losses in power devices are reduced but also in passive elements. The main reason is due to the input current ripple reduction, as shown in the input power ripple in Figures 11, 13 and 15, thus the conduction power losses are reduced. However, the converter electrical efficiency does not increase significantly and remains at approximately 89%. These results will be compared and analyzed in the following section.

Switching Loss Analysis
The switching losses of S 1 and S 2 for the different combinations of power devices consist of turn-on and turn-off loss, reverse recovery loss of the body diode, and output capacitance loss (C oss ). The output capacitance loss effect is presented when S 1 is in on-state because during both charging and discharging, the loss is generated. Therefore, the total additional loss caused by parasitic capacitances C oss from S 1 and S 2 estimated with the drain-source voltage charged is defined in (8).
where C oss(total) = C oss(S1) + C oss(S2) is the total parasitic capacitance of the two switches. Therefore, regarding these issues and based on [56], Tables 8 and 9 show the power loss distribution of S 1 (MOSFET and diode) with T D = 0.5 by applying the different combinations of power devices. In this way, the results for S 2 basically are the complementary losses of S 1 . According to Tables 11 and 12, the power losses in S 1 and S 2 considering T D = 0.5 show that 60% of the total power losses are caused by D 1 and D 2 . This means that the primary problem caused by the use of unidirectional switches and overlap is related to the high voltages that will be absorbed by the parasitic capacitances of the power devices, increasing switching losses as a result of the diode in series with the MOSFET, preventing the MOSFET output capacitance from being discharged before the ZVS event. As a result of the use of unidirectional switches in a CFRC, the switching stage will require power devices with low or zero reverse recovery charge, thus showing a clear value proposition for both GaN HEMTs and SiC devices, with both lower stored energies in the output capacitance, faster turn-off, and lower reverse recovery charge. On the other hand, GaN HEMTs power devices show better performance benefits as compared to their SiC counterparts by increasing the switching frequency. However, according to the topology under study, the use of both SiC and GaN power devices present a comprehensive similar performance.
As a result of the combination of Si, SiC, and GaN-based power devices in the CFRC applied to a PV-interconnected system in the DC-DC stage, at moderate switching frequencies, typically below 200 kHz, silicon carbide devices can compete. If switching frequencies move up to 400 kHz or above, the energy stored in the output capacitance will increases. In this case the value of GaN is significantly higher than its silicon counterparts. In fact, the benefits to the use of GaN power devices lies in its significantly lower charge stored in the output capacitance and its perfect linearity of the output capacitance. Additionally, the intrinsic capability to cope with hard commutation events in case of control errors is an additional benefit versus silicon and silicon carbide-based power devices.

Conclusions
This paper presents part of the key performance indicators for a CFRC combining Si, SiC, and GaN-based power devices. Regarding losses, one of the main problems associated with the low efficiency is related to the management that the overlap provides on the behavior of the unidirectional switch during the overlap the diode, preventing the MOSFET capacitance from being discharged.
The performance development by the unidirectional switches presents ZVS (Zero Voltage Switching) and ZCS (Zero Current Switching); however, hard switching appears when every device (MOSFET or diode) is analyzed independently. This issue is derived as a result of the energy losses in the parasitic capacitances of the MOSFET and diode. Furthermore, there is a recovery time on D 1 and D 2 in their shutdown states, generating that diodes are on-state even when the MOSFETs are off-state. Therefore, 60% of the total losses are generated by the diodes. Conversely, the percentage power reduction of GaN-transistor versus Si and SiC MOSFETs is approximately 66.49% and 53.57%, respectively. Additionally, the percentage power reduction of SiC-MOSFET plus SiC-diode versus Si-MOSFET plus Si-diode is around 27.84%.
The value proposition of SiC devices relies on the same arguments like for GaN devices with key performance indicators; however, not entirely reaching the level of corresponding GaN power devices for topologies that increase the switching frequency.
On the other hand, compared to conventional topologies, the proposed converter has continuous input current, and thus a capacitor in series with the photovoltaic panel is not necessary. Furthermore, the proposed converter does not present stability problems, and thanks to the arrangement of the parallel resonant tank, the topology provides galvanic isolation.

Conflicts of Interest:
The authors declare no conflict of interest.