Synchronization and Sampling Time Analysis of Feedback Loop for FPGA-Based PMSM Drive System

: The proportional-integral (PI)-based control for the motor drive system is commonly used in industrial applications. However, motor drive system development and prototyping are tedious tasks especially considering a ﬁeld programmable gate array (FPGA)-based real-time system implementation. In addition, the time-synchronization of the feedback control loop is another vital aspect concerning sampling time for the discrete-time controller. This paper presents an FPGA-based design and development of a permanent magnet synchronous motor (PMSM) drive system considering the impact of time-synchronization corresponding to the sampling time criteria for a feedback control loop. Furthermore, the repercussion of time-synchronization is examined for the transient conditions due to a step change in load as well as motor speed. The ﬁeld-oriented control (FOC) of the PMSM drive system is designed and implemented for the system authentication using a digital model integration approach provided by the Xilinx system generator (XSG) and VIVADO platform. Moreover, harmonic distortion in the motor current is considered for an in-depth analysis of the system performance corresponding to sampling time as well as switching frequencies.


Introduction
The energy conversion is an essential part of an electrical power system. The electrical motors are one of the major parts of electromechanical energy conversion (EMEC) system that is used for conversion of electrical energy into mechanical energy. The motors have been used in a wide variety of applications from industrial systems to domestic appliances [1][2][3][4]. Due to the advantages such as high power density, high torque to weight ratio, higher efficiency and lower maintenance cost the permanent magnet synchronous motor (PMSM) has been used in low power range applications such as robotics, actuators and machine tools as well as in high power applications for industrial drives, vehicular propulsions, aerospace system and traction [5][6][7][8].
The controlled operation of a motor is highly essential corresponding to system applications to achieve the desired motor speed and smooth transition considering the change in motor load conditions. Several linear and nonlinear controls have studied and implemented PMSM speed control. The nonlinear controls such as hysteresis control and predictive control are implemented for the motor drive system [9][10][11]. These controllers have their own advantage; however, they have a better performance at higher sampling time. In the linear control such as the proportional-integral (PI)-based field-oriented control (FOC) PMSM drive has been implemented for industrial applications because of its simple structure and reliability [12,13]. This controller implementation reproduces the dynamic behavior of the PMSM similar to that of the DC motor [14].
The control algorithm for the motor drive system has been developed using digital signal processors (DSPs) [15][16][17]. However, the DSP-based implementations suffer from long execution time and high memory allocation of the CPU. Considering the above demerits of the DSP, the field programmable gate array (FPGA) having advantages of parallel processing, programmable hard-wired feature, fast computation ability, shorter design cycle and an embedded processor, is more effective for the controller execution [18][19][20]. In [21], an FPGA-based FOC for PMSM drive is developed, and for the FPGA-based architecture for the sensor, less speed control of PMSM is presented in [22]. FPGA-based PMSM drive system development has not been scrutinized considering time-synchronization for a feedback control loop concerning its implications on system performance especially in transient conditions.
The feedback control loop of the motor drive system consists of a speed controller (outer control loop) and a current controller (inner control loop). The time constant of the speed controller loop is different to the current control loop [23]. The performance of the motor drive system is governed by the bandwidth of the current control and switching frequency selection is crucial to achieve the desired bandwidth [24,25]. However, the increase in switching frequency will ultimately lead to the higher system losses.
Besides the switching frequency, the digital implementation of control involves the vital role of sampling frequency for the performance of a motor drive system [26]. Nevertheless, the sampling frequency is having a vital impact on system performance especially during the transient condition.
There are no specific criteria available to decide the appropriate selection of sampling frequency. In [26], a lower limit is mentioned corresponding to a specific control and the bandwidth can be taken as one sixth of the sampling frequency. Furthermore, the digital delay of the control loop that consists of the throughput time of the AD converter, delay introduced by the converter in terms of dead time and computation time for the control execution constrained the controller bandwidth [24]. Consequently, the role of sampling frequency involves more complexity considering the performance of a motor drive system.
In general, the sampling rate of the speed controller is slower compared to that of the sampling rate of the current controller. As the control loops operate at different data sampling rate, the impact of time synchronization between these controllers is a crucial concern considering the transient conditions corresponding to the sampling rates. The motor speed is related to mechanical parameter and the sampling rate is predefined corresponding to the encoder setting. The sampling rate of the motor current is possible to control, corresponding to the maximum possible throughput rate of the AD converter. Consequently, the performance of the current control loop can be influenced under transient condition.
In the case of a motor drive system, the impact of sampling frequencies (throughput rates) is not yet analyzed categorically. The impact of sampling frequencies is required to probe the performance of the controller under transient conditions because the higher throughput rate will not necessarily result in improved performance. In addition, the indirect impact of throughput rate on speed controller is also one of the key points corresponding to a change in the reference speed of the motor. The repercussion of time synchronization on control loops corresponding to sampling frequencies is another crucial concern considering the transient conditions: change in reference speed and load disturbance. This paper presents an FPGA-based design and development of a PMSM drive system considering the impact of time-synchronization for feedback control loops corresponding to sampling frequencies.
A step-by-step and case-by-case time synchronization methodology is considered to analyze the repercussion of sampling frequencies corresponding to feedback control loop synchronization. The harmonics in a motor current are also taken into account for different switching frequencies and sampling frequencies correspondingly. Furthermore, a step change in reference speed as well as load disturbance is introduced to investigate the transient/dynamic behavior of the system. The controller is developed in the Xilinx system generator (XSG) environment integrated with the MATLAB/Simulink for the FPGA-based experimental system implementation.
The paper is organized as follows: Section 2 describes the mathematical model of PMSM, the controller designing and the step by step XSG based system implementation. The FPGA based system implementation is described in the Section 3. The experimental validation of the system performance is explained in the Section 4. Finally, the conclusions of the paper are presented in Section 5.

PMSM Drive
The motor structure consists of stator and rotor parts. The rotor part is responsible for the generation of the rotating magnetic field. The interaction between the rotor flux and the stator flux provides the desired torque. The stator dynamic equations in the rotating dq reference frame is give as: The i d and i q represent the stator current components in dq frame. L s and R s represents the stator winding inductance and resistance. v d and v q are the stator voltage component in the dq rotating frame corresponding to the three-phase stator voltage. The rotor electrical angular speed and the flux produced by the rotor magnet are represented by ω e and ϕ.
In case of the surface permanent magnet synchronous motor (SPMSM) the q axis current component is only responsible for the generation of the required torque. Mathematically the electromagnetic torque T e generation is given by: The mechanical dynamics of the motor have slower response compared to that of the electrical dynamics. Mathematically the mechanical dynamics of the motor can be described as: where ω m is the rotor angular mechanical speed, T l is the mechanical load torque, J is the moment of inertia and B is the viscous friction coefficient. The rotor electrical angular speed ω e and the electrical angular position θ e are given by: where, p p represents the number of pole pairs of the motor.

Field Oriented Control
The field-oriented control for the speed control of the PMSM is presented in the Figure 1. The FOC is a simple vector control which can control both the phase as well as the phase current magnitude of the motor. The implementation methodology of the control includes a speed control loop and the current control loop. Finally, the switching signal is generated for the power devices of the inverter. The speed control loop evaluates the reference quadrature axis current iqref to control the current magnitude corresponding to the speed and load torque of the motor. The iqref in the stationary reference frame is evaluated by feeding the speed error signal through PI controller. The equation involved for the generation of the reference current signal is given as: where s is the Laplace operator and ωer is the error between the reference speed ω* and the measured speed, represented as: id and iq are obtained from the sensed three phase current of motor using the Clarke's and Park's Transformations. id and iq are compared are the reference current idref and iqref, respectively. idref is kept as zero, as the motor torque for a SPMSM depends upon the quadrature axis current [27]. The error signals ider and iqer are converted to the equivalent voltages vd and vq, respectively through the PI controller. The following represent the d-q axis reference voltage equations:

Controller Design in XSG
XSG is a digital designing tool integrated with the MATLAB/Simulink and can be used for the FPGA-based system development. The model-based design in XSG has the functionality for automatic generation of the hardware description language (HDL) code that can be readily used for the real-time operation of FPGA-based system. FOC-based speed control of the PMSM drive system The speed control loop evaluates the reference quadrature axis current i qref to control the current magnitude corresponding to the speed and load torque of the motor. The i qref in the stationary reference frame is evaluated by feeding the speed error signal through PI controller. The equation involved for the generation of the reference current signal is given as: where s is the Laplace operator and ω er is the error between the reference speed ω* and the measured speed, represented as: i d and i q are obtained from the sensed three phase current of motor using the Clarke's and Park's Transformations. i d and i q are compared are the reference current i dref and i qref, respectively. i dref is kept as zero, as the motor torque for a SPMSM depends upon the quadrature axis current [27]. The error signals i der and i qer are converted to the equivalent voltages v d and v q , respectively through the PI controller. The following represent the d-q axis reference voltage equations:

Controller Design in XSG
XSG is a digital designing tool integrated with the MATLAB/Simulink and can be used for the FPGA-based system development. The model-based design in XSG has the functionality for automatic generation of the hardware description language (HDL) code that can be readily used for the real-time operation of FPGA-based system. FOC-based speed control of the PMSM drive system is designed and modelled in MATLAB/Simulink using XSG blockset. The modelling of the FOC is considered in three parts which is explained in detail.

Outer Speed Control Loop
The outer control loop of the FOC consists of a PI controller to regulate the motor speed. The implementation of the speed controller in XSG is presented in the Figure 2a. The PI controller implementation in FPGA using discrete-time domain platform of XSG, requires the discretization of dynamic Equation (7). Euler's forward method is used [28] for the discretization of the controller. The discretized equation for the PI control is presented as: where i * q (k) and ω er (k) are the reference q axis stator current and speed error at the instant k. g ω (k) is the output of the integral control at the instant k. T s is the sampling time. is designed and modelled in MATLAB/Simulink using XSG blockset. The modelling of the FOC is considered in three parts which is explained in detail.

Outer Speed Control Loop
The outer control loop of the FOC consists of a PI controller to regulate the motor speed. The implementation of the speed controller in XSG is presented in the Figure 2a. The PI controller implementation in FPGA using discrete-time domain platform of XSG, requires the discretization of dynamic Equation (7). Euler's forward method is used [28] for the discretization of the controller. The discretized equation for the PI control is presented as: where iq*(k) and ωer(k) are the reference q axis stator current and speed error at the instant k. gω(k) is the output of the integral control at the instant k. Ts is the sampling time.

Inner Current Control Loop
The control of the dc motor is easier as the speed is directly proportional to the current. However, in case of the ac motor in order to achieve similar kind of behavior, the co-ordinate transformation is an essential part of the controller design. Initially, abc-dq transformation is performed using an enable signal for conversion form three phase to two phase system abc-αβ, and subsequently, the conversion of two-phase system to synchronously rotating frame αβ-dq transformation using sin-cos shown in the Figure 2b.

Inner Current Control Loop
The control of the dc motor is easier as the speed is directly proportional to the current. However, in case of the ac motor in order to achieve similar kind of behavior, the co-ordinate transformation is an essential part of the controller design. Initially, abc-dq transformation is performed using an enable signal for conversion form three phase to two phase system abc-αβ, and subsequently, the conversion of two-phase system to synchronously rotating frame αβ-dq transformation using sin-cos shown in the Figure 2b.
In the inner current control loop, two PI controllers are used as shown in Figure 2c to generate an equivalent voltage quantity for generation of switching signals. Similar to the speed PI controller, the current PI controller is represented for dq quantity in the discrete-time domain as: where v d (k) and v q (k) are the stator reference voltage at the instant k. i der (k) and i qer (k) are the current error signal at the instant k. g d (k) and g q (k) are the output of the integral control at the instant k.
Further, dq-abc transformation is performed, as shown in Figure 2d to convert into three phase voltage quantity for the generation of the switching signal.

Switching Signal Generation
The Sine triangle pulse width modulation (SPWM) is considered for the generation of the switching signal. The switching signal is generated using a PWM technique that requires a carrier wave and modulating wave. The triangular waveform as a carrier signal of frequency f sw , is generated by using the fundamental blockset of the XSG, as shown in Figure 3. The sinusoidal three phase voltage waveform as a modulating signal is compared with the triangular wave to generate the switching pulses for a three-phase inverter system. A free running up counter block is used to generate a ramp signal. If the counter count for the ramp signal is greater than the desired triangular wave frequency the counter will be reset. Afterwards, the counter output is compared to that of the half of the triangular wave frequency. Finally, an up/down counter is used to perform the increment when the value is 1 and decrement when the value is zero. For the generation of the switching signal, the carrier wave is compared to that of incoming reference voltage signal and updated immediately. The Inverter used for the experimental validation has an inbuilt inversion circuit with dead time compensation for the PWM signal. Therefore, the switching signals are only generated for the upper half power devices of the inverter. In the inner current control loop, two PI controllers are used as shown in Figure 2c to generate an equivalent voltage quantity for generation of switching signals. Similar to the speed PI controller, the current PI controller is represented for dq quantity in the discrete-time domain as: where vd(k) and vq(k) are the stator reference voltage at the instant k. ider(k) and iqer(k) are the current error signal at the instant k. gd (k) and gq (k) are the output of the integral control at the instant k. Further, dq-abc transformation is performed, as shown in Figure 2d to convert into three phase voltage quantity for the generation of the switching signal.

Switching Signal Generation
The Sine triangle pulse width modulation (SPWM) is considered for the generation of the switching signal. The switching signal is generated using a PWM technique that requires a carrier wave and modulating wave. The triangular waveform as a carrier signal of frequency fsw, is generated by using the fundamental blockset of the XSG, as shown in Figure 3. The sinusoidal three phase voltage waveform as a modulating signal is compared with the triangular wave to generate the switching pulses for a three-phase inverter system. A free running up counter block is used to generate a ramp signal. If the counter count for the ramp signal is greater than the desired triangular wave frequency the counter will be reset. Afterwards, the counter output is compared to that of the half of the triangular wave frequency. Finally, an up/down counter is used to perform the increment when the value is 1 and decrement when the value is zero. For the generation of the switching signal, the carrier wave is compared to that of incoming reference voltage signal and updated immediately. The Inverter used for the experimental validation has an inbuilt inversion circuit with dead time compensation for the PWM signal. Therefore, the switching signals are only generated for the upper half power devices of the inverter.

FPGA System Implementation
The feedback control implementation of the PMSM drive system requires sensing of the control parameters: motor speed and current. Further, the sensed parameters are needed to feed to the control environment. Analog to digital converter (ADC) is used to feed the sensed control parameters to the digital control environment. PMSM drive system in Figure 4 is designed and developed using the digital control environment of FPGA. The encoder unit has the purpose to sense the rotor angular

FPGA System Implementation
The feedback control implementation of the PMSM drive system requires sensing of the control parameters: motor speed and current. Further, the sensed parameters are needed to feed to the control environment. Analog to digital converter (ADC) is used to feed the sensed control parameters to the Electronics 2020, 9,1906 7 of 19 digital control environment. PMSM drive system in Figure 4 is designed and developed using the digital control environment of FPGA. The encoder unit has the purpose to sense the rotor angular speed and angular position by generating pulses with a resolution of 2048 counts per revolution. The position and speed detector calculates the speed and rotor positions using the encoder pulses. The motor current sensed through a current sensor and fed to the FPGA through an ADC as shown in Figure 4. These currents are further passed through the PI controller unit. The control unit along with the ADC-digital to analog converter (DAC) interface unit and PWM generation unit is programmed to the FPGA board. The DAC interface unit is used to convert the controlled parameters into an analog signal, and it is measured and recorded through memory Hi-corder for monitoring and validation.
Electronics 2020, 9, x 7 of 19 speed and angular position by generating pulses with a resolution of 2048 counts per revolution. The position and speed detector calculates the speed and rotor positions using the encoder pulses. The motor current sensed through a current sensor and fed to the FPGA through an ADC as shown in Figure 4. These currents are further passed through the PI controller unit. The control unit along with the ADC-digital to analog converter (DAC) interface unit and PWM generation unit is programmed to the FPGA board. The DAC interface unit is used to convert the controlled parameters into an analog signal, and it is measured and recorded through memory Hi-corder for monitoring and validation.

ADC Interface
An interface program is developed for the operation of ADC to feedback the signal to FPGA. The schematic diagram in Figure 5 represents the ADC interfacing and pin configuration of PMOD (Peripheral Module) AD1. PMOD AD1 is consisting of a 12-bit, two-channel AD7476A ADC with maximum possible sampling rate up to 1MSPS [29]. PMOD AD1 has six input pins that is for two analog input signals (ia and ib) with their respective ground pins and a power supply pin (VCC) with its respective ground pin (GND). Similarly, the PMOD AD1 has six output pins that are connected to the FPGA, consisting of a clock pin (Clk), chip select (CS) pin, two digital data output pins (D1 and D2) and a VCC with its respective GND. Clk and CS signals are provided from FPGA using the ADC interface program block as shown in Figure 5. The conversion and data acquisition process is governed by the CS signal. The falling edge of the CS initializes the sampling of data as well as the data conversion. The digitized data D1 and D2 are synchronized at the rate of sampling frequency using the start signal through the ADC

ADC Interface
An interface program is developed for the operation of ADC to feedback the signal to FPGA. The schematic diagram in Figure 5 represents the ADC interfacing and pin configuration of PMOD (Peripheral Module) AD1. PMOD AD1 is consisting of a 12-bit, two-channel AD7476A ADC with maximum possible sampling rate up to 1MSPS [29]. PMOD AD1 has six input pins that is for two analog input signals (i a and i b ) with their respective ground pins and a power supply pin (VCC) with its respective ground pin (GND). Similarly, the PMOD AD1 has six output pins that are connected to the FPGA, consisting of a clock pin (Clk), chip select (CS) pin, two digital data output pins (D 1 and D 2 ) and a VCC with its respective GND.
Electronics 2020, 9, x 7 of 19 speed and angular position by generating pulses with a resolution of 2048 counts per revolution. The position and speed detector calculates the speed and rotor positions using the encoder pulses. The motor current sensed through a current sensor and fed to the FPGA through an ADC as shown in Figure 4. These currents are further passed through the PI controller unit. The control unit along with the ADC-digital to analog converter (DAC) interface unit and PWM generation unit is programmed to the FPGA board. The DAC interface unit is used to convert the controlled parameters into an analog signal, and it is measured and recorded through memory Hi-corder for monitoring and validation.

ADC Interface
An interface program is developed for the operation of ADC to feedback the signal to FPGA. The schematic diagram in Figure 5 represents the ADC interfacing and pin configuration of PMOD (Peripheral Module) AD1. PMOD AD1 is consisting of a 12-bit, two-channel AD7476A ADC with maximum possible sampling rate up to 1MSPS [29]. PMOD AD1 has six input pins that is for two analog input signals (ia and ib) with their respective ground pins and a power supply pin (VCC) with its respective ground pin (GND). Similarly, the PMOD AD1 has six output pins that are connected to the FPGA, consisting of a clock pin (Clk), chip select (CS) pin, two digital data output pins (D1 and D2) and a VCC with its respective GND. Clk and CS signals are provided from FPGA using the ADC interface program block as shown in Figure 5. The conversion and data acquisition process is governed by the CS signal. The falling edge of the CS initializes the sampling of data as well as the data conversion. The digitized data D1 and D2 are synchronized at the rate of sampling frequency using the start signal through the ADC Clk and CS signals are provided from FPGA using the ADC interface program block as shown in Figure 5. The conversion and data acquisition process is governed by the CS signal. The falling edge of Electronics 2020, 9, 1906 8 of 19 the CS initializes the sampling of data as well as the data conversion. The digitized data D 1 and D 2 are synchronized at the rate of sampling frequency using the start signal through the ADC interface and it generates the CS signal corresponding to the start signal condition. Once the acquisition following the sampling as well as conversion of the analog data is completed, it generates a done signal as shown in Figure 5. The AD converter works at 1MSPS and following the requirement for the implementation of the control algorithm the sampling frequency is specified using the start signal.

Timing Diagram of Closed Loop
The sampled digitized data of the feedback control parameters are further used for the control algorithm of motor drive system. The control algorithm consists of a speed control unit, current control unit and PWM generation unit. The control algorithm execution is required to be completed within a pre-specified sampling time interval. The crucial factors are sampling time as well as execution of control algorithm in a synchronized way to generate the PWM switching signals. The sampling time at least should be half the carrier time (minimum sampling frequency should be double of the carrier frequency) as represented in Figure 6a. In addition, the sampling frequency can be taken higher; however, the impact of lower sampling time for the same carrier frequency may not always be advantageous.
Electronics 2020, 9, x 8 of 19 interface and it generates the CS signal corresponding to the start signal condition. Once the acquisition following the sampling as well as conversion of the analog data is completed, it generates a done signal as shown in Figure 5. The AD converter works at 1MSPS and following the requirement for the implementation of the control algorithm the sampling frequency is specified using the start signal.

Timing Diagram of Closed Loop
The sampled digitized data of the feedback control parameters are further used for the control algorithm of motor drive system. The control algorithm consists of a speed control unit, current control unit and PWM generation unit. The control algorithm execution is required to be completed within a pre-specified sampling time interval. The crucial factors are sampling time as well as execution of control algorithm in a synchronized way to generate the PWM switching signals. The sampling time at least should be half the carrier time (minimum sampling frequency should be double of the carrier frequency) as represented in Figure 6a. In addition, the sampling frequency can be taken higher; however, the impact of lower sampling time for the same carrier frequency may not always be advantageous. The control algorithm is required to be executed in a sequential way as the output of the outer control loop generates the reference quantity and feeds to the inner control loop. The performance of the system is dependent on the controller bandwidth. The inner control loop has a dominant impact on the outer control loop; therefore, the bandwidth of the inner control loop should be higher to accommodate the bandwidth of the outer control loop. Furthermore, the execution timing can be crucial and may have significant impact on the system's performance. The enabled signals (done, sig.1-sig. n) are generated with on time Ten for the execution of control algorithm. A buffer delay time of Td is inserted for the successive enabled signals to avoid overlapping.

Time Synchronization
A time synchronization for the execution of entire control algorithm is crucial for the system performance. As the output of one unit is responsible for the next, a sequential time synchronization is used to perform the computation of the control algorithm within a sampling time. The control algorithm is required to be executed in a sequential way as the output of the outer control loop generates the reference quantity and feeds to the inner control loop. The performance of the system is dependent on the controller bandwidth. The inner control loop has a dominant impact on the outer control loop; therefore, the bandwidth of the inner control loop should be higher to accommodate the bandwidth of the outer control loop. Furthermore, the execution timing can be crucial and may have significant impact on the system's performance. The enabled signals (done, sig.1-sig. n) are generated with on time T en for the execution of control algorithm. A buffer delay time of T d is inserted for the successive enabled signals to avoid overlapping.

Time Synchronization
A time synchronization for the execution of entire control algorithm is crucial for the system performance. As the output of one unit is responsible for the next, a sequential time synchronization is used to perform the computation of the control algorithm within a sampling time.
The timing diagram in Figure 6b is used for the implementation of the control algorithm in the FPGA. The start signal width is defined by sampling time T s with on time of 1µs following the throughput time of ADC. Consequently, the done signal was switched to a high state following the quite time of 400 ns after the start signal switched to the low state. Following the done signal, the enabled signals are generated for the time-synchronized execution of the control algorithm.
There are various possibilities to generate the enabled signals to perform time-synchronization corresponding to the sampling time. In this study, enabled signals with on time T en of 0.5 µs and a buffer delay time T d of 2.5 µs in between consecutive signals are considered for the time-synchronization analysis of the control algorithm. The enabled signal (done) enables the speed controller loop as well as abc to dq conversion simultaneously to perform parallel computation as shown in the Figure 7. Further, a methodological approach is considered by using the different combination of enabled input signals for the computation of the current controller unit and dq to abc conversion. There are three cases considered for the analysis of the effect of the time synchronization, as shown in the Figure 8, for the computation of current controller unit and dq to abc conversion. The timing diagram in Figure 6b is used for the implementation of the control algorithm in the FPGA. The start signal width is defined by sampling time Ts with on time of 1µs following the throughput time of ADC. Consequently, the done signal was switched to a high state following the quite time of 400 ns after the start signal switched to the low state. Following the done signal, the enabled signals are generated for the time-synchronized execution of the control algorithm.
There are various possibilities to generate the enabled signals to perform time-synchronization corresponding to the sampling time. In this study, enabled signals with on time Ten of 0.5 µs and a buffer delay time Td of 2.5 µs in between consecutive signals are considered for the timesynchronization analysis of the control algorithm. The enabled signal (done) enables the speed controller loop as well as abc to dq conversion simultaneously to perform parallel computation as shown in the Figure 7. Further, a methodological approach is considered by using the different combination of enabled input signals for the computation of the current controller unit and dq to abc conversion. There are three cases considered for the analysis of the effect of the time synchronization, as shown in the Figure 8, for the computation of current controller unit and dq to abc conversion. Case I: In case I, the done signal enables the speed PI controller and abc-dq conversion. Further, the enable1 signal with Ten of 0.5 µs and Td of 2.5 µs from the done signal is used to enable the current PI control. Similarly, the enable 2 signal with Ten of 0.5 µs and Td of 5.5 µs from the enable1 signal is considered to enable the dq-abc conversion. The timing diagram executing case I is represented in Figure 8a. Case II: In this case, similar to case I, the done signal enables the speed PI controller and abc-dq conversion, and the enable1 signal with Ten of 0.5 µs and Td of 5.5 µs from done signal is used to enable the current PI controller. Further, the enable2 signal with Ten of 0.5 µs and Td of 5.5 µs from the enable1 signal enables the dq-abc transformations. The timing diagram for case II is shown in Figure 8b. Case III: Similar to case I and II the enable1 with Ten of 0.5 µs and Td of 8.5 µs is used as an enable signal for the current controller loop and the enable2 with Ten of 0.5 µs and Td of 5.5 µs enables the dq to abc transformation. The timing diagram corresponding to case III is shown in the Figure 8c. (a) Case I: In case I, the done signal enables the speed PI controller and abc-dq conversion. Further, the enable1 signal with T en of 0.5 µs and T d of 2.5 µs from the done signal is used to enable the current PI control. Similarly, the enable 2 signal with T en of 0.5 µs and T d of 5.5 µs from the enable1 signal is considered to enable the dq-abc conversion. The timing diagram executing case I is represented in Figure 8a.
Case II: In this case, similar to case I, the done signal enables the speed PI controller and abc-dq conversion, and the enable1 signal with T en of 0.5 µs and T d of 5.5 µs from done signal is used to enable the current PI controller. Further, the enable2 signal with T en of 0.5 µs and T d of 5.5 µs from the enable1 signal enables the dq-abc transformations. The timing diagram for case II is shown in Figure 8b.

Experimental Results and Discussion
An experimental system is developed as shown in Figure 9 for the analysis and validation of the time synchronization for the FPGA-based PMSM drive system. The three cases of time synchronization methodology as discussed in Section 3 are considered for feedback control loop analysis. Sampling frequencies of 25, 50 and 100 kHz are used for the extensive analysis of impacts due to time synchronization. The delay time for case II and case III is more than of 10 μs; therefore, only case I is considered corresponding to the sampling frequency of 100 kHz. A step change in speed reference and motor load condition (load disturbance) is introduced to demonstrate the system performance under transient conditions and examine the effect of time synchronization corresponding to different sampling frequencies. The system parameters and the component specifications are explained in the Tables 1 and 2. The sampling frequency of the speed controller is same as the current controller. Kp and Ki value for both the speed controller and the current controller are kept constant for all the cases as explained in the Table 3. However, considering the different sampling frequency, the sampling time Ts is multiplied with the Ki. The clock frequency considered for the FPGA-based system implementation is 100 MHz.

Experimental Results and Discussion
An experimental system is developed as shown in Figure 9 for the analysis and validation of the time synchronization for the FPGA-based PMSM drive system. The three cases of time synchronization methodology as discussed in Section 3 are considered for feedback control loop analysis. Sampling frequencies of 25, 50 and 100 kHz are used for the extensive analysis of impacts due to time synchronization. The delay time for case II and case III is more than of 10 µs; therefore, only case I is considered corresponding to the sampling frequency of 100 kHz. A step change in speed reference and motor load condition (load disturbance) is introduced to demonstrate the system performance under transient conditions and examine the effect of time synchronization corresponding to different sampling frequencies. The system parameters and the component specifications are explained in the Tables 1 and 2. The sampling frequency of the speed controller is same as the current controller. K p and K i value for both the speed controller and the current controller are kept constant for all the cases as explained in the Table 3. However, considering the different sampling frequency, the sampling time T s is multiplied with the K i . The clock frequency considered for the FPGA-based system implementation is 100 MHz.  FPGA board ARTY Z7-Xc7z020 Table 3. Controller parameters.   The no load speed response corresponding to the motor startup and stop is shown in the Figure  10. The speed reference is changed from 0 to 300 rpm (start-up) and 300 to 0 rpm (stop). The no load speed response corresponding to the motor startup and stop is shown in the Figure 10. The speed reference is changed from 0 to 300 rpm (start-up) and 300 to 0 rpm (stop). The no load speed response corresponding to the motor startup and stop is shown in the Figure  10. The speed reference is changed from 0 to 300 rpm (start-up) and 300 to 0 rpm (stop).

Change in Reference Speed
The motor system can go under the condition of speed change, and the transient performance of the motor drive system is of concern to attain the new speed smoothly with a lower settling time. A step change in the reference speed from 900 to 1500 rpm (low to high speed) and 1500 to 900 rpm (high to low speed) is considered to demonstrate and analyze the performance for time synchronization cases as well as sampling frequencies. The switching frequency of 5 kHz is used for the power devices of the inverter corresponding to different sampling time.

Change in Reference Speed
The motor system can go under the condition of speed change, and the transient performance of the motor drive system is of concern to attain the new speed smoothly with a lower settling time. A step change in the reference speed from 900 to 1500 rpm (low to high speed) and 1500 to 900 rpm (high to low speed) is considered to demonstrate and analyze the performance for time synchronization cases as well as sampling frequencies. The switching frequency of 5 kHz is used for the power devices of the inverter corresponding to different sampling time.
The speed regulation of PMSM in Figures 11-13 is demonstrated for the sampling frequency of 25, 50 and 100 kHz. The settling time performance of speed regulation is better for 25 and 50 kHz as compared to 100 kHz for the case I of time synchronization. Further, the speed regulation performance has improved in case II and case III for 50 kHz. The settling time performance of speed regulation is summarized in Table 4 in terms of time required to attain the steady state. The speed regulation of PMSM in Figures 11-13 is demonstrated for the sampling frequency of 25, 50 and 100 kHz. The settling time performance of speed regulation is better for 25 and 50 kHz as compared to 100 kHz for the case I of time synchronization. Further, the speed regulation performance has improved in case II and case III for 50 kHz. The settling time performance of speed regulation is summarized in Table 4 in terms of time required to attain the steady state.

Change in Load Condition
The motor system can go under the load disturbance condition as well, and the transient performance of motor drive system is of concern to attain the desired reference speed smoothly with a lower settling time. A step change in the electronic load to introduce a load disturbance is employed that ultimately results in a motor current change from 0.5 to 1 A (low to high) and 1 to 0.5 A (high to low). The switching frequency of 5 kHz is used to analyze the system behavior. The speed regulation of PMSM under load disturbance in Figures 14-16 is demonstrated for the sampling frequency of 25, 50 and 100 kHz. The settling time performance of 100 kHz sampling frequency is best for time synchronization in case I from low to high as well as high to low. Further, the speed regulation performance has improved in case II and case III for 50 kHz compared to 25 kHz and become almost same as performance of 100 kHz in case I. The settling time performance of speed under load disturbance is summarized in Table 5 considering the time required to attain the steady state.

Change in Load Condition
The motor system can go under the load disturbance condition as well, and the transient performance of motor drive system is of concern to attain the desired reference speed smoothly with a lower settling time. A step change in the electronic load to introduce a load disturbance is employed that ultimately results in a motor current change from 0.5 to 1 A (low to high) and 1 to 0.5 A (high to low). The switching frequency of 5 kHz is used to analyze the system behavior. The speed regulation of PMSM under load disturbance in Figures 14-16 is demonstrated for the sampling frequency of 25, 50 and 100 kHz. The settling time performance of 100 kHz sampling frequency is best for time synchronization in case I from low to high as well as high to low. Further, the speed regulation performance has improved in case II and case III for 50 kHz compared to 25 kHz and become almost same as performance of 100 kHz in case I. The settling time performance of speed under load disturbance is summarized in Table 5 considering the time required to attain the steady state.

Change in Load Condition
The motor system can go under the load disturbance condition as well, and the transient performance of motor drive system is of concern to attain the desired reference speed smoothly with a lower settling time. A step change in the electronic load to introduce a load disturbance is employed that ultimately results in a motor current change from 0.5 to 1 A (low to high) and 1 to 0.5 A (high to low). The switching frequency of 5 kHz is used to analyze the system behavior. The speed regulation of PMSM under load disturbance in Figures 14-16 is demonstrated for the sampling frequency of 25, 50 and 100 kHz. The settling time performance of 100 kHz sampling frequency is best for time synchronization in case I from low to high as well as high to low. Further, the speed regulation performance has improved in case II and case III for 50 kHz compared to 25 kHz and become almost same as performance of 100 kHz in case I. The settling time performance of speed under load disturbance is summarized in Table 5 considering the time required to attain the steady state.

Effect of Sampling Frequency on Speed Control Loop
The mechanical response of the motor is slower compared to that of the electrical response of the motor. Therefore, the sampling rate of the speed controller is slower than that of the current controller. The sampling rate of the encoder considered for the experimental validation is 1 kHz. Considering the sampling rate of the encoder the minimum sampling frequency that can be consider for the implementation of the speed control loop is 1 kHz.

Effect of Sampling Frequency on Speed Control Loop
The mechanical response of the motor is slower compared to that of the electrical response of the motor. Therefore, the sampling rate of the speed controller is slower than that of the current controller. The sampling rate of the encoder considered for the experimental validation is 1 kHz. Considering the sampling rate of the encoder the minimum sampling frequency that can be consider for the implementation of the speed control loop is 1 kHz.
The motor speed response corresponding to the speed controller sampling frequency 1 kHz for the change in the speed reference from 900 to 1500 rpm (low to high) and 1500 to 900 (high to low) is shown in the Figure 17. The motor speed response corresponding to change in the load disturbance that results in motor current change from 0.5 to 1 A is shown in Figure 18. In order to compare the effect of the sampling frequency on the speed controller the motor speed response with sampling frequency 1 kHz is compared to the 50 kHz sampling frequency. The current controller sampling frequency is considered as 50 kHz for both the cases. The motor speed response corresponding to the speed controller sampling frequency 1 kHz for the change in the speed reference from 900 to 1500 rpm (low to high) and 1500 to 900 (high to low) is shown in the Figure 17. The motor speed response corresponding to change in the load disturbance that results in motor current change from 0.5 to 1 A is shown in Figure 18. In order to compare the effect of the sampling frequency on the speed controller the motor speed response with sampling frequency 1 kHz is compared to the 50 kHz sampling frequency. The current controller sampling frequency is considered as 50 kHz for both the cases. The settling time required for the speed response to reach the steady state value is summarized in Table 6 for the change in the speed reference and in Table 7 for the change in the load torque disturbance corresponding to both speed sampling frequencies of 1 and 50 kHz. The transient response for the sampling frequency of 50 kHz is slightly better compared to the 1 kHz for both change in the speed reference and change in the load torque disturbance. Moreover, case III has a better response for the speed sampling frequencies of 1 and 50 kHz.

System Performance in Terms of THD
The controller performance (three-phase current harmonics) depends up on the switching frequency at which the power devices are operating as well as on the sampling frequency at which the digitized sampled data are coming. Therefore, different switching frequencies corresponding to the different sampling frequencies are considered to examine and analyze the controller performance. The sampling frequency for the system should be double or more than double the switching frequency and is considered as the fundamental criteria. The combinations of the switching frequency and sampling frequency are exercised to investigate the system performance as shown in the Table 8 considering case I of the time synchronization. The current ripples are presented in the form of percentage total harmonic distortion (%THD). The lower switching frequency performance in terms of %THD has improved drastically corresponding to an increase in sampling frequencies. Nevertheless, the higher switching frequency results in higher switching losses of the power devices and high sampling frequency demands the high-speed ADC to feedback the data samples at a higher rate. The advancement in digital technology with cost reduction trend can be vital in this aspect.

Conclusions
The PMSM drive system is presented considering the time synchronization analysis for FPGA-based real-time control implementation using a digital simulator XSG integrated with the MATLAB/Simulink (Math Works, Natick, MA, USA). The time synchronization of system control corresponding to sampling frequencies has a significant impact on motor performance under a transient operation. The controller demonstrates better performance under the change of speed reference for case II and Case III with a sampling frequency of 50 kHz. The controller performance under the change of load disturbance is better for case I with a sampling frequency of 100 kHz; however, Case III with sampling frequency of 50 kHz is comparable to it.
Furthermore, the effect of the sampling time on the speed controller and THD is also studied and investigated. The performance of the speed controller is slightly better for higher sampling frequency. Furthermore, the current ripple calculated in the form of %THD is lower corresponding to a higher sampling frequency. As the sampling frequency increases, the difference between the errors for consecutive samples reduces, and that ultimately reduces the current ripples. Therefore, a reduction in current ripple is achievable for an even lower switching frequency with a higher sampling frequency operation. The sampling frequency and the time synchronization both have an impact on motor performance. An appropriate synchronization methodology and sampling time can achieve better performance in terms of transient response under change in reference speed and motor load. Funding: This research received no external funding.

Conflicts of Interest:
The authors declare no conflict of interest.