Direct Space Vector Modulation with Novel DC-Link Voltage Balancing Algorithm for Easy Software Implementation of Three-Phase Three-Level Converter

: The present paper proposes a direct space vector modulation and novel balance algorithm for easy software application of three-level converters which operate in three-phase. In the case of the conventional space vector modulation, to get the on-state times of the switches, the dwell times of the three nearest stationary vectors, which are obtained after sector and region selection algorithms, should be rearranged. These processes, therefore, contain diverse conditional statements and complicated calculations such as inverse trigonometric functions and square roots. However, the burden of the software application of the proposed algorithm is greatly reduced by not using the sector selection algorithm, the region selection algorithm, and the on-state time allocation process as the proposed modulation can directly control the switch on-state time. In a three-level topology, it is required to balance top and bottom capacitor voltages because the DC-link voltage is composed of two capacitor voltages; the unbalanced voltage of each DC-link capacitor causes the overvoltage of the switching devices. Thus, the DC-link voltage balancing algorithm is proposed, and it is also very simple and effective without additional circuits because it controls the switch on-state time directly as well. The 5-kW prototype proved the validity of the proposed algorithm with its feasibility.


Introduction
For three-phase control, space vector modulation (SVM) control is commonly used [1,2]. The SVM is useful because, at the same carrier frequency, the switching number is about 30% less and the maximum possible output voltage is 15.5% higher than the sinusoidal pulse width modulation method [3]. The current controller in the d-q frame gives the angle of desired vector and magnitude to SVM algorithm; the d-q frame is often used to regulate the reactive power and active power [4,5]. However, in this procedure, the SVM demands complex calculations such as the inverse trigonometric functions and the square root of the microprocessor [6]. Moreover, a three-level converter requires much more complex selection algorithms than a two-level converter to control through the SVM; a three-level converter has at least six sectors, each of which is separated into a chain of regions [7,8]. Furthermore, at the end of the selection algorithm, the dwell time of the vectors should be properly distributed to the switch on-state time [9].
Under the same input/output state with the same filter size, three-level converters have better power conversion efficiency, rated voltage conditions, and current total harmonic distortion (THD) compared to two-level converters [10]. However, three-level converters require two DC-link capacitors linked in series to produce different voltage levels, unlike conventional two-level converters. Therefore, the DC-link voltage could be unbalanced, which causes overvoltage of the switching device and high THD of the grid current, so the two DC-link voltages should be controlled to be the same [11,12]. While additional circuits may solve this balancing problem, this solution increases power loss, cost, and complexity of the circuit [13][14][15].
In this study, the proposed algorithm and DC-link voltage balancing algorithm were validated through the T-type topology which represents the three-level converter. The proposed direct space vector modulation (DSVM) controls the switch on-state time directly without complicated calculations such as sector and region selection algorithms and on-state time allocation procedure on the software. In addition, the balancing algorithm that uses DSVM not only reduces the load of the software, but also eliminates the need for additional circuit configuration; its principle includes the direction of neutral current and its magnitude. The DC-link voltage comes into a balanced state by controlling the neutral-point-current, so the concerns about overvoltage on switching devices are reduced. The final switch on-state time is the sum of the compensated on-state time and on-state time, which is calculated from DSVM. This paper carries out the analysis of the conventional SVM and the theoretical analysis of the proposed DSVM and DC-link voltage balancing algorithms. Then, the experimental results of the 5-kW T-type topology prototype are provided to verify the validity of the proposed algorithm with its feasibility.

Algorithm Analysis
As shown in Figure 1, the grid voltages are e a , e b , and e c ; the grid currents are i a , i b , and i c ; and the branch voltages are v an , v bn , and v cn . In the stationary, a-b-c frame, the voltage equations are as follows: where E and ω are the grid voltage amplitude and the angular frequency of the grid voltage. L a , L b , and L c , which are filter inductors, have the same value of inductance L. The voltage equations in (1) are transformed from a-b-c frame to d-q frame as where d-axis grid voltage and current are e d and i d ; q-axis grid voltage and current are e q and i q ; d-axis branch voltages is v d ; and q-axis branch voltages is v q . By using (2), the active power P which is supplied to the grid is i q cannot affect the active power P of (3) because e q is 0 in (2). Therefore, the q-axis reference grid current i * q should be 0 for the zero reactive power and unity power factor. For linear control, the following equations should be satisfied: where the variation of d-axis branch voltage is ∆v d and the variation of q-axis branch voltage is ∆v q . They can be controlled as where the proportional control gains of ∆v d is k pd ; the proportional control gains of ∆v q is k pq ; the integral control gains of ∆v d is k id ; and the integral control gains of ∆v q is k iq . Since the current controller provides the branch voltages as (4), Equation (2) is easy to control as below: This directly controls the grid current and could improve the power quality with simple control.

The Conventional SVM Algorithm
The conventional SVM is a switching modulation technique for the three-phase current control of converters. In this modulation, the branch voltages of (4) are considered as the desired voltage. A three-level cell has three switching states, as presented in Table 1, because S x2 and S x4 (x = a, b, c) operate in complementary relations similar to S x1 and S x3 . Thus, the three-level converter which operates in three-phase has 27 (= 3 × 3 × 3) switching states because of the three legs configuration. In a complex plane, v an , v bn , and v cn , which are three branch voltages, can be represented as a single variable by utilizing the space vector transformation. The space vector u(t) in complex plane can be expressed as where a scaling factor is 2 3 . Any three of time functions which fulfill u a (t) + u b (t) + u c (t) = 0 could be expressed in two-dimensional space. Thus, 27 space vectors with 19 values of vectors ( V 0 ∼ V 18 ) could be drawn in complex planes, as shown in Figure 2a, and the 27 space vectors are classified into four groups: small, medium, large, and zero. In addition, in accordance with Figure 2b, the vector space can be six triangular sectors (I-VI); each triangular sector can be further divided into four triangular regions (1)(2)(3)(4). The reference space vector V re f of Figure 2b is provided from (4), and this reference space vector V re f can be redefined by the three nearest stationary vectors. For example, if V re f is in Region 4 of SECTOR I as in Figure 2b, V 2 , V 7 , and V 14 are the three nearest stationary vectors: where, in this case, the dwell times of V 2 , V 7 , and V 14 are T nv1 , T nv2 , and T nv3 , respectively. The switching period is T s . In addition, the three nearest stationary vectors V 2 , V 7 , and V 14 are represented as where After putting (10) into (8), the equation could be split into the real part and the imaginary part. Then, by utilizing (9), the dwell times are obtained as where the modulation index is m a , which is defined as The above processes could be repeated for each region. Consequently, Table 2 is the calculation results of the space vector dwell times for the V re f in SECTOR I. For the other sectors (II-VI) of dwell times for V re f , the results of Table 2 can be utilized; if the integer multiple of π/3 is taken from the actual angular displacement θ, the calculation results are available because the changed angle is in between 0 and π/3. Table 2. Space vector dwell times about V re f in SECTOR I.

Region
T nv1 /T s T nv2 /T s T nv3 /T s

The Proposed DSVM Algorithm
Because S x2 and S x4 operate in complementary relations, as indicated in Section 2.1, the S x4 on-state time can be represented as T s − T sx2 where T sx2 is the on-state time of S x2 and T sx4 is the on-state time of S x4 (x = a, b, c). Thus, v aO , v bO , and v cO , which are the terminal voltages, are represented as In addition, they can be represented as From (15), v nO is given as Therefore, from (14), (15), and (17), v an , v bn , and v cn are arranged as In matrix form, (18) is arranged as As shown in Figure 2b, if V re f is in Region 4, which is in SECTOR I, the three nearest vectors are V 2 , V 7 , and V 14 . In addition, because small vectors have P-and N-type, ( V 2P , V 7 , and V 14 ), ( V 2N , V 7 , and V 14 ), or ( V 2P , V 2N , V 7 , and V 14 ) can be utilized for V re f . If V re f is computed by a P-type space vector V 2P (PPO) with V 7 (PON) and V 14 (PPN), the switch on-state time and the space vector dwell time are represented as Because of T sa1 = T sa2 = T s , v aO is V dc /2 from (9), (14), and (20). Therefore, from (14), T sa1 + T sa2 , T sb1 + T sb2 , T sc1 + T sc2 are obtained as where v max (=max(v an , v bn , v cn )) is the maximum branch voltage; the branch voltage can be maximized by the maximum value of T sx1 + T sx2 (x = a, b, c) because of (19). Thus, because of T sa1 = T sa2 = T s from (9) and (20), v an is v max .
If V re f is computed by the N-type space vector V 2N (OON) with V 7 (PON) and V 14 (PPN) instead of V 2P (PPO), the switch on-state times and the space vector dwell time is obtained as Because of T sc1 = T sc2 = 0, −V dc /2 is v cO from (14) and (25). Therefore, after the same process as the above procedures of (21)-(24), T sa1 + T sa2 , T sb1 + T sb2 , and T sc1 + T sc2 are represented as where v min (=min(v an , v bn , v cn )) is the minimum branch voltage. For the minimum deviation of the DC-link voltages, the P-type state and the N-type state in the dwell time of V 2 should be equal during T s ideally. Therefore, from (20) and (25), if V 2P and V 2N are utilized equally during T s , the space vector dwell time and the switch on-state time are obtained as T sa1 +T sa2 , T sb1 +T sb2 , and T sc1 +T sc2 , from (24) and (27), are represented as The switch on-state times are calculated as represented in Table 3 thanks to the switching characteristics of three-level in [16]. Therefore, the proposed DSVM directly provides the switch on-state times from (29) without complicated computations, i.e. square root, inverse trigonometric function, sector and region selection algorithms, and on-time allocation process. As shown in Figure 3, DSVM takes the switch on-state time more easily through the greatly simplified procedures than the conventional SVM; DSVM needs just one generalized equations, whereas many conditional statements should be included in each block diagram of the conventional SVM in Figure 3. In accordance with Table 4, there are huge differences in complexity of switching sequences for DSVM compared to other methods. Even if, in [11], the number of switching sequence is zero, each sectors has the different equations for the switch on-state time. However, in DSVM, only one generalized equation covers all sectors, and the proposed DSVM can calculate the switch on-state time without considering of the switching sequence, sectors, and regions.

Condition
On-State Times (x = a, b, c)

The Proposed Balancing Algorithm of the DC-Link Voltage
A seven-segment switching sequence is used for the three-level converter which operates in three-phase after DSVM. Its characteristics could be summarized as follows: A) T s is composed of seven segments of the dwell times for the three stationary space vectors which are the nearest to the reference. B) The three space vectors have four switching states since the P-type state and the N-type state in the dwell time of small vectors should be equal during T s for the minimum deviation of the DC-link voltages. C) The change to the another segment is only one leg switching state. The change in Figure 4, for example, from the (PPN) to the (PPO) is conducted by altering the c-terminal side leg switching state from (N) to (O). D) For the grid current THD, the segment sequences are center-aligned and symmetric. E) The center segment, which is the P-type vector switching state, and the edge segments" which are the N-type vector switching state, have the same dwell time.
The switching state sequence based on A)-E) for V re f is shown in Figure 4. As referred to C) and E), the movement from the edge to the center make the switching states of all three legs change. Therefore, In Table 3 and Figure 4, if S x1 (or S x2 ) is 1 or 0 continuously during T s , the other switch S x2 (or S x1 ) is one of T max , T mid , and T min ; T max is the five centered segments period; T mid is the three centered segments period; and T min is the centered segment period. Thus, by utilizing E), (30) Figure 4. The switching state sequences of V re f , where 1 is the switch on-state and 0 is the switch off-state.
As shown in Figure 5, the five states of the space vectors are (PPP) of a zero vector, (POO) and (ONN) of two small vectors, (PON) of a medium vector, and (PNN) of a large vector. Although Figure 5 represents only the state of (PPP), the converter operates in zero vector V 0 with (PPP), (NNN), and (OOO). In the state of (PPP), as shown in Figure 5a, the a, b, and c terminals are linked to the positive node of the DC-source because the all of S x1 and S x2 in three legs are turned on (x = a, b, c). Thus, the voltage difference between the top capacitor and the bottom capacitor maintains constant since the capacitors are linked only to the DC-source. The same is true for (OOO) and (NNN). Figure 5b shows the circuit diagram of small vector V 1P (POO); the top capacitor voltage V dct is decreased since the neutral current i O flows in the negative direction. On the other hand, as shown in Figure 5c  It can be assumed that the grid current is constant during T s because the switching frequency is far higher than the grid frequency. Therefore By using Figure 4, T max , T mid , and T min can be obtained as Thus, by utilizing (32) and (33), where i O,3s =0 because i O is zero in Figure 5e. Thus, the compensated dwell time T comp for the balancing control can be expressed as where the proportional gain is k(> 0) and the compensation value is α. If T comp compensates T max , T mid , and T min equally, (31) is reorganized as below To eliminate i O term, α can be expressed as: Thus, from (35)-(37), the compensated neutral current i O,comp is expressed as: where 2i O,4s k/T s is k (< 0) and i O,4s < 0 since the centered segment is the P-type small vector switching state from E). If, in DC-link unbalanced condition, V dcb is lower than T max,comp = T max + T comp .

Experimental Result
To demonstrate the validity of DSVM and its feasibility, grid-connected experiments were conducted using the prototype for the proposed converter in Figure 1. The parts and component values of the prototype, as shown in Figure 1, are as follows: a-, b-, and c-phase T-type module, 4MBI300VG-120R-50; current sensor, LA 55-P; capacitance of C t and C b , 2200 µF; and inductance of L a , L b , and L c , 1 mH. The DC-link voltage V dc is 360 V; the line voltage v a b is 220 V rms ; the grid frequency f g is 60 Hz; and the rated power P o is 5 kW. Figure 6 shows the experimental results of T-type converter which operates in three-phase and utilizes the proposed control algorithms. i a , i b , and i c , which are the grid currents in Figure 6a, show sinusoidal wave form with the phase difference of 120 • . In addition, they provides the desired rated power of 5 kW. Each of the grid currents is controlled very well as the sinusoidal form in Figure 6a. Furthermore, to check the response time in transient condition, load variation was conducted (Figure 6b). In this experiment, the grid currents i a , i b and i c were changed smoothly and quickly from 5 to 2.5 kW. As a result, those experiments completely demonstrated the validity of the proposed control algorithm and its feasibility. As represented in Figure 6c, the three-level voltage v ab has five voltage levels, and the line voltage v a b is the 220 V rms sine wave. To verify the proposed DC-link voltage balancing algorithm, the initial unbalancing experiment was conducted, as presented in Figure 6d, which shows the voltage of the top capacitor V dct and the voltage of the bottom capacitor V dcb . The V dct initial condition is 240 V and the V dcb initial condition is 120 V. To make the initial unbalanced DC-link state, the register linked to the circuit breaker, as shown in Figure 7b, is temporarily utilized before the operation. As shown in Figure 6d, after starting the operation of the converter, which conducts the proposed algorithm, the difference between V dct and V dcb has become zero. It proves that the proposed balancing algorithm gives equal distribution of two DC-link capacitor voltages. Thus, the proposed DSVM and the balancing algorithm for the three-level converter which operates in three-phase permit giving precise current control and the DC-link capacitor voltages balancing.
Pictures of experiment environment are shown in Figure 7. The prototype is evenly arranged, as represented in Figure 7a, and a plate also acts as the heatsink and support at the same time. In addition, the power circuit and control board are insulated. As shown in Figure 7b, DC power supply gives the power for the prototype, and the prototype transfers the power to the three-phase grid. To create an initial DC-link unbalance condition, the register linked to the circuit breaker in Figure 7b is utilized temporarily before the converter operation, as shown in Figure 6d.

Conclusions
This paper proposes a direct space vector modulation and a novel DC-link voltage balance algorithm for easy software application of three-level converters which operate in three-phase. The proposed DSVM directly gives the switch on-state time without complicated computations, which are the on-state time allocation process and sector and region selection algorithms. Due to DSVM, a novel DC-link voltage balancing algorithm is also developed. The three-level converters have two divided DC-link capacitors which are linked in series. Then, it can generate the unbalanced voltages of the DC-link capacitors which is causing raised concerns about overvoltage on switching devices. In addition, the equal voltages of the DC-link capacitors linked in series can improve the current quality of the three-level converters. The proposed balancing algorithm with DSVM simply controls the DC-link voltages in equality by adjusting the neutral current and provides an effective balance control without the additional hardware and complex calculations. Therefore, the proposed DSVM and the balancing algorithm are simple to apply to three-level converters which operate in three-phase, and the experimental results thoroughly represent the validity, effectiveness, and feasibility of the proposed algorithms.