Nonuniformity-Immune Read-In Integrated Circuit for Infrared Sensor Testing Systems

: In this study, a novel IR projector driver that can minimize nonuniformity in electric circuits, using a dual-current-programming structure, is proposed to generate high-quality infrared (IR) scenes for accurate sensor evaluation. Unlike the conventional current-mode structure, the proposed system reduces pixel-to-pixel nonuniformity by assigning two roles (data sampling and current driving) to a single transistor. A prototype of the proposed circuit was designed and fabricated using the SK-Hynix 0.18 µ m CMOS process, and its performance was analyzed using post-layout simulation data. It was veriﬁed that nonuniformity, which is deﬁned as the standard deviation divided by the mean radiance, could be reduced from 21% to less than 0.1%.


Introduction
An infrared scene projector (IRSP) is a widely used piece of equipment that projects infrared (IR) images to investigate the performance of IR sensors [1][2][3][4][5][6][7]. These projectors are composed of IR emitters and driver integrated circuits (ICs) that are called read-in integrated circuits (RIICs) and are responsible for driving current to the IR emitters. High-quality IR scenes are required for accurately evaluating the performance of IR sensors; therefore, the IRSPs needs to be able to correct the nonuniformity between individual pixels of an IR emitter and an RIIC.
Currently, the look-up table (LUT) method is used to reduce the nonuniformity at each pixel [8][9][10][11][12][13][14]; however, as the radiance range of the overall pixels must be standardized to alower value to achieve uniform radiation, the performance of this method is hindered for a wide radiance range of IRSPs. Therefore, to obtain high-quality IR images for wide radiance ranges, a nonuniformity reduction in emitters and ICs is required in addition to external correction.
To improve circuit uniformities, several RIICs that adopt current-programming methods have been suggested [15,16]. However, to ensure the simultaneous IR emission of pixels [9,10], two transistors are separately needed for data sampling and current driving, hindering precise RIIC nonuniformity reduction.
In this paper, a novel RIIC design that enables precise nonuniformity compensation by adopting a dual-current-programming structure is proposed. In particular, with a mode-switching mechanism, a transistor can perform both data sampling and current driving, improving the uniformity of all pixels. Section 2 describes the implementation and analysis of the proposed nonuniformity-immune RIIC and its behavior is analyzed based on post-layout simulations presented in Section 3. Finally, conclusions are drawn in Section 4.
where T emitter and T sub are the temperatures of the emitter and substrate, respectively; T app is the apparent temperature considering the emissivity, ε, and fill factor, ff, of the IR emitter; G and R are the thermal conductance and resistance of the emitter, respectively. η(T) represents Planck's equation; λ 1 and λ 2 are the wavelengths of interest; h, k and c are the Planck and Boltazman constants and the speed of light. As indicated in Equation (1), T emitter , used to determine pixel radiance in Equation (3), is proportional to the square of I emitter . As a result, the control of the current by RIIC is critical to reduce the radiance gap between pixels. In this study, R, G, ε, and ff were assumed equal to the ideal design parameters. Figure 1a shows a block diagram of the RIIC. Every unit pixel of the IR display panel contains an IR emitter, represented as a resistor in Figure 1b. Conventional RIIC pixels contain two capacitors and a unity-gain buffer (B 1 ), responsible for a synchronized IR emission (snapshot operation), resulting in high-speed scene generation without defects [17][18][19][20][21]. However, as the RIIC layout area is limited by the pitch of the emitter, the small-sized B 1 , shown in Figure 1b, is vulnerable to gain and offset errors that induce the nonuniformity of each pixel.

Nonuniformity Influences of the Conventional RIIC
The relationship between the current of the emitter, driven by the RIIC (Iemitter), and its final radiance (Γ) can be calculated using Equations (1) and (2) [17]: where Temitter and Tsub are the temperatures of the emitter and substrate, respectively; Tapp is the apparent temperature considering the emissivity, ɛ, and fill factor, ff, of the IR emitter; G and R are the thermal conductance and resistance of the emitter, respectively. ( ) represents Planck's equation; and are the wavelengths of interest; h, k and c are the Planck and Boltazman constants and the speed of light.
As indicated in Equation (1), Temitter, used to determine pixel radiance in Equation (3), is proportional to the square of Iemitter. As a result, the control of the current by RIIC is critical to reduce the radiance gap between pixels. In this study, R, G, ɛ, and ff were assumed equal to the ideal design parameters. Figure 1a shows a block diagram of the RIIC. Every unit pixel of the IR display panel contains an IR emitter, represented as a resistor in Figure 1b. Conventional RIIC pixels contain two capacitors and a unity-gain buffer (B1), responsible for a synchronized IR emission (snapshot operation), resulting in high-speed scene generation without defects [17][18][19][20][21]. However, as the RIIC layout area is limited by the pitch of the emitter, the small-sized B1, shown in Figure 1b, is vulnerable to gain and offset errors that induce the nonuniformity of each pixel. For example, in Figure 2a, the dotted line A1 represents a nonideal transfer curve affected by a gain and offset voltage (Vos) of the buffer. According to this curve, the voltage VG1, applied to the gate node (VG), is lower than that generated in an ideal situation, VG0, at the same data voltage VDATA0. This difference also affects the apparent temperature, as indicated by T0 and T1 in Figure 2b, resulting in pixel-to-pixel nonuniformity.
The relationship between Iemitter and VG can be represented using the following equation: For example, in Figure 2a, the dotted line A 1 represents a nonideal transfer curve affected by a gain and offset voltage (V os ) of the buffer. According to this curve, the voltage V G1 , applied to the gate node (V G ), is lower than that generated in an ideal situation, V G0 , at the same data voltage V DATA0 . This difference also affects the apparent temperature, as indicated by T 0 and T 1 in Figure 2b, resulting in pixel-to-pixel nonuniformity. threshold voltage Vth, result in the nonuniformity of Iemitter. As a result, even if the gate voltage is an ideal value VG0, the apparent temperature can be a nonideal value T0*, as indicated in J1 in Figure 2b. The x-axis intercept P1 and the slope of J1 are affected by the difference in Vth and K′n, respectively. Therefore, a novel circuit design that avoids buffer errors and current-driving transistor mismatch is desired.

Proposed Nonuniformity-Immune RIIC
The proposed circuit comprises two current-driving transistors (Md1 and Md2), two capacitors (Cm1 and Cm2), and six switches (S1-S6), as shown in Figure 3a. The IR emitter is represented as a resistor in Figure 3a. Furthermore, Idata represents the current-type scene data, which can be designed using a current-output digital-to-analog converter or a current-output source-driver [15,16]. Meanwhile, the pixel circuit comprises a dual-current-programming structure. The first is composed of Md1, Cm1, S1, S3, and S5, while the other is formed by Md2, Cm2, S2, S4, and S6. In the timing diagram, Figure 3b, two operating phases, whose period is one frame time, continuously repeat. The relationship between I emitter and V G can be represented using the following equation: As shown in Equation (4), transistor mismatch parameters, the constant K n (K n = µ n ·C ox ) and the threshold voltage V th , result in the nonuniformity of I emitter . As a result, even if the gate voltage is an ideal value V G0 , the apparent temperature can be a nonideal value T 0* , as indicated in J 1 in Figure 2b. The x-axis intercept P 1 and the slope of J 1 are affected by the difference in V th and K n , respectively. Therefore, a novel circuit design that avoids buffer errors and current-driving transistor mismatch is desired.

Proposed Nonuniformity-Immune RIIC
The proposed circuit comprises two current-driving transistors (M d1 and M d2 ), two capacitors (C m1 and C m2 ), and six switches (S1-S6), as shown in Figure 3a. The IR emitter is represented as a resistor in Figure 3a. Furthermore, I data represents the current-type scene data, which can be designed using a current-output digital-to-analog converter or a current-output source-driver [15,16]. Meanwhile, the pixel circuit comprises a dual-current-programming structure. The first is composed of M d1 , C m1 , S1, S3, and S5, while the other is formed by M d2 , C m2 , S2, S4, and S6. In the timing diagram, Figure 3b, two operating phases, whose period is one frame time, continuously repeat.
In phase I, the I data passes through S1, S3, and M d1 . As a result, the gate-source voltage of M d1 (V gs1 ) is sampled in C m1 and can be calculated using the following equation: Unlike voltage-programmed pixels, the V gs of the current-programmed pixel contains the mismatch parameters of M d1 . In phase II, the S5 switch turns on, enabling M d1 to drive the current (I emitter ) to the emitter. In this stage, I emitter can be calculated using the following equation: It should be noted that the mismatch parameters of M d1 are canceled when V gs from Equation (6) is substituted into Equation (5). As a result, when neglecting the channel-length modulation effect, the circuit can drive the emitter current regardless of the current-driving transistor mismatch. It should be noted that the Equations (4)- (6) are based on the operation in the saturation region; M d1 and M d2 need to operate in the saturation region. Thus, when designing the unit RIIC cell, the resistance of the IR emitter and the amount of current driven to the emitter needs to be considered for guaranteeing the drain-to-source voltages (V ds ) of M d1 and M d2 .
The proposed circuit comprises two current-driving transistors (Md1 and Md2), two capacitors (Cm1 and Cm2), and six switches (S1-S6), as shown in Figure 3a. The IR emitter is represented as a resistor in Figure 3a. Furthermore, Idata represents the current-type scene data, which can be designed using a current-output digital-to-analog converter or a current-output source-driver [15,16]. Meanwhile, the pixel circuit comprises a dual-current-programming structure. The first is composed of Md1, Cm1, S1, S3, and S5, while the other is formed by Md2, Cm2, S2, S4, and S6. In the timing diagram, Figure 3b, two operating phases, whose period is one frame time, continuously repeat. In phase I, the Idata passes through S1, S3, and Md1. As a result, the gate-source voltage of Md1 (Vgs1) is sampled in Cm1 and can be calculated using the following equation: Unlike voltage-programmed pixels, the Vgs of the current-programmed pixel contains the mismatch parameters of Md1. In phase II, the S5 switch turns on, enabling Md1 to drive the current (Iemitter) to the emitter. In this stage, Iemitter can be calculated using the following equation: It should be noted that the mismatch parameters of Md1 are canceled when Vgs from Equation (6) is substituted into Equation (5). As a result, when neglecting the channel-length modulation effect, the circuit can drive the emitter current regardless of the current-driving transistor mismatch. It should be noted that the Equations (4)- (6) are based on the operation in the saturation region; Md1 and Md2 need to operate in the saturation region. Thus, when designing the unit RIIC cell, the resistance of the IR emitter and the amount of current driven to the emitter needs to be considered for guaranteeing the drain-to-source voltages (Vds) of Md1 and Md2. Md2 samples the data voltage in phase II and drives the current to the subsequent phase I. As a result, Md1 and Md2 can operate in sampling or driving modes, enabling a snapshot operation without a unity-gain buffer B1 and precise mismatch compensation. For example, in phase I, Md1 is in the sampling mode and Md2 is in the driving mode. Figure 4 shows the circuit diagram between the A1 and B nodes in Figure 3a. In the sampling mode, when S3 is turned on, the drain-source voltage of Md1 (Vds1) is identical to the gate-source M d2 samples the data voltage in phase II and drives the current to the subsequent phase I. As a result, M d1 and M d2 can operate in sampling or driving modes, enabling a snapshot operation without a unity-gain buffer B 1 and precise mismatch compensation. For example, in phase I, M d1 is in the sampling mode and M d2 is in the driving mode. Figure 4 shows the circuit diagram between the A 1 and B nodes in Figure 3a. In the sampling mode, when S3 is turned on, the drain-source voltage of M d1 (V ds1 ) is identical to the gate-source voltage of M d1 (V gs1 ). However, in the driving mode, the V ds1 changes according to V dd − I emitter ·R, generating an unexpected charge (∆Q) at the gate node (V G1 ). This generated error voltage (V error,gs1 ) can be estimated using Equation (7), derived from the charge conversion law [22]: The error voltage also results in a current error, which can prevent accurate IR scene generation. Furthermore, the cascode structure, which is commonly used to neglect the effect of ∆V ds , cannot be used in the pixel as it prevents the dual functionality of M d1 and M d2 . To avoid the existence of ∆Q, a unity-gain buffer (B p1 ) is inserted, as shown in Figure 4b. In particular, B p1 is placed in a feedback loop during the sampling mode, preventing the pixel-to-pixel nonuniformity due to buffer errors.   Figure 5 shows the mask layout of the proposed RIIC pixel with two buffers (Bp1, Bp2) in a 56 µm pitch. The W/L parameters of Md1 and Md2 are both 10/10. Two pads are located in each pixel to establish a connection with the IR emitter device. Considering the symmetry of the layout, C1 is divided into two subcomponents (C1a and C2b) whose sizes are 150 fF and 600 fF, as shown in Figure  5. C2 is analogously divided into C2a and C2b.

Data Sampling Accuracy
To verify the feasibility of the proposed circuit, a prototype RIIC was designed via an SK-Hynix 0.18 µm CMOS process and apost-layout simulation on Cadence software (Cadence Design Systems, Inc., San Jose, CA, USA) was performed. The data current (Idata) varied from 0.1 to 200 µA, and the measured gate-source voltage of Md1 varied as plotted in Figure 6. To verify the operating speed, the Idata varied by one frame time 1/100 Hz = 10 ms, and the pixel-selecting time (Tsel) shown in Figure 3b was set to 1/(100 × 64 × 64) = 2.4 µs.
From the simulation results, the gate voltage error (Verror,gs1 = 2.5 mV) disappeared by using the Bp1, as indicated by the solid line in Figure 6b. Therefore, the unity-gain buffer helps maintain the sampled voltage regardless of the operational phase of the circuit.  Figure 5 shows the mask layout of the proposed RIIC pixel with two buffers (B p1 , B p2 ) in a 56 µm pitch. The W/L parameters of M d1 and M d2 are both 10/10. Two pads are located in each pixel to establish a connection with the IR emitter device. Considering the symmetry of the layout, C 1 is divided into two subcomponents (C 1a and C 2b ) whose sizes are 150 fF and 600 fF, as shown in Figure 5. C 2 is analogously divided into C 2a and C 2b .   Figure 5 shows the mask layout of the proposed RIIC pixel with two buffers (Bp1, Bp2) in a 56 µm pitch. The W/L parameters of Md1 and Md2 are both 10/10. Two pads are located in each pixel to establish a connection with the IR emitter device. Considering the symmetry of the layout, C1 is divided into two subcomponents (C1a and C2b) whose sizes are 150 fF and 600 fF, as shown in Figure  5. C2 is analogously divided into C2a and C2b.

Data Sampling Accuracy
To verify the feasibility of the proposed circuit, a prototype RIIC was designed via an SK-Hynix 0.18 µm CMOS process and apost-layout simulation on Cadence software (Cadence Design Systems, Inc., San Jose, CA, USA) was performed. The data current (Idata) varied from 0.1 to 200 µA, and the measured gate-source voltage of Md1 varied as plotted in Figure 6. To verify the operating speed, the Idata varied by one frame time 1/100 Hz = 10 ms, and the pixel-selecting time (Tsel) shown in Figure 3b was set to 1/(100 × 64 × 64) = 2.4 µs.
From the simulation results, the gate voltage error (Verror,gs1 = 2.5 mV) disappeared by using the Bp1, as indicated by the solid line in Figure 6b. Therefore, the unity-gain buffer helps maintain the sampled voltage regardless of the operational phase of the circuit.

Data Sampling Accuracy
To verify the feasibility of the proposed circuit, a prototype RIIC was designed via an SK-Hynix 0.18 µm CMOS process and apost-layout simulation on Cadence software (Cadence Design Systems, Inc., San Jose, CA, USA) was performed. The data current (I data ) varied from 0.1 to 200 µA, and the measured gate-source voltage of M d1 varied as plotted in Figure 6. To verify the operating speed, the I data varied by one frame time 1/100 Hz = 10 ms, and the pixel-selecting time (T sel ) shown in Figure 3b was set to 1/(100 × 64 × 64) = 2.4 µs.
From the simulation results, the gate voltage error (V error,gs1 = 2.5 mV) disappeared by using the B p1 , as indicated by the solid line in Figure 6b. Therefore, the unity-gain buffer helps maintain the sampled voltage regardless of the operational phase of the circuit.

Evaluation of Nonuniformity
To evaluate the improvement in pixel-to-pixel uniformity, deviations in some quantities were purposefully inserted during the post-layout simulations. The offset voltage and gain error of B1, which were estimated based on the mismatch parameters of the CMOS process, were set to 16 mV and 2%, respectively. The standard deviation ( ) of the threshold voltage was set to 3 mV following the data sheet of the CMOS process. Furthermore, the widths and lengths of Md, Md1 and Md2 were identical. Moreover, the maximum current of the conventional RIIC was defined, according to the proposed RIIC, as 200 µA. This value is sufficient for the circuit to achieve the target temperature range listed in Table 1. Figure 7a,b shows the acquired emitter current data driven by the conventional RIIC and proposed RIIC, respectively. Using the current data acquired from the simulation, the apparent temperature was calculated using Equations (1) and (2): the desired properties of the IR emitter used in this calculation are listed in Table 2.

Evaluation of Nonuniformity
To evaluate the improvement in pixel-to-pixel uniformity, deviations in some quantities were purposefully inserted during the post-layout simulations. The offset voltage and gain error of B 1 , which were estimated based on the mismatch parameters of the CMOS process, were set to 16 mV and 2%, respectively. The standard deviation (σ) of the threshold voltage was set to 3 mV following the data sheet of the CMOS process. Furthermore, the widths and lengths of M d , M d1 and M d2 were identical. Moreover, the maximum current of the conventional RIIC was defined, according to the proposed RIIC, as 200 µA. This value is sufficient for the circuit to achieve the target temperature range listed in Table 1. Figure 7a,b shows the acquired emitter current data driven by the conventional RIIC and proposed RIIC, respectively.

Evaluation of Nonuniformity
To evaluate the improvement in pixel-to-pixel uniformity, deviations in some quantities were purposefully inserted during the post-layout simulations. The offset voltage and gain error of B1, which were estimated based on the mismatch parameters of the CMOS process, were set to 16 mV and 2%, respectively. The standard deviation ( ) of the threshold voltage was set to 3 mV following the data sheet of the CMOS process. Furthermore, the widths and lengths of Md, Md1 and Md2 were identical. Moreover, the maximum current of the conventional RIIC was defined, according to the proposed RIIC, as 200 µA. This value is sufficient for the circuit to achieve the target temperature range listed in Table 1. Figure 7a,b shows the acquired emitter current data driven by the conventional RIIC and proposed RIIC, respectively. Using the current data acquired from the simulation, the apparent temperature was calculated using Equations (1) and (2): the desired properties of the IR emitter used in this calculation are listed in Table 2.  Using the current data acquired from the simulation, the apparent temperature was calculated using Equations (1) and (2): the desired properties of the IR emitter used in this calculation are listed in Table 2.

Properties Value
Resistance 15 kΩ ε · ff 0.47 G 1.0 µW/K λ 1 , λ 2 3 µm, 5 µm Figure 8 shows a graph of the relationship between digital input and apparent temperature considering the conventional and proposed RIIC, respectively, and Figure 9 shows a graph of the relationship between digital input and in-band power radiance. Comparing Figure 8a,b, the temperature difference between pixels decreases when using the proposed circuit structure. In particular, the maximum temperature difference decreased from 112 to 0.5 K.
Electronics 2020, 9, x FOR PEER REVIEW 7 of 10 3 µm, 5 µm Figure 8 shows a graph of the relationship between digital input and apparent temperature considering the conventional and proposed RIIC, respectively, and Figure 9 shows a graph of the relationship between digital input and in-band power radiance. Comparing Figure 8a,b, the temperature difference between pixels decreases when using the proposed circuit structure. In particular, the maximum temperature difference decreased from 112 to 0.5 K. The nonuniformity, which can be calculated with Equation (8) [9], was plotted as a function of the apparent temperature, as shown in Figure 10.
The highest nonuniformity value for a conventional RIIC was 21%, however, when the proposed structure was used, this quantity became lower than 0.1%. This value, therefore, is  3 µm, 5 µm Figure 8 shows a graph of the relationship between digital input and apparent temperature considering the conventional and proposed RIIC, respectively, and Figure 9 shows a graph of the relationship between digital input and in-band power radiance. Comparing Figure 8a,b, the temperature difference between pixels decreases when using the proposed circuit structure. In particular, the maximum temperature difference decreased from 112 to 0.5 K. The nonuniformity, which can be calculated with Equation (8) [9], was plotted as a function of the apparent temperature, as shown in Figure 10.
The highest nonuniformity value for a conventional RIIC was 21%, however, when the proposed structure was used, this quantity became lower than 0.1%. This value, therefore, is The nonuniformity, which can be calculated with Equation (8) [9], was plotted as a function of the apparent temperature, as shown in Figure 10.
Nonuni f ormity(%) = (σ radiance /avg radiance ) × 100, Electronics 2020, 9, 1603 8 of 10 operating at 200 Hz, accurate data sampling within a pixel-selecting time of nearly 0.04 µs would be needed [20]. As a result, the slow driving speed of the current-programming mechanism from the large line capacitance can prevent the performance of the proposed system [21][22][23][24][25]. In this case, the use of a column digital-to-analog converter (DAC) [26][27][28][29][30], which ensures a pixel-selecting time nearly 510 times longer than that of the single DAC structure, is a suitable solution.

Conclusions
We evaluated the operation and performance of a novel nonuniformity-immune RIIC composed of a dual-current-programming structure, which uses dual-functional transistors responsible for data sampling and current driving, to improve the accuracy of nonuniformity corrections. The results obtained from a post-layout simulation and data analyses indicated that the variance of the maximum apparent temperature and radiance nonuniformity were reduced from 122 to 0.5 K and from 21% to less than 0.1%, respectively. Therefore, the proposed RIIC design could be applied to IR sensor testing and evaluation applications with uniform IR scenes.