CRM PFC Converter with New Valley Detection Method for Improving Power System Quality

High efficiency and the power factor of power converters, are very important factors which can improve power system quality. In particular, research on improving low efficiency and the power factor at light-load conditions is essential. A boost power factor correction (PFC) is most commonly used in home appliances, with several operations being at light-loads; the critical conduction mode (CRM) control, fixed ON-time control, and valley detection technique are mainly applied to PFC control. However, these control schemes have the following problems: (1) low efficiency, due to sudden increase in switching frequency at light-loads; and (2) low power factor, due to switching ON-time limitation. This paper presents a new valley detection method that can actively extend the fixed ON-time to overcome these problems. Furthermore, a new valley point detection circuit and an ON-time extension signal generation circuit are proposed and described in detail. The superiority of the proposed method is demonstrated via comparison with two existing CRM PFC control methods, namely fixed ON-time (conventional#1) and existing valley detection (conventional#2) methods. Experimental results at 20% load demonstrate that the proposed method shows an efficiency improvement of 2.1%, compared with the fixed ON-time strategy; and a power factor improvement of 34.9%, compared with the existing valley detection strategy.


Introduction
Nowadays, conventional TVs are being replaced with smart TVs, and the usage of TVs has expanded from merely viewing purposes, to becoming media equipment. Smart TVs have built-in smart home hubs, that can monitor and control other Internet-of-things devices with existing TV functions. In other words, smart TVs have become a multiscreen to be connected to and operated with various devices, e.g., PCs, mobile phones, USBs, HDDs, Internet, etc., and watching is not necessitated. This means that a smart TV consumes more power than standby power, even if it is not operated as a conventional TV. In addition, owing to the rapid expansion of smart TVs, the efficiency and power factor at light-load can deteriorate the power system quality. Therefore, it is important to enhance the efficiency and power factor not only in heavy-load conditions, but also in light-load conditions for improving the power system quality.
In general, a 55-inch smart TV adopts a switch-mode power supply (SMPS) of approximately 200 W in consideration of power consumption, and the critical mode (CRM) boost power factor correction (PFC) topology is primarily adopted [1][2][3]. The CRM boost PFC can be implemented simply. However, the power conversion efficiency in relatively light-load conditions degrade, because the switching frequency increases in inverse proportion to the peak current level, which is decided by input voltage and load current [4][5][6].
value to retain the output voltage (V out ) at a target value, and the average value of the inductor current (I L ) in a switching cycle, i.e., the input current of the PFC converter is proportional to V in , as shown in Figure 2 [20][21][22][23][24]. It was observed that the CRM boost PFC shows a reduced power conversion efficiency, because the switching frequency was increased significantly at the low-input-voltage or light-load condition.
Electronics 2020, 9, x FOR PEER REVIEW 3 of 14 in a switching cycle, i.e., the input current of the PFC converter is proportional to Vin, as shown in Figure 2 [20][21][22][23][24]. It was observed that the CRM boost PFC shows a reduced power conversion efficiency, because the switching frequency was increased significantly at the low-input-voltage or light-load condition.

Switching Frequency Limit Method
To reduce switching loss in light-load and low-input-voltage conditions, i.e., short Ton, it is typical to limit the switching frequency, as shown in Figure 3. The timing to turn the switch ON is delayed until a predetermined time passes from the previous point when the switch is turned ON, even though IL returns to zero [5,25]. In this method, switching is reduced, but the average IL in a period also changes with the switching frequency. Therefore, it is difficult to reduce the limit of the switching frequency without degrading the power factor. Furthermore, switching with a low peak of IL is reduced, but still occurs when Vin is low. Such switching only consumes energy without contributing any energy transfer from the input to the output, as the energy stored in the inductor is insufficient to change the parasitic capacitance of the drain of the switch or to conduct the diode.  Electronics 2020, 9, x FOR PEER REVIEW 3 of 14 in a switching cycle, i.e., the input current of the PFC converter is proportional to Vin, as shown in Figure 2 [20][21][22][23][24]. It was observed that the CRM boost PFC shows a reduced power conversion efficiency, because the switching frequency was increased significantly at the low-input-voltage or light-load condition.

Switching Frequency Limit Method
To reduce switching loss in light-load and low-input-voltage conditions, i.e., short Ton, it is typical to limit the switching frequency, as shown in Figure 3. The timing to turn the switch ON is delayed until a predetermined time passes from the previous point when the switch is turned ON, even though IL returns to zero [5,25]. In this method, switching is reduced, but the average IL in a period also changes with the switching frequency. Therefore, it is difficult to reduce the limit of the switching frequency without degrading the power factor. Furthermore, switching with a low peak of IL is reduced, but still occurs when Vin is low. Such switching only consumes energy without contributing any energy transfer from the input to the output, as the energy stored in the inductor is insufficient to change the parasitic capacitance of the drain of the switch or to conduct the diode.

Switching Frequency Limit Method
To reduce switching loss in light-load and low-input-voltage conditions, i.e., short T on , it is typical to limit the switching frequency, as shown in Figure 3. The timing to turn the switch ON is delayed until a predetermined time passes from the previous point when the switch is turned ON, even though I L returns to zero [5,25]. In this method, switching is reduced, but the average I L in a period also changes with the switching frequency. Therefore, it is difficult to reduce the limit of the switching frequency without degrading the power factor. Furthermore, switching with a low peak of I L is reduced, but still occurs when V in is low. Such switching only consumes energy without contributing any energy transfer from the input to the output, as the energy stored in the inductor is insufficient to change the parasitic capacitance of the drain of the switch or to conduct the diode.
Electronics 2020, 9, x FOR PEER REVIEW 3 of 14 in a switching cycle, i.e., the input current of the PFC converter is proportional to Vin, as shown in Figure 2 [20][21][22][23][24]. It was observed that the CRM boost PFC shows a reduced power conversion efficiency, because the switching frequency was increased significantly at the low-input-voltage or light-load condition.

Switching Frequency Limit Method
To reduce switching loss in light-load and low-input-voltage conditions, i.e., short Ton, it is typical to limit the switching frequency, as shown in Figure 3. The timing to turn the switch ON is delayed until a predetermined time passes from the previous point when the switch is turned ON, even though IL returns to zero [5,25]. In this method, switching is reduced, but the average IL in a period also changes with the switching frequency. Therefore, it is difficult to reduce the limit of the switching frequency without degrading the power factor. Furthermore, switching with a low peak of IL is reduced, but still occurs when Vin is low. Such switching only consumes energy without contributing any energy transfer from the input to the output, as the energy stored in the inductor is insufficient to change the parasitic capacitance of the drain of the switch or to conduct the diode.

Existing Valley Switching Method
Additionally, the existing valley switching scheme, as shown in Figure 4, is widely known for reducing switching loss. After I L returns to zero, the drain-source voltage of the switch (V ds ) starts to decrease due to the resonance between the inductance of the inductor (L) and the drain-source parasitic capacitance of the switch (C oss ). Therefore, turning the switch ON at a valley of V ds is better than when I L returns to zero after a current through the diode stops, for efficiency.

Existing Valley Switching Method
Additionally, the existing valley switching scheme, as shown in Figure 4, is widely known for reducing switching loss. After IL returns to zero, the drain-source voltage of the switch (Vds) starts to decrease due to the resonance between the inductance of the inductor (L) and the drain-source parasitic capacitance of the switch (Coss). Therefore, turning the switch ON at a valley of Vds is better than when IL returns to zero after a current through the diode stops, for efficiency. To achieve this, a timer to measure a time equal to half the resonant frequency from when point IL reaches zero is widely used. The timer must be set depending on the resonant frequency from one converter to another; therefore, a pin for the setting is often assigned when such controllers are fabricated in ICs. However, the resonant frequency changes even in a converter, depending on the input voltage of the converter, because Coss contains the parasitic capacitance of a P-N junction in the MOSFET switch, which depends on the voltage applied to it. Furthermore, if we realize valley switching using the timer, even when a frequency limit function delays the timing for the switch to turn ON again, as shown in Figure 3, the timing of the valley must be estimated from the moment IL returns to zero after the current through the diode stops. The error of the timer against the resonant frequency accumulates. Therefore, this method is not practical when the number of valleys to be skipped before the switch turns ON is large.

Proposed Valley Detection Strategies with ON-Time Extension
In detail, this section describes the proposed valley detection strategies that can overcome the problems that arose with the CRM boost PFC converter that applied the existing valley detection method, as mentioned in Section 2. Figure 5 shows the inductor current applied to the proposed valley detection method. The detailed inductor current waveform at a light-load is compared with the conventional method, and is shown in Figure 6.  To achieve this, a timer to measure a time equal to half the resonant frequency from when point I L reaches zero is widely used. The timer must be set depending on the resonant frequency from one converter to another; therefore, a pin for the setting is often assigned when such controllers are fabricated in ICs. However, the resonant frequency changes even in a converter, depending on the input voltage of the converter, because C oss contains the parasitic capacitance of a P-N junction in the MOSFET switch, which depends on the voltage applied to it. Furthermore, if we realize valley switching using the timer, even when a frequency limit function delays the timing for the switch to turn ON again, as shown in Figure 3, the timing of the valley must be estimated from the moment I L returns to zero after the current through the diode stops. The error of the timer against the resonant frequency accumulates. Therefore, this method is not practical when the number of valleys to be skipped before the switch turns ON is large.

Proposed Valley Detection Strategies with ON-Time Extension
In detail, this section describes the proposed valley detection strategies that can overcome the problems that arose with the CRM boost PFC converter that applied the existing valley detection method, as mentioned in Section 2. Figure 5 shows the inductor current applied to the proposed valley detection method. The detailed inductor current waveform at a light-load is compared with the conventional method, and is shown in Figure 6.

Existing Valley Switching Method
Additionally, the existing valley switching scheme, as shown in Figure 4, is widely known for reducing switching loss. After IL returns to zero, the drain-source voltage of the switch (Vds) starts to decrease due to the resonance between the inductance of the inductor (L) and the drain-source parasitic capacitance of the switch (Coss). Therefore, turning the switch ON at a valley of Vds is better than when IL returns to zero after a current through the diode stops, for efficiency. To achieve this, a timer to measure a time equal to half the resonant frequency from when point IL reaches zero is widely used. The timer must be set depending on the resonant frequency from one converter to another; therefore, a pin for the setting is often assigned when such controllers are fabricated in ICs. However, the resonant frequency changes even in a converter, depending on the input voltage of the converter, because Coss contains the parasitic capacitance of a P-N junction in the MOSFET switch, which depends on the voltage applied to it. Furthermore, if we realize valley switching using the timer, even when a frequency limit function delays the timing for the switch to turn ON again, as shown in Figure 3, the timing of the valley must be estimated from the moment IL returns to zero after the current through the diode stops. The error of the timer against the resonant frequency accumulates. Therefore, this method is not practical when the number of valleys to be skipped before the switch turns ON is large.

Proposed Valley Detection Strategies with ON-Time Extension
In detail, this section describes the proposed valley detection strategies that can overcome the problems that arose with the CRM boost PFC converter that applied the existing valley detection method, as mentioned in Section 2. Figure 5 shows the inductor current applied to the proposed valley detection method. The detailed inductor current waveform at a light-load is compared with the conventional method, and is shown in Figure 6.

Realization of Proposed Method
To prevent switching without transferring energy from the input to the output, the ON-time of the switch is extended if the inductor current does not exceed a predetermined level. Simultaneously, the OFF-time should be extended when the average current in the cycle is the same as that when the ON-time is not extended; that is, when the switching period (Tsw) satisfies Equation (1).
where IL is the inductor current, Tsw is the switching period, Tono is the ON-time before it is extended, Vin is the input voltage, and L is the inductance. A circuit to realize this control is shown in Figure 7. A ramp generator generates a ramp signal voltage (Vramp), which begins to increase at the moment the switch turns ON. An error amplifier amplifies the difference between the voltage feedback signal from the PFC converter (VFB) and a predetermined reference voltage (Vref), and generates an output voltage (Vea). Vramp is compared with Vea, and the current sense signal from the PFC converter (VCS) is compared with a voltage corresponding to the predetermined minimum level of the inductor current (Vcsmin). An OFF trigger signal to turn the switch OFF is generated if VCS is larger than Vcsmin when Vramp reaches Vea, similar to conventional CRM boost PFC converters.
In another case, the OFF trigger signal is generated when VCS reaches Vcsmin, that is, when the ONtime is extended. After the switch turns OFF, the point where the inductor current returns to zero (Tzcd) is detected, by comparing VCS with a voltage corresponding to the state (Tzcd), which is typically slightly lower than zero. An ON trigger signal to turn the switch ON is generated by a current signal generator, capacitor, reset switch, and comparator. To realize extended ON-time, the reference current signal (Iint), which is the output of the current signal generator as shown in Figure 7, should be defined first; this signal should be defined by each section, according to the levels of Vramp and Vea, as shown in Figure 8. Iint for each mode in Figure 8 is described as follows:

Realization of Proposed Method
To prevent switching without transferring energy from the input to the output, the ON-time of the switch is extended if the inductor current does not exceed a predetermined level. Simultaneously, the OFF-time should be extended when the average current in the cycle is the same as that when the ON-time is not extended; that is, when the switching period (T sw ) satisfies Equation (1).
where I L is the inductor current, T sw is the switching period, T ono is the ON-time before it is extended, V in is the input voltage, and L is the inductance. A circuit to realize this control is shown in Figure 7. A ramp generator generates a ramp signal voltage (V ramp ), which begins to increase at the moment the switch turns ON. An error amplifier amplifies the difference between the voltage feedback signal from the PFC converter (V FB ) and a predetermined reference voltage (V ref ), and generates an output voltage (V ea ). V ramp is compared with V ea , and the current sense signal from the PFC converter (V CS ) is compared with a voltage corresponding to the predetermined minimum level of the inductor current (V csmin ). An OFF trigger signal to turn the switch OFF is generated if V CS is larger than V csmin when V ramp reaches V ea , similar to conventional CRM boost PFC converters. where Iint is the output current generated by the current signal generator, K is constant value which can be selected for easy circuit implementation, Vramp is ramp signal voltage, Vea is the generated output voltage, Tzcd is the time when the inductor current returns to zero, and Tsw is switching period.
Here, for brevity, it is assumed that the ramp signal starts at 0 V. In another case, the OFF trigger signal is generated when V CS reaches V csmin , that is, when the ON-time is extended. After the switch turns OFF, the point where the inductor current returns to zero (T zcd ) is detected, by comparing V CS with a voltage corresponding to the state (T zcd ), which is typically slightly lower than zero. An ON trigger signal to turn the switch ON is generated by a current signal generator, capacitor, reset switch, and comparator. To realize extended ON-time, the reference current signal (I int ), which is the output of the current signal generator as shown in Figure 7, should be defined Electronics 2020, 9, 38 6 of 14 first; this signal should be defined by each section, according to the levels of V ramp and V ea , as shown in Figure 8. I int for each mode in Figure 8 is described as follows: where I int is the output current generated by the current signal generator, K is constant value which can be selected for easy circuit implementation, V ramp is ramp signal voltage, V ea is the generated output voltage, T zcd is the time when the inductor current returns to zero, and T sw is switching period. Here, for brevity, it is assumed that the ramp signal starts at 0 V. where Iint is the output current generated by the current signal generator, K is constant value which can be selected for easy circuit implementation, Vramp is ramp signal voltage, Vea is the generated output voltage, Tzcd is the time when the inductor current returns to zero, and Tsw is switching period.
Here, for brevity, it is assumed that the ramp signal starts at 0 V.

Description of ON-Time Extension
At the moment when the switch turns ON, the reset switch discharges the capacitor. Subsequently, the capacitor generates a voltage corresponding to the integration of Iint. When the ONtime is extended, the voltage stored in the capacitor is larger than zero at the moment when the switch turns OFF, and is reduced by Iint ( ea K V − ⋅ ) subsequently. Finally, it reaches zero, and the comparator generates the ON trigger signal. Figure 8 illustrates the waveforms when the ON-time is extended. During the ON-time, IL and Vramp continue increasing. Simultaneously, the capacitor integrates Iint, which is proportional to twice that of the difference between Vramp and Vea. The switch is turned off when IL reaches a predetermined level (ILmin). Subsequently, IL decreases and returns to zero. During that time, the value of Vramp remains the previous value at the moment the switch turns OFF, and Iint is proportional to the difference between Vramp and Vea. After IL reaches zero (in fact, IL remains in resonance with a small amplitude,

Description of ON-Time Extension
At the moment when the switch turns ON, the reset switch discharges the capacitor. Subsequently, the capacitor generates a voltage corresponding to the integration of I int . When the ON-time is extended, the voltage stored in the capacitor is larger than zero at the moment when the switch turns OFF, and is reduced by I int (−K·V ea ) subsequently. Finally, it reaches zero, and the comparator generates the ON trigger signal. Figure 8 illustrates the waveforms when the ON-time is extended. During the ON-time, I L and V ramp continue increasing. Simultaneously, the capacitor integrates I int , which is proportional to twice that of the difference between V ramp and V ea . The switch is turned off when I L reaches a predetermined level (I Lmin ). Subsequently, I L decreases and returns to zero. During that time, the value of V ramp remains the previous value at the moment the switch turns OFF, and I int is proportional to the difference between V ramp and V ea . After I L reaches zero (in fact, I L remains in resonance with a small amplitude, owing to the parasitic capacitance in this region; however, it is omitted for a simple illustration), the capacitor is discharged by I int , which is a constant value depending on V ea . When the voltage stored in the capacitor reaches zero, the switch is turned ON again, and the same operation in the previous period repeats. Here, it can be confirmed that the length of a period (T sw ) decided by integrating I int satisfies Equation (1), which describes a desirable operation. Additionally, the voltage between the switches remain in resonance in the time period when I L remains in resonance; and T sw can be adjusted within a range of cycles of resonant frequency, by combining techniques typically employed in conventional PFC converters. For minimizing loss, it is better to delay the timing to turn ON the switch from T sw , as calculated by Equation (1), to the next valley of V d , where the loss from turning the switch ON is the smallest.

Circuit Implementations and Design Considerations
In this section, two methods of detecting the valley of V d in detail are examined, and the actual implementation circuitry for each method is described.

Proposed Valley Detect Method with Current Sense Voltage
One of the methods, involves the detection of the moment V CS crosses zero, from positive to negative. In this case, no additional external component is necessary, but the V CS in the resonant region of V d is typically small, and noise should be considered. Figure 9a shows a circuit to detect the zero-cross of V CS , where an offset cancel topology is employed to avoid the effect transistor mismatch in detecting small voltages. When valley detection is not required, the switches controlled by DET b turn ON, and the voltage corresponding to the condition V CS = 0 is stored to the capacitor C hold . In detecting the valley, the switch controlled by DET turns ON, and the voltage depending on V CS is compared with the voltage stored in C hold . We can adjust the gain from V CS to the voltage for the comparison, with resistors R csin and R csa . By verifying the moment that the comparator output changes from high to low during the detection, we can detect the moment that V CS crosses zero, from positive to negative. owing to the parasitic capacitance in this region; however, it is omitted for a simple illustration), the capacitor is discharged by Iint, which is a constant value depending on Vea. When the voltage stored in the capacitor reaches zero, the switch is turned ON again, and the same operation in the previous period repeats. Here, it can be confirmed that the length of a period (Tsw) decided by integrating Iint satisfies Equation (1), which describes a desirable operation. Additionally, the voltage between the switches remain in resonance in the time period when IL remains in resonance; and Tsw can be adjusted within a range of cycles of resonant frequency, by combining techniques typically employed in conventional PFC converters. For minimizing loss, it is better to delay the timing to turn ON the switch from Tsw, as calculated by Equation (1), to the next valley of Vd, where the loss from turning the switch ON is the smallest.

Circuit Implementations and Design Considerations
In this section, two methods of detecting the valley of Vd in detail are examined, and the actual implementation circuitry for each method is described.

Proposed Valley Detect Method with Current Sense Voltage
One of the methods, involves the detection of the moment VCS crosses zero, from positive to negative. In this case, no additional external component is necessary, but the VCS in the resonant region of Vd is typically small, and noise should be considered. Figure 9a shows a circuit to detect the zero-cross of VCS, where an offset cancel topology is employed to avoid the effect transistor mismatch in detecting small voltages. When valley detection is not required, the switches controlled by DETb turn ON, and the voltage corresponding to the condition VCS = 0 is stored to the capacitor Chold. In detecting the valley, the switch controlled by DET turns ON, and the voltage depending on VCS is compared with the voltage stored in Chold. We can adjust the gain from VCS to the voltage for the comparison, with resistors Rcsin and Rcsa. By verifying the moment that the comparator output changes from high to low during the detection, we can detect the moment that VCS crosses zero, from positive to negative.

Proposed Valley Detect Method with Divided Drain Voltage
The other method is to divide Vd using two capacitors, i.e., C1 and C2, as shown in Figure 10, and to sense the moment that the differentiation of the divided voltage VVAL changes from negative to positive. One of the two capacitors (C2) is often used in practical applications to reduce EMI noise, and only one low-voltage capacitor (C1) is necessary in this case. The value of the capacitors for the divided voltage should not exceed the input range of the circuit receiving it. Figure 9b shows a valley detection circuit with the divided voltage of Vd. Part of the circuit is the same as that shown in Figure  9a, and a differentiator is additionally included. Owing to the capacitor Cdiv connected between the input and the node with near constant voltage maintained by the source-follower transistors, the current proportional to dVVAL/dt is generated, and converted to the voltage fed to the comparator.

Proposed Valley Detect Method with Divided Drain Voltage
The other method is to divide V d using two capacitors, i.e., C1 and C2, as shown in Figure 10, and to sense the moment that the differentiation of the divided voltage V VAL changes from negative to positive. One of the two capacitors (C2) is often used in practical applications to reduce EMI noise, and only one low-voltage capacitor (C1) is necessary in this case. The value of the capacitors for the divided voltage should not exceed the input range of the circuit receiving it. Figure 9b shows a valley detection circuit with the divided voltage of V d . Part of the circuit is the same as that shown in Figure 9a, and a differentiator is additionally included. Owing to the capacitor C div connected between the input and the node with near constant voltage maintained by the source-follower transistors, the current proportional to dV VAL /dt is generated, and converted to the voltage fed to the comparator. When valley detection is not required, the switches controlled by DET b turn ON; the voltage corresponding to when the current proportional to dV VAL /dt is equal to zero is stored in capacitor C hold . In detecting the valley, the switch controlled by DET turns ON, and the current-voltage proportional to dV VAL /dt is compared with the voltage stored in C hold . By verifying the moment when the comparator output changes from low to high during the detection, we can detect the moment when the differentiation of VAL changes from negative to positive. When valley detection is not required, the switches controlled by DETb turn ON; the voltage corresponding to when the current proportional to dVVAL/dt is equal to zero is stored in capacitor Chold.
In detecting the valley, the switch controlled by DET turns ON, and the current-voltage proportional to dVVAL/dt is compared with the voltage stored in Chold. By verifying the moment when the comparator output changes from low to high during the detection, we can detect the moment when the differentiation of VAL changes from negative to positive.

Simualtion Results
The two valley detection methods described in Sections 3 and 4 were verified by computer simulations with the circuit shown in Figure 11. Moreover, the parameters used in the simulations are detailed in the schematic. Acquiring accurate data is very important for accurate valley detection and ON-time calculation [26]. Therefore, properly designed low-pass filters were used in the sensing stage, such as 'VCS' and 'VVAL'. Figures 12 and 13 show the operating waveforms in different Vin conditions, i.e., 300 and 100 V, in a light-load condition. To verify the effect of delay for the current detection, the low-pass filters for Vcs is changed in the ranges of 50 Ω-47 pF and 39 Ω-5 nF. The simulation results in Figures 12 and  13 correspond to the valley detection circuits with Vcs and VVAL, respectively.
When the low-pass filter is 50 Ω-47 pF, the delay caused by it is negligible, the peak value of IL is almost the same even if Vin decreases from 300 V to 100 V, and only switching frequency decreases; from which we can confirm that the proposed control method in light-load conditions operates properly. Moreover, we can confirm that the switch always turns ON near the valley of Vd in both valley detection circuits.
When the low-pass filter is 39 Ω-5 nF, the dependency of the peak value of IL on Vin increases, because slope of IL depends on Vin, and a larger slope results in a larger extension owing to the delay of the low-pass filter. When the peak value of IL increases, owing to delay of the low-pass filter, the switching frequency decreases to cancel its effect.

Simualtion Results
The two valley detection methods described in Sections 3 and 4 were verified by computer simulations with the circuit shown in Figure 11. Moreover, the parameters used in the simulations are detailed in the schematic. Acquiring accurate data is very important for accurate valley detection and ON-time calculation [26]. Therefore, properly designed low-pass filters were used in the sensing stage, such as 'V CS ' and 'V VAL '.

Simualtion Results
The two valley detection methods described in Sections 3 and 4 were verified by computer simulations with the circuit shown in Figure 11. Moreover, the parameters used in the simulations are detailed in the schematic. Acquiring accurate data is very important for accurate valley detection and ON-time calculation [26]. Therefore, properly designed low-pass filters were used in the sensing stage, such as 'VCS' and 'VVAL'. Figures 12 and 13 show the operating waveforms in different Vin conditions, i.e., 300 and 100 V, in a light-load condition. To verify the effect of delay for the current detection, the low-pass filters for Vcs is changed in the ranges of 50 Ω-47 pF and 39 Ω-5 nF. The simulation results in Figures 12 and  13 correspond to the valley detection circuits with Vcs and VVAL, respectively.
When the low-pass filter is 50 Ω-47 pF, the delay caused by it is negligible, the peak value of IL is almost the same even if Vin decreases from 300 V to 100 V, and only switching frequency decreases; from which we can confirm that the proposed control method in light-load conditions operates properly. Moreover, we can confirm that the switch always turns ON near the valley of Vd in both valley detection circuits.
When the low-pass filter is 39 Ω-5 nF, the dependency of the peak value of IL on Vin increases, because slope of IL depends on Vin, and a larger slope results in a larger extension owing to the delay of the low-pass filter. When the peak value of IL increases, owing to delay of the low-pass filter, the switching frequency decreases to cancel its effect.  Figures 12 and 13 show the operating waveforms in different V in conditions, i.e., 300 and 100 V, in a light-load condition. To verify the effect of delay for the current detection, the low-pass filters for V cs is changed in the ranges of 50 Ω-47 pF and 39 Ω-5 nF. The simulation results in Figures 12 and 13 correspond to the valley detection circuits with V cs and V VAL , respectively.
When the low-pass filter is 50 Ω-47 pF, the delay caused by it is negligible, the peak value of I L is almost the same even if V in decreases from 300 V to 100 V, and only switching frequency decreases; from which we can confirm that the proposed control method in light-load conditions operates properly. Moreover, we can confirm that the switch always turns ON near the valley of V d in both valley detection circuits.
When the low-pass filter is 39 Ω-5 nF, the dependency of the peak value of I L on V in increases, because slope of I L depends on V in , and a larger slope results in a larger extension owing to the delay of the low-pass filter. When the peak value of I L increases, owing to delay of the low-pass filter, the switching frequency decreases to cancel its effect.   The timing for when the switch turns ON deviates significantly from the valley of V d , when a valley detection circuit with V cs is employed; however, it does not change, owing to the delay of the low-pass filter, when a valley detection circuit with V VAL is employed. Figure 14a shows an actual IC picture of the proposed valley detection circuit using the TowerJazz 0.18 µm 5 V/42 V CMOS process (TS035), and Figure 14b shows the experimental setup using the fabricated IC. This IC is designed as an output power in a full-load condition of approximately 240 W; however, the experimental results are focused on light-load conditions within a 40 W load, which is approximately 20% of the rated output power, to verify the improvement in power factor and efficiency under light-load conditions.   Figure 15a shows the time-extended inductor current waveform shown in Figure 8, with the current sense voltage valley detection circuit shown in Figure 9a. As shown, the delay in switching ON is calculated by calculating t sw , satisfying Equation (1). Figure 15b shows the inductor current of the existing CRM boost PFC. The switching frequency in the zero-crossing region at a 40 W load is 130 kHz and shows a typical CRM boost PFC inductor current waveform, similar to that shown in Figure 2. Figure 15c shows the inductor current when the proposed valley switching technique is applied. The switching frequency is reduced to 76 kHz through the new valley detector method and the ON-time is extended, as shown in Figures 6 and 8, even under the same load condition. Figure 16a-c show the comparison results of the light-load efficiency and power factor, between the existing CRM boost PFC method and the new valley detection method. Two commercial ICs were selected as the comparison group, and their performance was compared with that of the proposed method, to confirm the superiority of the proposed method more accurately. For the first comparison group (conventional#1), the SPC7011F manufactured by Fuji, with a fixed ON-time, and SFL of 500 kHz was used [20]. The second comparison group (conventional#2) had an existing valley detection method that was limited to 150 kHz at light-loads, and the On Semi's NPC1602 was used for this [21]. The comparison result between the proposed method and conventional#1 shows an efficiency difference of 2.1% in the 40 W load condition; moreover, it shows an efficiency difference of up to 13% in the 1 W condition. This is due to the switching loss, caused by the increase of switching frequency to 500 kHz in the light-load or low-input-voltage condition. Furthermore, the MOSFET is turned on at a high V ds voltage while resonating, which may reduce the efficiency. In terms of power factor, due to its fast switching in light-load and low-input-voltage conditions, the conventional#1 method achieves a higher power factor than the conventional#2 method. As a result, the power factor of the conventional#1 method was measured at 0.85 and 0.93 at 5 W and 40 W, respectively, while that of the proposed method was 0.95 and 0.985 under the same conditions, respectively. All the test conditions were controlled identically, and the comparison experiment was conducted after changing only the conventional#1 method to conventional#2 method. The efficiency of the conventional#2 method was 97% at 40 W and 48% at 1 W, which was 0.7% and 4% lower than that of the proposed method, respectively. However, this indicates that the conventional#2 method is relatively better than the conventional#1 method, in terms of efficiency. This result is because of the reduction in switching losses due to the limited switching frequency of 150 kHz, especially in light-load and low-input-voltage conditions. Compared with the proposed method, the efficiency drop in the conventional#2 method increases as the load decreases. The analysis indicates that the reason for this result is the switching ON time limit of the conventional#2 method at light-loads and low-input-voltages. Compared with the proposed method, the power factor of the conventional#2 method shows a significantly larger difference under an 80 W load; moreover, a power factor difference of 0.581 is observed at 1 W. These results can be attributed to the large current distortion caused by the switching limitation of the conventional#2 controller in light-load and low-input-voltage conditions.

Conclusions
Herein, a new valley detection method, that includes the ON-time extension strategy, to improve both efficiency and power factor in light-load conditions in CRM controlled boost PFC converters, was proposed. In this method, the ON-time of the switch was extended unless the current of the inductor reached a predetermined level, and the OFF time was extended such that the average current of the inductor in a cycle remained the same as that without extending the ON-time. The theory of the ON-time extension method, the circuit implementation, and the circuit of the actual implemented IC were presented and explained in detail. A circuit for achieving the control method was designed in a 0.35 um CMOS IC process, where a circuit detecting the lowest point of drain voltage of the switch, which turned the switch ON at that moment, was included. Experimental results demonstrated that the proposed method obtains a significant 13% improvement in efficiency, compared with that of a fixed ON-time method; and an excellent power factor improvement of 0.581, compared with an existing valley detection method under a 1 W load condition. As a result, this study can be applied to power converters using CRM boost PFC as well as home appliances such as smart TVs, which operate under several light-load conditions. This study is expected to contribute to the improvement of power quality by improving efficiency and power factor.

Conclusions
Herein, a new valley detection method, that includes the ON-time extension strategy, to improve both efficiency and power factor in light-load conditions in CRM controlled boost PFC converters, was proposed. In this method, the ON-time of the switch was extended unless the current of the inductor reached a predetermined level, and the OFF time was extended such that the average current of the inductor in a cycle remained the same as that without extending the ON-time. The theory of the ON-time extension method, the circuit implementation, and the circuit of the actual implemented IC were presented and explained in detail. A circuit for achieving the control method was designed in a 0.35 um CMOS IC process, where a circuit detecting the lowest point of drain voltage of the switch, which turned the switch ON at that moment, was included. Experimental results demonstrated that the proposed method obtains a significant 13% improvement in efficiency, compared with that of a fixed ON-time method; and an excellent power factor improvement of 0.581, compared with an existing valley detection method under a 1 W load condition. As a result, this study can be applied to power converters using CRM boost PFC as well as home appliances such as smart TVs, which operate under several light-load conditions. This study is expected to contribute to the improvement of power quality by improving efficiency and power factor.

Conflicts of Interest:
The authors declare no conflict of interest.