Low Noise, High Input Impedance Digital-Analog Hybrid O ﬀ set Suppression Ampliﬁer for Wearable Dry Electrode ECG Monitoring

: The portable real-time electrocardiogram (ECG) is a convenient and promising electronic device for cardiovascular diseases patients. However, unlike wet gel electrodes in traditional clinical applications, dry electrodes are competent for comfortable long-time wearing and can prevent skin ulceration. Its ultra-high source impedance and electrode o ﬀ set (EOS) make traditional chopper ampliﬁers with low input impedance and limited EOS range di ﬃ cult to apply to this area. To overcome these challenges, this paper proposes a novel chopper ampliﬁer topology. This architecture includes a gain control loop, a ripple reduction loop, and a DC-servo loop (DSL). The proposed sampling input stage and digital-analog hybrid DSL are employed to boost input impedance and extend the EOS handing range. Designed with a 0.18 µ m 1P6M 1.8 V CMOS salicide process, the proposed chopper capacitively coupled instrumentation ampliﬁer achieves an ultra-high input impedance of 120 G Ω ( < 0.05 Hz) or 2.1 G Ω (0.6~250 Hz), an EOS handing range of ± 325 mV and a low noise of 1.9 µ Vrms at 0.6~250 Hz. It occupies an area of 0.36 mm 2 and only consumes a quiescent current of 11 µ A.


Introduction
Cardiovascular diseases (CVDs) are the biggest killer of global human health. Of all worldwide deaths every year, nearly 31%, a conservatively estimated 17.9 million, are caused by CVDs [1]. As one of the major physiological vital signs, the electrocardiogram (ECG) is widely recognized as a diagnostic tool and standard for medical and research purposes. Real-time ECG monitoring shows clear advantages in preventing CVDs [2]. However, the traditional clinical ECG with wet gel electrodes (usually Ag/AgCl electrodes) normally requires a galvanic contact to the body and often skin preparation, which may cause skin irritation. Dry electrodes solve this problem by eliminating the need for gel, which in turn enables a faster setup time and improves patients' comfort. However, the flaw is its high electrode-skin impedance. Typical dry-electrode impedance is in a range from a few hundreds of kiloohms to a few tens of megaohms [3], leading to a large signal attenuation and a significant increase in noise and offset [4].
A reliable, real-time portable ECG monitoring system has to satisfy some challenging requirements. First of all, it must be able to cope with the effects of large skin-electrode impedance changes on the signal, usually by a pre-amplifier with very high input-impedance to minimize signal attenuation and degeneration [5]. Chopper-stabilized amplifier is a popular front-end topology for ECG monitoring and neural recording [6][7][8][9][10], as the chopper technique is an effective way to suppress low-frequency

System Overview
The proposed system diagram is shown in Figure 1. This ECG amplifier system consists of sampling input stage, chopper amplifier, ripple reduction loop, gain control loop and digital-analog hybrid DSL. The chopper amplifier adopts a basic two-stage Miller compensated amplifier, which is composed of MX1, MX2, C IN , G m1 , G m2 , C 31 and C 32 . It has two feedback connections for gain control and ripple reduction, respectively. Its circuit implementation will be described in Section 3. The gain control loop of the ECG amplifier consists of MX4, C 1x , C 2x and FB 1 , which defines the pass-band gain as: C 21 + C 11 C 11 (1) Electronics 2019,x, x FOR PEER REVIEW 2 of 13 low-frequency flicker noise of the amplifier [11]. However, chopping reduces the DC input impedance of the amplifier because the passive mixer at the input together with the input capacitor forms a switched-capacitor resistance. To boost the input impedance, a positive-feedback loop has been used in [7]. However, the positive-feedback loop is rendered inoperative at DC, and due to the parasitic capacitance appearing at the input node, the realized impedance boost is limited to a factor of 5 [8]. Another challenge is the electrode offset voltage, which can be as large as several hundred millivolts. It may reduce the pre-amplifier's headroom or even easily saturate its output [5]. In such a case, a DC-servo loop (DSL) is usually employed to attenuate the electrode offset (EOS) at the output. However, it has to tradeoff between capability of handling EOS and noise [12]. This paper presents a low noise, high input impedance digital-analog hybrid offset suppression amplifier to address the aforementioned challenges. The main amplification path is a chopperstabilized amplifier, which effectively suppresses the low-frequency flicker noise. To boost the input impedance at the ECG frequency range of 0~250 Hz, a sampling input stage has been adopted. A digital-analog hybrid servo loop is employed to attenuate the EOS at the output, which can reduce the noise contribution of the servo loop and keep the capability of handling EOS voltage. A ripple reduction loop (RRL) is used to attenuate the ripple at the outputs. The gain of the circuit is determined by the gain control loop. This paper is organized as follows. Section 2 describes the architecture of the proposed circuit. Section 3 discusses the detail circuit implementation. Section 4 presents the results of system characterization and a comparison table. Section 5 concludes the paper.

System Overview
The proposed system diagram is shown in Figure 1. This ECG amplifier system consists of sampling input stage, chopper amplifier, ripple reduction loop, gain control loop and digital-analog hybrid DSL. The chopper amplifier adopts a basic two-stage Miller compensated amplifier, which is composed of MX1, MX2, CIN, Gm1, Gm2, C31 and C32. It has two feedback connections for gain control and ripple reduction, respectively. Its circuit implementation will be described in Section 3. The gain control loop of the ECG amplifier consists of MX4, C1x, C2x and FB1, which defines the pass-band gain as:  The drawback of chopper amplifier is that its input signal becomes DC-coupled, because the input signal is shifted to its chopping frequency. Hence a DSL should be added to suppress the EOS and implement a high-pass corner frequency at f L ≈ 0.6 Hz. The high-pass corner frequency is [12]: where β is the attenuation coefficient of the attenuator in the analog DSL, G 0 is the closed-loop gain of the chopper amplifier, and f 0 is the unity gain frequency of the analog DSL. In this design, G m1 /FB 1 = 6.2, C 21 /C 11 = 34, β = 0.1, f 0 is about 35.6 mHz. Thus, the pass-band gain and the high-pass corner frequency are around 217 and 772 mHz, respectively. As shown in Figure 1, the input of G m1 is not a voltage feedback node or a "virtual ground", because the RRL, analog DSL and gain control loop are not connected to the input of G m1. Thus, the input equivalent capacitance is equal to the series capacitance of C IN and C par . The differential input impedance is determined by the equivalent switched-capacitor resistance: where f CH is the chopping frequency, C par is the parasitic capacitance appearing at the input of G m1 . Usually C par is very small so that the input impedance Z in is high enough. In this design, the input differential pairs work in sub-threshold region to minimize the parasitic capacitance, and C par is about 5 fF, f CH = 20 kHz. Thus, the input impedance is around 2.5 GΩ at the passband. The input-referred noise of the whole chopper amplifier due to the white noise of the pseudo resistor (P-RES) and G DSL can be estimated as [12]: where f H is the −3 dB frequency of the chopper amplifier. In order to minimize the noise, a smaller attenuation coefficient β of the attenuator is preferred. However, a small β will limit the capability of handling EOS. Hence the digital DSL was used to extend the EOS handling range.

Circuit Implementation
In the previous section, we have presented an overview of the system, and in this section, we will discuss the circuit-level implementation issues in details.

Two-Stage Chopper Amplifier
The main two-stage amplifier (G m1 , G m2 ), the gain control transconductance (FB 1 ), and the ripple compensation transconductance (FB 2 ) are shown in Figure 2. In order to achieve high input impedance, FB 1 and FB 2 are added to provide current feedback. Additional feedback increases circuit noise unavoidably. It means that there should be distributed current properly to minimize noise. Additionally, to increase the noise efficiency, the input pairs are biased in sub-threshold region and the current of G m1 is seven times larger than that of FB 1 and FB 2 . The Miller compensation capacitors are C 3x and are also used as a low-pass filter capacitor.

Sampling Input Stage
To boost the input impedance at low frequency, the DSL feedback loop cannot be connected to the input of Gm1. Therefore, the sampling input stage is added to the system for easy access to DSL feedback. The sampling input stage is shown in Figure 3. Block1 and block2 act as a ping-pong structure to implement a continuous-time system. K1x   During the sampling phase Ф1, the voltages over the sampling capacitors CS1 and CS2 can be expressed as: Cs1 inn DDSLn During the signal phase Ф2, the input voltage Vampin can be expressed as:

Sampling Input Stage
To boost the input impedance at low frequency, the DSL feedback loop cannot be connected to the input of G m1 . Therefore, the sampling input stage is added to the system for easy access to DSL feedback. The sampling input stage is shown in Figure 3. Block1 and block2 act as a ping-pong structure to implement a continuous-time system. K 1x and K 2x are controlled by a non-overlapping clock Φ 1 and Φ 2 . C S1 , C S2 , C S3 and C S4 are sampling capacitors. In block1, during the sampling phase Φ 1 , K 2x are open and K 1x are closed. During the signal phase Φ 2 , K 2x are closed and K 1x are open.

Sampling Input Stage
To boost the input impedance at low frequency, the DSL feedback loop cannot be connected to the input of Gm1. Therefore, the sampling input stage is added to the system for easy access to DSL feedback. The sampling input stage is shown in Figure 3. Block1 and block2 act as a ping-pong structure to implement a continuous-time system. K1x   During the sampling phase Ф1, the voltages over the sampling capacitors CS1 and CS2 can be expressed as: Cs1 inn DDSLn During the signal phase Ф2, the input voltage Vampin can be expressed as: During the sampling phase Φ 1 , the voltages over the sampling capacitors C S1 and C S2 can be expressed as: During the signal phase Φ 2 , the input voltage V ampin can be expressed as: Electronics 2020, 9, 165 5 of 13 A point of note from Equation (7) is that the sampling input stage can effectively implement DSL feedback. If V DSL is equal to the EOS, the DC portion of the input signal will be removed.

Input Impedance
The traditional chopper capacitively coupled instrumentation amplifier with DSL is shown in Figure 4a. According to the analysis in [8,12], the positive feedback loop is rendered inoperative at DC. Therefore, the DC input impedance can be expressed as: With the typical values of C in = 10 pF and f CH = 20 kHz, the DC input impedance is limited to 1.25 MΩ, which is significantly lower than the basic requirement of 1 GΩ.
A point of note from Equation (7) is that the sampling input stage can effectively implement DSL feedback. If VDSL is equal to the EOS, the DC portion of the input signal will be removed.

Input Impedance
The traditional chopper capacitively coupled instrumentation amplifier with DSL is shown in Figure 4a. According to the analysis in [8,12], the positive feedback loop is rendered inoperative at DC. Therefore, the DC input impedance can be expressed as: With the typical values of Cin = 10 pF and fCH = 20 kHz, the DC input impedance is limited to 1.25 MΩ, which is significantly lower than the basic requirement of 1 GΩ.
Virtual ground The equivalent input impedance of the proposed sampling input stage circuit is shown in Figure  4b. As the RRL is a narrow bandpass feedback, it has little effect on the input impedance at the frequency of interest. Thus, the RRL is not included in Figure 4b. During the sampling phase Ф1, the voltage of CS tracks the input signal. During the signal phase Ф2, the electronic charge transferred from CS to the chopper amplifier. According to the principle of switched capacitor, the charge charged to CS in the sampling phase of the previous cycle is equal to the charge transferred to the chopper The equivalent input impedance of the proposed sampling input stage circuit is shown in Figure 4b. As the RRL is a narrow bandpass feedback, it has little effect on the input impedance at the frequency of interest. Thus, the RRL is not included in Figure 4b. During the sampling phase Φ 1 , the voltage of C S tracks the input signal. During the signal phase Φ 2 , the electronic charge transferred from C S to the chopper amplifier. According to the principle of switched capacitor, the charge charged to C S in the sampling phase of the previous cycle is equal to the charge transferred to the chopper amplifier in the next cycle (Q 1 = Q 2 ). Ignoring the sampling loss, the input terminal current is equal to the input Electronics 2020, 9, 165 6 of 13 current of the chopper amplifier. Thus, the differential input impedance is determined by the input parasitic capacitance of the chopper amplifier and the chopping frequency; the expression has been given as Equation (3). With the typical values C par = 5 fF and f CH = 20 kHz, the input impedance up to 2.5 GΩ in the signal frequency. Meanwhile, if the loop gain is infinite, V DSL is equal to EOS in Equation (7) and V ampin,dc = 0. Therefore, the DC input current is zero and the DC input impedance is infinite. In fact, the DC input impedance is higher than 170 GΩ, even in view of the limited loop gain.

Digital-Analog Hybrid DC-Servo Loop
The DC-servo loop is employed to attenuate the EOS at the output, which is actually equivalent to a low pass filter. It can be seen from Figure 1 that the noise of the DSL circuit is chopped twice. Therefore, the DSL circuit noise cannot be reduced by chopping and it directly affects the noise performance of the entire circuit. In order to analyze the noise of the DSL, the circuit can be simplified to Figure 5a, where V n is the equivalent input-referred noise of the DSL amplifier. Since f H is much smaller than f sig.min , the impedance of the capacitor is much smaller than the impedance of the resistor. Ignoring the impedance of the capacitor as shown in Figure 5b, we can find that the output noise is equal to the input noise and it is independent of the amplifier gain.
Electronics 2019,x, x FOR PEER REVIEW 6 of 13 amplifier in the next cycle (Q1 = Q2). Ignoring the sampling loss, the input terminal current is equal to the input current of the chopper amplifier. Thus, the differential input impedance is determined by the input parasitic capacitance of the chopper amplifier and the chopping frequency; the expression has been given as Equation (3). With the typical values Cpar = 5 fF and fCH = 20 kHz, the input impedance up to 2.5 GΩ in the signal frequency. Meanwhile, if the loop gain is infinite, VDSL is equal to EOS in Equation (7) and Vampin,dc = 0. Therefore, the DC input current is zero and the DC input impedance is infinite. In fact, the DC input impedance is higher than 170 GΩ, even in view of the limited loop gain.

Digital-Analog Hybrid DC-Servo Loop
The DC-servo loop is employed to attenuate the EOS at the output, which is actually equivalent to a low pass filter. It can be seen from Figure 1 that the noise of the DSL circuit is chopped twice. Therefore, the DSL circuit noise cannot be reduced by chopping and it directly affects the noise performance of the entire circuit. In order to analyze the noise of the DSL, the circuit can be simplified to Figure 5a, where Vn is the equivalent input-referred noise of the DSL amplifier. Since fH is much smaller than fsig.min, the impedance of the capacitor is much smaller than the impedance of the resistor. Ignoring the impedance of the capacitor as shown in Figure 5b, we can find that the output noise is equal to the input noise and it is independent of the amplifier gain. In Figure 1, the attenuator was added to reduce the noise contribution of the DSL. The behavioral level model of the DSL with attenuator is shown in Figure 6. Vn1 and Vn2 are the main sources of noise in the system, being Vn1 and Vn2 the input-referred noise sources of the chopper amplifier and the DSL, respectively. The system input noise can be expressed as:  In Figure 1, the attenuator was added to reduce the noise contribution of the DSL. The behavioral level model of the DSL with attenuator is shown in Figure 6. V n1 and V n2 are the main sources of noise in the system, being V n1 and V n2 the input-referred noise sources of the chopper amplifier and the DSL, respectively. The system input noise can be expressed as: Electronics 2019,x, x FOR PEER REVIEW 6 of 13 amplifier in the next cycle (Q1 = Q2). Ignoring the sampling loss, the input terminal current is equal to the input current of the chopper amplifier. Thus, the differential input impedance is determined by the input parasitic capacitance of the chopper amplifier and the chopping frequency; the expression has been given as Equation (3). With the typical values Cpar = 5 fF and fCH = 20 kHz, the input impedance up to 2.5 GΩ in the signal frequency. Meanwhile, if the loop gain is infinite, VDSL is equal to EOS in Equation (7) and Vampin,dc = 0. Therefore, the DC input current is zero and the DC input impedance is infinite. In fact, the DC input impedance is higher than 170 GΩ, even in view of the limited loop gain.

Digital-Analog Hybrid DC-Servo Loop
The DC-servo loop is employed to attenuate the EOS at the output, which is actually equivalent to a low pass filter. It can be seen from Figure 1 that the noise of the DSL circuit is chopped twice. Therefore, the DSL circuit noise cannot be reduced by chopping and it directly affects the noise performance of the entire circuit. In order to analyze the noise of the DSL, the circuit can be simplified to Figure 5a, where Vn is the equivalent input-referred noise of the DSL amplifier. Since fH is much smaller than fsig.min, the impedance of the capacitor is much smaller than the impedance of the resistor. Ignoring the impedance of the capacitor as shown in Figure 5b, we can find that the output noise is equal to the input noise and it is independent of the amplifier gain. In Figure 1, the attenuator was added to reduce the noise contribution of the DSL. The behavioral level model of the DSL with attenuator is shown in Figure 6. Vn1 and Vn2 are the main sources of noise in the system, being Vn1 and Vn2 the input-referred noise sources of the chopper amplifier and the DSL, respectively. The system input noise can be expressed as:   In order to minimize the noise due to the DSL, a smaller β is preferred. As an example, if β = 0.1, the total noise is reduced by 10 times, because the noise of the chopper amplifier is far less than that of the DSL. Meanwhile the noise of the DSL is independent of the gain A 2 , which can maintain the loop gain by increasing the gain of the DSL. However, since |V EOS | < βV supply , V EOS is limited to ±180 mV when β = 0.1 and V supply = 1.8 V. It is lower than the required ±300 mV. To extend V EOS without increasing noise, a digital DSL is added in Figure 7a. In order to minimize the noise due to the DSL, a smaller β is preferred. As an example, if β = 0.1, the total noise is reduced by 10 times, because the noise of the chopper amplifier is far less than that of the DSL. Meanwhile the noise of the DSL is independent of the gain A2, which can maintain the loop gain by increasing the gain of the DSL. However, since |VEOS| < βVsupply, VEOS is limited to ±180 mV when β = 0.1 and Vsupply = 1.8 V. It is lower than the required ±300 mV. To extend VEOS without increasing noise, a digital DSL is added in Figure 7a. The digital-analog hybrid DSL has two comparators to monitor the differential outputs of the low pass filter (V Lp and V Ln ). The analog compensation voltage V ADSLp and V ADSLn are obtained from V Lp and V Ln through the attenuator. When V Lp is higher than reference voltage VCM, the DAC will decrease the output voltage at the next clock. From Equations (6) and (7), V Lp will decrease when the differential outputs of the DAC decreases. Likewise, V Ln will decrease when the differential outputs of the DAC increase. In this way, when the DAC output range is ±210 mV, LSB is 70 mV and the output range of the low pass filter is bigger than 1 LSB, the EOS handling range is extended to Furthermore, the cycle time of the DAC has to longer than the settling time of the analog DSL loop. The DAC of the DSL is shown in Figure 7b. The shift register controls eight switches to encode the output voltage, and the rest module monitors the output. At the same time, M 11~M14 or M 21~M24 turn on only one, otherwise, the shift register output will be reset to 1. The working flow chart of the shift register is shown in Figure 7c.

Ripple Reduction Loop (RRL)
As shown in Figure 8, the offset of the transconductance G m1 , being chopped by MX2, appears as a square wave voltage. Then, the square wave voltage is integrated into a triangular wave to form an output ripple [13]. The RRL is used to suppress the output ripple, which consists of capacitor C 4 , chopper MX3, integrator and feedback transconductance FB 2 . This can be explained as follows. The capacitor C 4 converts the output ripple into a square wave current. This current is chopped by MX3, and the resulting DC current is integrated to generate a DC compensation voltage that can eliminate the offset of the transconductance G m1 . The digital-analog hybrid DSL has two comparators to monitor the differential outputs of the low pass filter (VLp and VLn). The analog compensation voltage VADSLp and VADSLn are obtained from VLp and VLn through the attenuator. When VLp is higher than reference voltage VCM, the DAC will decrease the output voltage at the next clock. From Equations (6) and (7), VLp will decrease when the differential outputs of the DAC decreases. Likewise, VLn will decrease when the differential outputs of the DAC increase. In this way, when the DAC output range is ±210 mV, LSB is 70 mV and the output range of the low pass filter is bigger than 1 LSB, the EOS handling range is extended to Furthermore, the cycle time of the DAC has to longer than the settling time of the analog DSL loop. The DAC of the DSL is shown in Figure 7b. The shift register controls eight switches to encode the output voltage, and the rest module monitors the output. At the same time, M11~M14 or M21~M24 turn on only one, otherwise, the shift register output will be reset to 1. The working flow chart of the shift register is shown in Figure 7c.

Ripple Reduction Loop (RRL)
As shown in Figure 8, the offset of the transconductance Gm1, being chopped by MX2, appears as a square wave voltage. Then, the square wave voltage is integrated into a triangular wave to form an output ripple [13]. The RRL is used to suppress the output ripple, which consists of capacitor C4, chopper MX3, integrator and feedback transconductance FB2. This can be explained as follows. The capacitor C4 converts the output ripple into a square wave current. This current is chopped by MX3, and the resulting DC current is integrated to generate a DC compensation voltage that can eliminate the offset of the transconductance Gm1.

Simulated Results
The proposed ECG amplifier was designed in a 0.18 µm 1P6M 1.8 V CMOS salicide process and simulated with Spectre of Cadence EDA software. The layout is shown in Figure 9. This chopping and DAC sampling frequencies are 20 kHz and 100 Hz respectively.

Simulated Results
The proposed ECG amplifier was designed in a 0.18 µm 1P6M 1.8 V CMOS salicide process and simulated with Spectre of Cadence EDA software. The layout is shown in Figure 9. This chopping and DAC sampling frequencies are 20 kHz and 100 Hz respectively. The input impedance of the ECG amplifier using different impedance-boost techniques is shown in Figure 10. This clearly shows that the proposed sampling input stage has better impedance improvement effect than aux-path technique and positive feedback (FB) technique. As described above, the DC input impedance is boosted to 120 GΩ at 0.05 Hz by the sampling input stage; at passband, the input impedance is 2.1 GΩ, which is determined by the equivalent switched-capacitor resistance of the chopper amplifier. The proposed ECG amplifier with very high input impedance characteristic can be applied to dry electrodes applications easily, which can effectively reduce the effects of signal attenuation and impedance variation interference, and its ultra-high DC impedance can reduce its input offset and DC current.  Figure 11 shows the transient waveform of the ECG amplifier with and without digital DSL. The range of EOS handling is less than ±300 mV when only use analog DSL. Its output is obviously saturated. However, the digital-analog hybrid DSL can effectively expand the EOS handling range.  The input impedance of the ECG amplifier using different impedance-boost techniques is shown in Figure 10. This clearly shows that the proposed sampling input stage has better impedance improvement effect than aux-path technique and positive feedback (FB) technique. As described above, the DC input impedance is boosted to 120 GΩ at 0.05 Hz by the sampling input stage; at pass-band, the input impedance is 2.1 GΩ, which is determined by the equivalent switched-capacitor resistance of the chopper amplifier. The proposed ECG amplifier with very high input impedance characteristic can be applied to dry electrodes applications easily, which can effectively reduce the effects of signal attenuation and impedance variation interference, and its ultra-high DC impedance can reduce its input offset and DC current. The input impedance of the ECG amplifier using different impedance-boost techniques is shown in Figure 10. This clearly shows that the proposed sampling input stage has better impedance improvement effect than aux-path technique and positive feedback (FB) technique. As described above, the DC input impedance is boosted to 120 GΩ at 0.05 Hz by the sampling input stage; at passband, the input impedance is 2.1 GΩ, which is determined by the equivalent switched-capacitor resistance of the chopper amplifier. The proposed ECG amplifier with very high input impedance characteristic can be applied to dry electrodes applications easily, which can effectively reduce the effects of signal attenuation and impedance variation interference, and its ultra-high DC impedance can reduce its input offset and DC current.  Figure 11 shows the transient waveform of the ECG amplifier with and without digital DSL. The range of EOS handling is less than ±300 mV when only use analog DSL. Its output is obviously saturated. However, the digital-analog hybrid DSL can effectively expand the EOS handling range.  Figure 11 shows the transient waveform of the ECG amplifier with and without digital DSL. The range of EOS handling is less than ±300 mV when only use analog DSL. Its output is obviously saturated. However, the digital-analog hybrid DSL can effectively expand the EOS handling range.  Figure 12 shows the input-referred noise power spectral density with and without attenuator, respectively. The results show that the system noise can be suppressed by adding an attenuator to the output of the analog DSL, and the integrated noise with attenuator on 0.6 Hz to 250 Hz is 1.9 µVrms. Figure 13 shows the AC frequency response of the ECG amplifier at different EOS. The passband gain is 46 dB, and the high-pass cut-off frequency is 0.6 Hz. Their variations are less than 1 dB and 0.4 Hz respectively when the EOS changes within ±325 mV. The very low high-pass cut-off frequency can effectively filter out ECG baseline drift and EOS interference. Figure 14 shows the Monte Carlo simulation results, which can predict the reliability of physical implementation in advance. The simulation results show that the CMRR is greater than 88 dB in 84.13 %, the gain fluctuation is less than 1 dB at the same EOS, and the input offset voltage is less than 181 µV in 95.44 %. The results show that the proposed circuit has good process stability.   Figure 12 shows the input-referred noise power spectral density with and without attenuator, respectively. The results show that the system noise can be suppressed by adding an attenuator to the output of the analog DSL, and the integrated noise with attenuator on 0.6 Hz to 250 Hz is 1.9 µVrms. Figure 13 shows the AC frequency response of the ECG amplifier at different EOS. The passband gain is 46 dB, and the high-pass cut-off frequency is 0.6 Hz. Their variations are less than 1 dB and 0.4 Hz respectively when the EOS changes within ±325 mV. The very low high-pass cut-off frequency can effectively filter out ECG baseline drift and EOS interference. Figure 14 shows the Monte Carlo simulation results, which can predict the reliability of physical implementation in advance. The simulation results show that the CMRR is greater than 88 dB in 84.13 %, the gain fluctuation is less than 1 dB at the same EOS, and the input offset voltage is less than 181 µV in 95.44 %. The results show that the proposed circuit has good process stability.  Figure 12 shows the input-referred noise power spectral density with and without attenuator, respectively. The results show that the system noise can be suppressed by adding an attenuator to the output of the analog DSL, and the integrated noise with attenuator on 0.6 Hz to 250 Hz is 1.9 µVrms. Figure 13 shows the AC frequency response of the ECG amplifier at different EOS. The passband gain is 46 dB, and the high-pass cut-off frequency is 0.6 Hz. Their variations are less than 1 dB and 0.4 Hz respectively when the EOS changes within ±325 mV. The very low high-pass cut-off frequency can effectively filter out ECG baseline drift and EOS interference. Figure 14 shows the Monte Carlo simulation results, which can predict the reliability of physical implementation in advance. The simulation results show that the CMRR is greater than 88 dB in 84.13 %, the gain fluctuation is less than 1 dB at the same EOS, and the input offset voltage is less than 181 µV in 95.44 %. The results show that the proposed circuit has good process stability.     Table 1 summarizes the main performance parameters of this work, and compares the parameters with the state-of-the-art implementations. The portable ECG and neural monitoring applications tend to implement low noise, high input impedance and low power consumption. The capacitively coupled instrumentation amplifier without chopping in [14] has very high input impedance, but its input-referred noise and power consumption are higher than chopper amplifiers in [8,12,15,16]. On the other hand, the chopper amplifier without DSL in [15], must have a large off-chip capacitor to avoid the influence of EOS. In this work, the DC input impedance (120 GΩ@0.05 Hz) and passband impedance (2.1 GΩ) are boosted significantly, while achieving the state-of-the-art EOS range and noise performance. It effectively balances the performance of input impedance, EOS range and noise.

Conclusions
This paper presents a chopper stabilized amplifier capability of wearable dry electrode ECG monitoring in the presence of large EOS and source impedance. By the chopper stabilized technology, the 1/f noise was effectively suppressed, while the noise of the DSL was suppressed obviously by the attenuator. The digital-analog hybrid DSL with sampling input stage, which feedback by the switched capacitor technology, boosted the DC input impedance up to 120 GΩ and extended the EOS handling range to ±325 mV. The high passband input impedance was achieved by the current feedback technology. The ECG amplifier only has 1.9 µVrms integrated noise from 0.6 Hz to 250 Hz, which effectively balance the performance of the input impedance, EOS range and noise. The low noise, ultra-high input impedance digital-analog hybrid offset suppression amplifier is appropriate for wearable dry electrode ECG monitoring applications.