Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel

: Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel e ﬀ ects for logic / analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary e ﬀ ect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the ﬁrst time. The proposed model was compared with the measured data and good agreements were observed.


Introduction
With growing technology, compact and faster semiconductor transistors are required. To achieve this, the channel length of a device was reduced. However, as the channel length is reduced to a nanoscale region, the performance of the scaled down devices is degraded by the short-channel effects [1,2]. To avoid short-channel effects, there have been many studies on multi-gate transistors such as FinFETs and gate-all-around (GAA) MOSFETs. The common feature of these structures is that the gate surrounds the channel. In addition, in display application, poly-silicon has a faster electron field-effect mobility speed than a-Si, TFTs using poly-silicon have been used instead of a-Si TFTs [3]. Moreover, in a memory application pursuing the rapid integration density path of the floating gate beyond 20 nm, 3D NAND device has been adopted as the next generation solution. Majority of the solutions presented recently use a deposited poly-silicon channel [4]. Meanwhile, many studies have been conducted on compact modeling of GAA MOSFETs [5][6][7] and polysilicon channel MOSFETs [8][9][10], respectively. The existing GAA MOSFETs papers considered cylindrical coordinates according to the device structure. Compact modeling was performed but using single-crystalline silicon and grain boundary effect which is represent using poly-silicon was not considered at all. Similarly, the existing poly-silicon TFTs papers considered the grain boundary effect by using poly-silicon. Although compact modeling was performed, cylindrical coordinates was not considered since the device is planar TFTs structure. However, there is only one published paper considering cylindrical coordinates and grain boundary effect. In Fei Yu's studies [11], which modeled the I-V characteristics through the Lambert-W function and some approximation techniques, the surface potential of poly-silicon GAA transistors have been studied. However, the result of the model is not intuitive to implement SPICE simulation because of the complexity of the Equation and to understand the device operation and major electrical characteristics (e.g. threshold voltage) per operating domain. This issue is most often attributed to the use of GAA's cylindrical coordinates and additional trap charge at the grain boundary in a poly-silicon channel. In this work, to solve this issue, by using proper approximations for each operating region like as D. Jimenez's work [12] we propose analytical simple drain current and threshold voltage model which can give useful and intuitive Equation for poly-Si GAA transistor.

Electrostatic Potential Modeling
We considered a doped cylindrical GAA MOSFET, as shown in Figure 1. A highly doped drain and source regions ≈ 10 20 cm −3 have been assumed. Following the gradual channel approximation and considering the cylindrical coordinates, we can express the Poisson's Equation as: where q is the electron charge, ε si is the poly-silicon permittivity, n(r) is the free carrier charge density, which is expressed as n(r) = n i exp(q(ϕ − V n )/kT), N TA − is the ionized acceptor like trap density, which is expressed as N TA and N a is the uniform doping concentration in the poly-silicon body. In this density Equation, n i is the intrinsic carrier concentration, V n is the channel potential, k is the Boltzmann constant, ϕ is the electrostatic potential, g c1 is the density of states at the conduction band energy level, E 1 is the inverse slope of states, and E c is the conduction band energy level. In addition, the localized acceptor-like states, N TA − , which are important for the n-channel device operation may be divided into two groups: 'deep localized acceptor states' and 'tail states' and E 1 is the characteristic energy slope of the density of localized acceptor states [13]. Equation (1) must satisfy three boundary conditions: where R is the radius of the channel so ϕ s is the surface potential and ϕ 0 is midpoint potential. To apply boundary conditions, Equation (1) should be rewritten using V str and V sub , which determine dominant term in Equation (1). In strong inversion region, where V gs is larger than V str , the density of free carrier charges become dominant. We define V str as (Appendix A): where V f b is the flat band voltage and t ox is the oxide thickness. Hence Equation (1) can be rewritten as Equation (1) must satisfy three boundary conditions: where R is the radius of the channel so is the surface potential and is midpoint potential. To apply boundary conditions, Equation (1) should be rewritten using and , which determine dominant term in Equation (1). In strong inversion region, where is larger than , the density of free carrier charges become dominant. We define as (appendix A): When V gs is smaller than V str , we divide the subthreshold region by defining V sub , which becomes dominant between the trap density and the ionized acceptor concentration.
When V gs < V sub , the body doping charge term becomes dominant in Equation (1). We used the term n b in Equation (6) instead of N a . As a result, Equation (1) which considered only N a term can be expressed including electrostatic potential: When V str > V gs > V sub , the trap charge term becomes dominant in Equation (1): From Equations (4), (6) and (8), we get a unified Poisson's Equation in the different operational regions as: To derive electrostatic potential, we use Debye length term and well-known mathematical solution z = A − 2 ln Br 2 + 1 , where A and B are constant . As a result, the electrostatic potential function can be expressed as [11,12]: . From Gauss's law, the following relation is satisfied: By substituting Equation (10) into Equation (11), the function about β U and V is derived: where η = 2ε si /C ox R. We can rewrite Equation (12) as substituting β U 2 /1 − β U 2 as K U . So, Equation (12) becomes following Equation (13): By using Lambert W function [14], β U can be solved.
The first term in Equation (14) is the initial solution (K U0 ). The second and third terms in Equation (14) are the correction term to improve the accuracy [15]. The second term w(y, y , y ) is expressed as w(y, y , y ) = −(y/y /(1 − 0.5yy /y /y )), where y = K U0 The third term can be calculated by y , y ). As a result, β U can be solved from Equations (10) and (11) for a given V gs . We can then obtain the electrostatic potential by substituting β U into the RHS of Equation (10). To obtain the unified electrostatic potential, we use the smoothing function [9]: where ϕ s_sub is the electric surface potential result considering the two terms, i.e., body doping and trap density in the subthreshold region. ϕ s_body and ϕ s_trap are the surface potential dominated by the body uniform doping charge and trap charge, respectively. ϕ s_ f ree is the surface potential dominated by the free carrier charges. m T is the weight parameter to connect the different asymptotical results.

Drain Current Modeling
We can obtain current Equation by using drift-diffusion current Equation I ds = µ e f f (2πR)QdV/dy. Integrating this Equation from the source to the drain and changing from the function of V to the function of β, we can get the different expression of drift-diffusion current Equation (17): where β U_S and β U_D are solved from Equation (13) corresponding to V = 0 and V = V DS respectively. Effective mobility can be defined to consider the grain boundary effect [16][17][18].
where µ 0 is the low-field mobility and θ 1 ∼ θ 10 are the fitting parameters. We can obtain ] from Equation (12). By substituting this terms to Equation (17), we can get the drain current Equation (19): Due to the difference in the current derivation method and approximation, there is a difference between the second term of Equation (19) and the current Equation in [11]. To calculate Q t , we should calculate −qg c1 [πkT/ sin(πkT/E 1 )] exp(−E c /E 1 ) exp(q(ϕ − V n )/E 1 )rdrdθ/(2πR). Instead of using this integral method, we use the trapezoid rule as: To compute the drain current at the different operation region, we define three functions of f(β), g(β) and h(β): For a given V gs and V ds , β U_S and β U_D can be calculated from Equations (12) and (21a) Following the approach of D. Jimenez [12], we can derive the analytical drain current Equation with closed-form by carefully checking the fluctuation of f(β) and β, which has different values at each operation region.
(1) Linear region above threshold In this region, f(β U_S ), f(β U_D ) 1, thus β U_S , β U_D ∼ 0. Hence, the term η/2 1 − β U_S,D (2) Saturation region In this region, f(β U_S ) 1 and f(β U_D ) −1 thus β U_S ∼ 0 and β U_D ∼ 1. Hence, the in g(β U_D ) becomes dominant, the term η/1 − β U_S in h(β U_S ) becomes dominant, and the term ln β U_D / 1 − β U_D 2 + η/(1 − β U_D ) in h(β U_D ) becomes dominant. As a result, the drain current Equation is derived as: Finally, to get the unified electrostatic potential, we use smoothing function: where I ds_ f ree , I ds_body and I ds_trap are the drain current dominated by free carriers charge, body doping charge and trap charge respectively. m v is weight parameter. As shown in the linear region, threshold voltage can be expressed as V t = V 0 − 2ηV U . If V t is written as a function of R, the following Equation (27) is obtained: Figure 2a represents the electrostatic potential from boundary conditions (Equations (2b) and (2c)). From Equation (10), the surface potential is solved by substituting r to R. Likewise, the midpoint potential is solved by substituting r to zero. Figure 2 shows that in the subthreshold region, where the gate voltage is smaller than V str , the surface potential and midpoint potential are linear as the gate voltage increases. After the subthreshold region, each potential value is saturated in the strong inversion region. Figure 2b shows the surface potential at different channel potentials. The surface potential increases as V n increases. The values of the parameters in Table 1 refer to the values extracted for the fabricated device through the actual process [11,19]. We divided the current Equation into three operation regions, as represented by Equations (22)-(24). Figure 3 shows the drain current versus drain-to-source voltage curve. This I-V curve can be drawn by using the current value of the linear region and the current value of the saturation region. As shown in Figure 3, we obtained the drain current value for different gate-to-source voltages. As the gate-to-source voltage increases, the saturation point increases and its current value increases. In addition, in this graph, we compared the GAA MOSFET devices with poly-silicon channel and the GAA MOSFET devices with single-crystalline silicon channel.

Results and Discussion
As shown in the Figure 3, devices using single-crystalline silicon channels show higher current values when compared to poly-silicon with grain boundary as expected. However, as the gate voltage increases, electrons are occupied at the trap. So the difference is smaller than when the gate voltage is low. Figure 4 shows the graph where drain current is plotted against the gate-to-source voltage for low and high drain-to-source voltages. This I-V curve can be plotted by using the current value of the subthreshold voltage region and the current value of the linear region at low drain-to-source voltages. At high drain-to-source voltages, we used the current values of the subthreshold voltage region and the saturation region. As shown in Figure 4, the high drain-to-source voltage has a larger current value than the low drain-to-source voltage because of a lower barrier region.

Conclusions
In this work, we proposed an analytical current-voltage model of GAA transistor using poly-silicon channel. The proposed model considers both GAA cylindrical coordinates and poly-silicon grain boundary trap effects. It is a channel potential-based model that calculates the potential at the center of the substrate and the surface. Using the obtained channel potentials and the D. Jimenez approach, a useful and intuitive drain current-voltage and threshold voltage model Equation are derived by taking the appropriate approximation in each transistor's operating region (linear, saturation and sub-threshold regions). The proposed model shows high consistency when compared with the measured results which is the actual performance measured by applying NH 3 plasma treatment to reduce the trap-state density on poly-silicon TFT with GAA structure. As shown in Figure A1, at specific value, density of free carrier charges over density of trap charges. We defined this crossover point as V str0 and we expressed it as function of voltage shown in the following method.
V str0 can be defined by Equation (A1).
At this point, density of free carrier charges and density of trap charges are same value. So rewrite the Poisson's Equation (1).
Integrating the Equation (A3) results: From voltage relationship Equation, V str can be written as V str = V str0 + V f b + V ox and V ox can be calculated by: Hence, substitute Equations (A2) and (A5) into voltage relationship Equation (A6):