Active Power Decoupling Design of a Single-Phase AC–DC Converter

: The second-order ripple power of single-phase converter causes second-order ripple voltages on the DC bus. For eliminating second-order ripple components, passive power decoupling methods including DC bus electrolytic capacitors have some shortcomings, such as low power density and poor stability of converters. Thus, an active power decoupling method based on a single-phase converter is proposed in this paper. The control method, taking single-phase voltage source pulse width modulation (PWM) rectiﬁer (single-phase VSR) as the basic converter and adopting a buck-boost power decoupling circuit, introduces second-order ripple of DC bus voltage into a power decoupling circuit. The ripple acts as compensation of the phase deviation between the command value and the actual value of the second-order ripple current. Therefore, estimation of the second-order ripple current is more accurate, the power decoupling circuit absorbs the second-order ripple power behind the H-bridge more completely, and the DC bus voltage ripple is e ﬀ ectively suppressed accordingly. Finally, experimental results of the single-phase VSR are given to verify the validity of the proposed method.


Introduction
Single-phase voltage source pulse width modulation (PWM) converters are widely used in uninterruptible power supply, locomotive traction, DC microgrids, and renewable energy systems because of its high efficiency and reliability [1][2][3][4][5]. However, the unbalance of instantaneous active power between DC and AC sides of the single-phase converter puts inevitable second-order components of the voltage and power on the DC bus, which endangers the operation of equipment and system [6,7]. In order to reduce the fluctuation of voltage and power on the DC side, the most common way is to install passive power decoupling systems on the DC side, such as large capacitors or LC filters. LC filter refers to a resonant branch consisting of an inductor and a capacitor in series. A reasonable parameter design will make the resonant frequency of this branch twice the power frequency. As a result, the second-order ripple power is completely transferred to the LC filter. Nevertheless, passive power decoupling systems always need large capacitors, especially in high-voltage and high-power situations. In addition, for the specific systems pursuing a high power density or lighter weight, small capacitors are preferable. Another factor is the limited lifetime of large electrolytic capacitors, which leads to reliability problems and increases maintenance costs [8][9][10]. To solve the above problems, some scholars put forward the active power decoupling method [11][12][13][14][15][16]. Active power decoupling circuits include switches and storage systems. By controlling the on/off states of switches, the conversion between the second-order ripple energy of the DC bus and the energy of storage element in the power decoupling circuit is realized. This method greatly reduces system volume and prolongs the service life of the system. Figure 1 shows the typical topology of single-phase VSR. Part I and II are the H-bridge circuit and power decoupling loop, respectively. i r represents the second-order harmonic current of the line behind the H-bridge. i rr is the input second-order ripple current of the power decoupling loop. The remaining second-order ripple current of the DC bus is represented by i rc . where Us and Is represent the amplitude of the input voltage and the input current, respectively.  is the angular frequency of the grid voltage, and  is the phase of us leading is. From Equations (1) and (2), the input power Pin is:  . (4) From Equations (3) and (4), the power Ptr transmitted to the DC bus can be expressed as:

Power Analysis of a Single-Phase Rectifier
P0 is the output power of the rectifier. Pr is the second-order ripple power (i.e., the power to be processed in part II), which can be further expressed as follows: The above deduction shows that the phase angles  and  cannot be measured directly, which is not beneficial for controlling the power decoupling loop by the expression. To this end, the two phase angles are combined to establish a reference coordinate system with is as 0 phase, as shown in Figure 2. At this time, the calculation of the power Ptr transmitted to the DC bus is as follows: When the rectifier is operating at unit power factor, the AC input current i s and the voltage u s are kept in phase. In fact, a precise unit power factor is difficult to achieve; thus, there will be a small phase difference between i s and u s . In this case, the two can be expressed as follows: (1) where U s and I s represent the amplitude of the input voltage and the input current, respectively. ω is the angular frequency of the grid voltage, and β is the phase of u s leading i s . From Equations (1) and (2), the input power P in is: According to Equation (2), the voltage drop u L on the inductor L s is: From Equations (3) and (4), the power P tr transmitted to the DC bus can be expressed as: Equation (5) shows that P tr consists of two parts: constant power P o and second-order ripple power P r , which are expressed, respectively, as follows: P 0 is the output power of the rectifier. P r is the second-order ripple power (i.e., the power to be processed in part II), which can be further expressed as follows: The above deduction shows that the phase angles β and ψ cannot be measured directly, which is not beneficial for controlling the power decoupling loop by the expression. To this end, the two phase angles are combined to establish a reference coordinate system with i s as 0 phase, as shown in Figure 2. At this time, the calculation of the power P tr transmitted to the DC bus is as follows: In Equation (10), uab is the voltage of the ab bridge arm. ϕ is the phase of is ahead of uab. If the power decoupling circuit is not added, the second-order ripple power in the circuit is completely absorbed by the DC bus capacitors. As shown in Figure 2, the energy ΔE of the bus capacitor C filled in the period from ϕ/2ω to t is as follows: At the same time, the energy change of capacitor in this period ΔEc is as follows: where udc is the DC bus voltage and Udc is its DC component. Ignoring the power loss in the circuit, Equations (11) and (12) should be equal; thus, the DC bus voltage is as follows: Applying Taylor's formula to Equation (13), the results are approximately as follows: From Equation (14), there is a second-order component in DC bus voltage. Refer to Equation (11) to calculate the capacitance C during ϕ/2ω +π/4ω to ϕ/2ω +3π/4ω period: In Equation (15), ΔUmax is the maximum value of the DC bus voltage ripple. Considering the reliability of the power supply and normal operation of the equipment, the DC bus voltage ripple should be within the prescribed range, generally not more than 10%. If C is selected by Equation (15), a capacitor with larger capacitance value is needed to suppress the second-order ripple effectively. As a result, the buck-boost-type active power decoupling circuit is selected to absorb the secondorder harmonic power on the DC side. In Equation (10), u ab is the voltage of the ab bridge arm. ϕ is the phase of i s ahead of u ab . If the power decoupling circuit is not added, the second-order ripple power in the circuit is completely absorbed by the DC bus capacitors. As shown in Figure 2, the energy ∆E of the bus capacitor C filled in the period from ϕ/2ω to t is as follows:

Analysis of an Active Power Decoupling Circuit
At the same time, the energy change of capacitor in this period ∆E c is as follows: where u dc is the DC bus voltage and U dc is its DC component. Ignoring the power loss in the circuit, Equations (11) and (12) should be equal; thus, the DC bus voltage is as follows: Applying Taylor's formula to Equation (13), the results are approximately as follows: From Equation (14), there is a second-order component in DC bus voltage. Refer to Equation (11) to calculate the capacitance C during ϕ/2ω +π/4ω to ϕ/2ω +3π/4ω period: In Equation (15), ∆U max is the maximum value of the DC bus voltage ripple. Considering the reliability of the power supply and normal operation of the equipment, the DC bus voltage ripple should be within the prescribed range, generally not more than 10%. If C is selected by Equation (15), a capacitor with larger capacitance value is needed to suppress the second-order ripple effectively. As a result, the buck-boost-type active power decoupling circuit is selected to absorb the second-order harmonic power on the DC side.

Analysis of an Active Power Decoupling Circuit
In this paper, a buck-boost-type power decoupling circuit is adopted [33]. Similarly, bidirectional buck-boost circuits can be used for power decoupling, such as the decoupling circuits in reference [27,32]. The characteristics of the three circuits are compared in Table 1, where d is the duty cycle of the bidirectional decoupling circuit. As shown in the table, the voltage stress and current stress of the buck-boost-type decoupling topology are not dominant. However, the choice of decoupling capacitance and capacitor voltage is more flexible, which will bring broad application prospects. Assuming that the second-order ripple power is constant, if the DC bus voltage is high, in order to avoid excessive voltage stress on the power device, a decoupling capacitor voltage lower than the DC bus voltage can be selected. From Equation (14), the ripple of the capacitor voltage is large at this time. In addition, if the voltage across the decoupling capacitor is high, the capacitance can be selected to be very small, thereby achieving an increase in power density. As a result, a buck-boost-type power decoupling circuit was selected in this paper. The buck-boost-type power decoupling topology is shown in Figure 3a, in which capacitance acts as the energy storage element, while inductance acts as the energy transmission element. When the instantaneous power of the AC side is larger than that of DC side, that is, when the power decoupling circuit is in the charging mode (hereinafter referred to as charging mode), the switching modes of CCM are shown in Figure 3b. i r denotes the second-order ripple current processed in each switching cycle, i L denotes the instantaneous value of the inductor current in the decoupling loop, and v Q1 represents the voltage stress sustained by Q 1 . During t 0 -t 1 period, Q 1 is on, and the pulsating power is transferred to the inductor. During the period from t 1 to t 2 , Q 1 is off, and the pulsating power flows through diode D 2 to transfer energy to the capacitor.
Similarly, when the instantaneous power of the AC side is less than that of DC side, that is, when the power decoupling circuit is in discharging mode (hereinafter referred to as discharging mode), Q 2 is on, and the pulsating power is transferred to the inductor. When Q 2 is turned off, the pulsating power flows through the diode D 1 , and the energy is transmitted to the DC side. and vQ1 represents the voltage stress sustained by Q1. During t0-t1 period, Q1 is on, and the pulsating power is transferred to the inductor. During the period from t1 to t2, Q1 is off, and the pulsating power flows through diode D2 to transfer energy to the capacitor.
Similarly, when the instantaneous power of the AC side is less than that of DC side, that is, when the power decoupling circuit is in discharging mode (hereinafter referred to as discharging mode), Q2 is on, and the pulsating power is transferred to the inductor. When Q2 is turned off, the pulsating power flows through the diode D1, and the energy is transmitted to the DC side.

Control System Design
In order to eliminate the second-order ripple power on the DC bus, the precondition is to accurately obtain ir in Figure 1. If irr is controlled to equal ir, the DC bus voltage will be constant. Generally, there are two methods to obtain the second-order ripple current [32,33]. The first method is to sample ir directly and get its second-order component through the second-order resonant controller [33]. However, since the change of zero and nonzero values of pulsating current are consistent with the switching frequency, a higher sampling frequency is required. Only in this case can the signal be undistorted. It greatly increases the difficulty of the system's hardware design. As a result, this paper selected the second method, which is to estimate ir by other variables in the circuit.
Ideally, the second-order ripple energy needs to be fully absorbed by the power decoupling circuit. According to Equation (10), the output power Ptro is as follows: where Idc is the DC component of the load current on the DC side. The second-order harmonic power Ptrr is: Combining Equations (16) and (17), ir is obtained as follows: ( ) ω ϕ ϕ = − − dc r cos 2 cos From Figure 3, the second-order ripple current iL on the inductor of the decoupling circuit is: where d is the duty cycle of Q1 in the buck-boost circuit. According to the control method in [30,31], the command value iLc is set to:

Control System Design
In order to eliminate the second-order ripple power on the DC bus, the precondition is to accurately obtain i r in Figure 1. If i rr is controlled to equal i r , the DC bus voltage will be constant. Generally, there are two methods to obtain the second-order ripple current [32,33]. The first method is to sample i r directly and get its second-order component through the second-order resonant controller [33]. However, since the change of zero and nonzero values of pulsating current are consistent with the switching frequency, a higher sampling frequency is required. Only in this case can the signal be undistorted. It greatly increases the difficulty of the system's hardware design. As a result, this paper selected the second method, which is to estimate i r by other variables in the circuit.
Ideally, the second-order ripple energy needs to be fully absorbed by the power decoupling circuit. According to Equation (10), the output power P tro is as follows: where I dc is the DC component of the load current on the DC side. The second-order harmonic power P trr is: Combining Equations (16) and (17), i r is obtained as follows: From Figure 3, the second-order ripple current i L on the inductor of the decoupling circuit is: where d is the duty cycle of Q 1 in the buck-boost circuit. According to the control method in [30,31], the command value i Lc is set to: The duty cycle d in Equation (20) is calculated by the DC component of DC bus voltage u dc and decoupling capacitor voltage u z . Figure 4 shows the control block diagram of the power decoupling circuit. From Equation (20), part 1 in Figure 4 can be obtained. This command value is only an approximation of i r . Since the phase difference ϕ is ignored, there is a deviation between the command value i Lc and the actual value i L . To this end, this paper introduced DC bus voltage u dc to participate in the estimation of i r . udc (i.e., ur). Because most of the second-order ripple energy in the circuit is absorbed by the power decoupling circuit, according to Equation (14), the second-order ripple component of the DC bus voltage can be expressed as: Referring to Equations (11) and (14), E´ represents a value proportional to the second-order ripple energy of the DC bus. It is a constant to characterize ur. Equation (21)   Equation (22) shows that the DC bus capacitor is also considered as the load, and  is the impedance angle of the RC load. Expressing the command values iLc and ur by phasors gives: Equation (23) can be rewritten as: Plotting the phasor form of the above variables in a vector diagram is shown in Figure 5. The figure will present the function of udc in the control circuit more intuitively. There is a phase difference between the command value iLc and the actual inductor current iL. Since the output amplitude of ur is small, if ur is superimposed on iLc, the estimated command value of the second-order current is The function of DC bus voltage in the power decoupling circuit is shown in part 2 in Figure 4. Res represents the second-order resonant controller, which extracts the second-order component of u dc (i.e., u r ). Because most of the second-order ripple energy in the circuit is absorbed by the power decoupling circuit, according to Equation (14), the second-order ripple component of the DC bus voltage can be expressed as: Referring to Equations (11) and (14), E´represents a value proportional to the second-order ripple energy of the DC bus. It is a constant to characterize u r . Equation (21) is based on the fact that the second-order ripple component of the DC side is completely absorbed by the DC bus capacitor (i.e., the ripple current does not flow through the output). In fact, this condition is only valid when the DC bus capacitance is large enough. However, after the power decoupling circuit is added, the DC bus capacitance decreases, and the second-order ripple component also exists in the load current. At this time, the second-order component of the DC bus voltage should be expressed as: Equation (22) shows that the DC bus capacitor is also considered as the load, and θ is the impedance angle of the RC load. Expressing the command values i Lc and u r by phasors gives: Equation (23) can be rewritten as: Plotting the phasor form of the above variables in a vector diagram is shown in Figure 5. The figure will present the function of u dc in the control circuit more intuitively. There is a phase difference between the command value i Lc and the actual inductor current i L . Since the output amplitude of u r is small, if u r is superimposed on i Lc , the estimated command value of the second-order current is basically unchanged. Moreover, the superimposed phase approaches the phase of i r . As a result, the control of the second-order ripple absorption is more accurate. basically unchanged. Moreover, the superimposed phase approaches the phase of ir. As a result, the control of the second-order ripple absorption is more accurate. At the same time, this method is highly applicable because the phase can be compensated in four quadrants. The phasors in the first and second quadrants are shown in Figure 5. The same applies to the third and fourth quadrants. Part 3 in Figure 4 shows the control of uz. LP represents the low-pass filter, which extracts the DC component of uz. The superposition of part 1, part 2, and part 3 serves as the given value of iL.

Inductance Design of the Power Decoupling Circuit
The inductance of the power decoupling circuit was designed in CCM. In charging mode, the following can be seen from Figure 3b: When Q1 is on, the inductor charges: At the same time, this method is highly applicable because the phase can be compensated in four quadrants. The phasors in the first and second quadrants are shown in Figure 5. The same applies to the third and fourth quadrants.
Part 3 in Figure 4 shows the control of u z . LP represents the low-pass filter, which extracts the DC component of u z . The superposition of part 1, part 2, and part 3 serves as the given value of i L .

Inductance Design of the Power Decoupling Circuit
The inductance of the power decoupling circuit was designed in CCM. In charging mode, the following can be seen from Figure 3b: When Q 1 is on, the inductor charges: where K 1 indicates the rise rate of the inductor current during charging. When Q 1 is off, the inductor discharges: where K 2 represents the drop rate of the inductor current during discharging. In this process, the second-order ripple energy is transferred to the inductor and then to the capacitor. Ignoring the energy storage on the inductor in a switching period, that is, the second-order ripple energy injected into the inductor is approximately equal to the average value of second-order ripple energy processed by decoupling loop in a switching period: where T 1 indicates the time when Q 1 is turned on in one switching cycle, and T represents one switching period. Combining Equations (27) and (28) with (29), the duty cycle d c of Q 1 is: where f r is the switching frequency of power decoupling circuit, which is equal to the switching frequency of rectifier circuit in this paper. Similarly, in a switching cycle, the second-order ripple energy flowing from the inductor is approximately equal to the average value of second-order ripple energy processed by the decoupling loop. As a result, the duty cycle d d of Q 2 is: At the peak current of the inductor, the current ripple is the largest. Thus, the peak current value of the inductor is taken to calculate the minimum value of the required inductance. From Equation (20), the peak value i Lmax of the inductor current is approximately as follows: Since the current only plays the role of energy transmission, the ripple index is not strictly required; therefore, the ripple is calculated by 1.5 times.
According to the given ripple index, when Q 1 is on or off, L must be met respectively: The range of L is obtained as follows: Moreover, the peak current ripple value of the inductor should be less than the maximum value I p allowed to flow through the inductor. When the average current value of the inductor reaches i Lmax in a switching cycle, L is calculated as follows: The range of L is obtained as follows: The calculation of inductance selection in discharging mode is the same. By Equations (27)-(38), the selection of inductance should follow: That is, the selected inductance L should be greater than the maximum values of L 1 and L 2 .

Capacitance Design of the Power Decoupling Circuit
From Equation (15), the selection of capacitance in the decoupling circuit is related to the average value and the ripple of decoupling capacitor voltage. Therefore, the maximum value of capacitor voltage ripple ∆U zmax is obtained: In order to ensure the continuity of capacitor voltage and normal operation of the decoupling circuit, the following conditions should be satisfied: A combination of Equations (40) and (41) can be further expressed as: The relationship of capacitance, capacitor voltage. and output power is plotted in Figure 6 based on Equation (42). From the figure, if the capacitance C z is larger, the capacitor voltage u z can be made smaller; thus, the voltage stress of the decoupling loop can be reduced. If u z is higher, C z can be reduced accordingly. If the output power increases, C z needs to increase to maintain effective operation.
The relationship of capacitance, capacitor voltage. and output power is plotted in Figure 6 based on Equation (42). From the figure, if the capacitance Cz is larger, the capacitor voltage uz can be made smaller; thus, the voltage stress of the decoupling loop can be reduced. If uz is higher, Cz can be reduced accordingly. If the output power increases, Cz needs to increase to maintain effective operation.

Simulation Verification
In order to verify the feasibility of the control method, two sets of simulation models were built for comparison. The first group adopted the control method in [30,31]. This method estimated i r without phase compensation, and the power decoupling circuit was in CCM, which is called the estimation method for short. The second group adopted the control method proposed in this paper. The two sets of control methods were based on the same rectifier and power decoupling topology. Their simulation parameters are shown in Table 2. The steady-state simulation waveforms of the estimation method and the proposed method are compared. Under the estimation method, the simulation waveforms before and after the power decoupling loop was connected are shown in Figure 7a. Before 1 s, the power decoupling circuit was not connected. At this time, the second-order ripple energy in the system was all processed by the DC bus capacitor. From the figure, the peak-to-peak value of the voltage ripple reached 57 V, the capacitor voltage and inductor current in the decoupling circuit were both 0 V. After the power decoupling circuit was connected at 1 s, the circuit gradually restored to steady state. The fluctuation of DC bus voltage was greatly reduced compared with that before 1 s, but the DC bus voltage still had a ripple of 27 V.
Under the proposed method, the simulation waveforms before and after the power decoupling circuit was connected are shown in Figure 7b. The power decoupling circuit was also connected at 1 s. After the system was stable, the DC bus voltage ripple was 10 V, which was 17 V less than that in the estimation method. It can be seen that the DC bus voltage ripple was smaller, and the second-order ripple power processing was more effective by the proposed method. Although 150 µF capacitance was introduced into the circuit, if the power decoupling circuit was not connected, a DC bus capacitance C of 1400 µF was needed to achieve the same effect. The waveforms of the power decoupling circuit in two ripple periods are shown in Figure 7c. The average voltage of the decoupling capacitor C z was stable at 150 V; the voltage ripple was 74 V. In the charging mode, the average value of the inductor current was greater than 0 in each switching cycle; thus, the capacitor voltage u z rose. The waveform in the discharging mode was similar. The control method was validated by simulation.

Experiment Verification
Similar to simulations, two groups of experiments were carried out based on the same experimental prototype. Figure 8 is a picture of the prototype, the parameters of which are selected as in Table 2. The experiment waveforms without a power decoupling circuit are shown in Figure 9. When the power decoupling loop was not connected, the DC bus capacitor was selected to be 250 µF, which is the sum of the DC bus capacitor C and the decoupling capacitor C z in Table 2. As the figure shows, the voltage and current were in phase, but the voltage fluctuated greatly, and the ripple reached 56 V. A large harmonic component was introduced into the AC input current; thus, the inductor's current waveform was not ideal.

Experiment Verification
Similar to simulations, two groups of experiments were carried out based on the same experimental prototype. Figure 8 is a picture of the prototype, the parameters of which are selected as in Table 2. The experiment waveforms without a power decoupling circuit are shown in Figure 9. When the power decoupling loop was not connected, the DC bus capacitor was selected to be 250 μF, which is the sum of the DC bus capacitor C and the decoupling capacitor Cz in Table 2. As the figure When the power decoupling circuit was connected, the experiment waveforms obtained by the estimation method and the proposed method are shown in Figure 10. The average voltage of the decoupling capacitor Cz was 150 V. As shown in Figure 10a, the voltage ripple obtained by the estimation method was 34 V, which was 11% less than that without the power decoupling loop. Eleven percent represents the ripple ratio of the DC bus voltage; it was derived from the formula: ΔUmax/Udc*×100%. It was proved that this method was effective for second-order ripple power absorption, but the calculation was not accurate enough; thus, the second-order ripple content of the DC bus voltage was still large. As shown in Figure 10b, the voltage ripple of the bus obtained by the proposed method was 13 V within the prescribed range of 10%, which was 20% less than that without the power decoupling loop. Thus, the validity of the proposed control method was verified. The capacitor voltage ripple of the decoupling loop was 90 V, and the inductor current presented a second-order sinusoidal curve with a peak value approximating 6.2 A, which was basically consistent with the simulation results.   When the power decoupling circuit was connected, the experiment waveforms obtained by the estimation method and the proposed method are shown in Figure 10. The average voltage of the decoupling capacitor Cz was 150 V. As shown in Figure 10a, the voltage ripple obtained by the estimation method was 34 V, which was 11% less than that without the power decoupling loop. Eleven percent represents the ripple ratio of the DC bus voltage; it was derived from the formula: ΔUmax/Udc*×100%. It was proved that this method was effective for second-order ripple power absorption, but the calculation was not accurate enough; thus, the second-order ripple content of the DC bus voltage was still large. As shown in Figure 10b, the voltage ripple of the bus obtained by the proposed method was 13 V within the prescribed range of 10%, which was 20% less than that without the power decoupling loop. Thus, the validity of the proposed control method was verified. The capacitor voltage ripple of the decoupling loop was 90 V, and the inductor current presented a second-order sinusoidal curve with a peak value approximating 6.2 A, which was basically consistent with the simulation results.

200V 56V
10ms/div Figure 9. Experiment waveforms of input voltage us, input current is, and output voltage udc without the power decoupling circuit. When the power decoupling circuit was connected, the experiment waveforms obtained by the estimation method and the proposed method are shown in Figure 10. The average voltage of the decoupling capacitor C z was 150 V. As shown in Figure 10a, the voltage ripple obtained by the estimation method was 34 V, which was 11% less than that without the power decoupling loop. Eleven percent represents the ripple ratio of the DC bus voltage; it was derived from the formula: ∆U max /U dc *×100%. It was proved that this method was effective for second-order ripple power absorption, but the calculation was not accurate enough; thus, the second-order ripple content of the DC bus voltage was still large. As shown in Figure 10b, the voltage ripple of the bus obtained by the proposed method was 13 V within the prescribed range of 10%, which was 20% less than that without the power decoupling loop. Thus, the validity of the proposed control method was verified. The capacitor voltage ripple of the decoupling loop was 90 V, and the inductor current presented a second-order sinusoidal curve with a peak value approximating 6.2 A, which was basically consistent with the simulation results.
Experiment waveforms of the ripple of i L and the ripple of u dc in each switching cycle are shown in Figure 11. Because of the time axis of the oscilloscope, u dc was approximately constant over the field of view. L was charged and discharged in each switching cycle with the opening and closing of Q 1 . 10ms/div Figure 9. Experiment waveforms of input voltage us, input current is, and output voltage udc without the power decoupling circuit. Experiment waveforms of the ripple of iL and the ripple of udc in each switching cycle are shown in Figure 11. Because of the time axis of the oscilloscope, udc was approximately constant over the field of view. L was charged and discharged in each switching cycle with the opening and closing of Q1.
At this time, the operation of the whole system is observed. The experiment waveforms of the input voltage, input current, and output voltage are shown in Figure 12 by the proposed method. As shown in the figure, the input voltage and current were approximately in phase. The input current had a higher sinusoidal degree and a lower harmonic content, which was notably better than that without power decoupling, as shown in Figure 9. As a result, the goal of power decoupling is achieved. Experiment waveforms of the ripple of iL and the ripple of udc in each switching cycle are shown in Figure 11. Because of the time axis of the oscilloscope, udc was approximately constant over the field of view. L was charged and discharged in each switching cycle with the opening and closing of Q1.
At this time, the operation of the whole system is observed. The experiment waveforms of the input voltage, input current, and output voltage are shown in Figure 12 by the proposed method. As shown in the figure, the input voltage and current were approximately in phase. The input current had a higher sinusoidal degree and a lower harmonic content, which was notably better than that without power decoupling, as shown in Figure 9. As a result, the goal of power decoupling is achieved. At this time, the operation of the whole system is observed. The experiment waveforms of the input voltage, input current, and output voltage are shown in Figure 12 by the proposed method. As shown in the figure, the input voltage and current were approximately in phase. The input current had a higher sinusoidal degree and a lower harmonic content, which was notably better than that without power decoupling, as shown in Figure 9. As a result, the goal of power decoupling is achieved. Taking full advantage of the buck-boost circuit's step-up and step-down advantages, the capacitor voltage uz of the decoupling circuit can be controlled to be higher than that of the DC bus, with an average value of 250 V instead of the average value of 150 V above. Figure 13 shows the experiment waveforms of the proposed method under this voltage level. As shown in the figure, the bus voltage ripple was 14 V within the prescribed range of 10%. The capacitor voltage ripple of the decoupling circuit was 65 V, which is smaller than that when the average value of uz was 150 V. Therefore, under the condition of maintaining the same DC bus voltage ripple, if the capacitor voltage uz of the decoupling loop is increased, the voltage ripple will be reduced. The capacitance Cz can be taken to a smaller value accordingly. In order to verify the good dynamic characteristics of the system, a load switching experiment was carried out. Figure 14a shows the experiment waveforms when the full load was switched to 75% load and then switched to full load. The 75 % load indicated that the output power was 75% of the rated power. Figure 14b,c shows the experiment waveforms in load reduction and load increase, respectively. It can be seen that the rise and fall of voltage did not exceed 10 V, and the response time was short. Within 0.1 s after load switching, the system reached steady-state quickly, indicating that the system has good dynamic performance during load switching. Taking full advantage of the buck-boost circuit's step-up and step-down advantages, the capacitor voltage u z of the decoupling circuit can be controlled to be higher than that of the DC bus, with an average value of 250 V instead of the average value of 150 V above. Figure 13 shows the experiment waveforms of the proposed method under this voltage level. As shown in the figure, the bus voltage ripple was 14 V within the prescribed range of 10%. The capacitor voltage ripple of the decoupling circuit was 65 V, which is smaller than that when the average value of u z was 150 V. Therefore, under the condition of maintaining the same DC bus voltage ripple, if the capacitor voltage u z of the decoupling loop is increased, the voltage ripple will be reduced. The capacitance C z can be taken to a smaller value accordingly. Taking full advantage of the buck-boost circuit's step-up and step-down advantages, the capacitor voltage uz of the decoupling circuit can be controlled to be higher than that of the DC bus, with an average value of 250 V instead of the average value of 150 V above. Figure 13 shows the experiment waveforms of the proposed method under this voltage level. As shown in the figure, the bus voltage ripple was 14 V within the prescribed range of 10%. The capacitor voltage ripple of the decoupling circuit was 65 V, which is smaller than that when the average value of uz was 150 V. Therefore, under the condition of maintaining the same DC bus voltage ripple, if the capacitor voltage uz of the decoupling loop is increased, the voltage ripple will be reduced. The capacitance Cz can be taken to a smaller value accordingly. In order to verify the good dynamic characteristics of the system, a load switching experiment was carried out. Figure 14a shows the experiment waveforms when the full load was switched to 75% load and then switched to full load. The 75 % load indicated that the output power was 75% of the rated power. Figure 14b,c shows the experiment waveforms in load reduction and load increase, respectively. It can be seen that the rise and fall of voltage did not exceed 10 V, and the response time was short. Within 0.1 s after load switching, the system reached steady-state quickly, indicating that the system has good dynamic performance during load switching. In order to verify the good dynamic characteristics of the system, a load switching experiment was carried out. Figure 14a shows the experiment waveforms when the full load was switched to 75% load and then switched to full load. The 75 % load indicated that the output power was 75% of the rated power. Figure 14b,c shows the experiment waveforms in load reduction and load increase, respectively. It can be seen that the rise and fall of voltage did not exceed 10 V, and the response time was short. Within 0.1 s after load switching, the system reached steady-state quickly, indicating that the system has good dynamic performance during load switching. 75% load and then switched to full load. The 75 % load indicated that the output power was 75% of the rated power. Figure 14b,c shows the experiment waveforms in load reduction and load increase, respectively. It can be seen that the rise and fall of voltage did not exceed 10 V, and the response time was short. Within 0.1 s after load switching, the system reached steady-state quickly, indicating that the system has good dynamic performance during load switching.

Conclusions
Based on buck-boost-type power decoupling circuit of the single-phase VSR, an independent power decoupling control strategy with second-order ripple current estimation was proposed in this paper. The second-order ripple component of the DC bus voltage was introduced in the control, which compensated the phase deviation between the command value and the actual value of the second-order ripple current. Thus, the power decoupling circuit can effectively absorb the secondorder ripple power, and the DC bus voltage ripple is controlled within the allowable range. Finally, an experimental prototype of 533 W rated power was built for the experiment. With the proposed control method, the DC bus voltage ripple was controlled within 7% in steady state, the voltage overshoot was not more than 10 V in load switching, and the transition time was not more than 0.2 s, which verifies the effectiveness of the control method with a good dynamic response and stable characteristics.

Conclusions
Based on buck-boost-type power decoupling circuit of the single-phase VSR, an independent power decoupling control strategy with second-order ripple current estimation was proposed in this paper. The second-order ripple component of the DC bus voltage was introduced in the control, which compensated the phase deviation between the command value and the actual value of the second-order ripple current. Thus, the power decoupling circuit can effectively absorb the second-order ripple power, and the DC bus voltage ripple is controlled within the allowable range. Finally, an experimental prototype of 533 W rated power was built for the experiment. With the proposed control method, the DC bus voltage ripple was controlled within 7% in steady state, the voltage overshoot was not more than 10 V in load switching, and the transition time was not more than 0.2 s, which verifies the effectiveness of the control method with a good dynamic response and stable characteristics.