A High-Accuracy Ultra-Low-Power Offset-Cancelation On-Off Bandgap Reference for Implantable Medical Electronics

: An ultra-low-power and high-accuracy on-o ﬀ bandgap reference (BGR) is demonstrated in this paper for implantable medical electronics. The proposed BGR shows an average current consumption of 78 nA under 2.8 V supply and an output voltage of 1.17 V with an untrimmed accuracy of 0.69%. The on-o ﬀ bandgap combined with sample-and-hold switched-RC ﬁlter is developed to reduce power consumption and noise. The on-o ﬀ mechanism allows a relatively higher current in the sample phase to alleviate the process variation of bipolar transistors. To compensate the error caused by operational ampliﬁer o ﬀ set, the correlated double sampling strategy is adopted in the BGR. The proposed BGR is implemented in 0.35 µ m standard CMOS process and occupies a total area of 0.063 mm 2 . Measurement results show that the circuit works properly in the supply voltage range of 1.8–3.2 V and achieves a line regulation of 0.59 mV / V. When the temperature varies from − 20 to 80 ◦ C, an average temperature coe ﬃ cient of 19.6 ppm / ◦ C is achieved.


Introduction
Along with the continuous development of modern society and growing demand for high-quality life, implantable medical electronics are increasingly adopted in healthcare medical devices such as cardiac pacemakers [1][2][3]. These devices are usually battery powered and need to have ultra-low power consumption of a few microwatts or less [4][5][6][7][8]. Since they would probably be placed where they are not easily removed or recharged, they have to continue working for a relatively long time. A number of important analog circuits for high-precision signal processing, such as voltage regulators, analog to digital converters (ADCs) and digital to analog converters (DACs), are used in almost every biomedical system. All of them demand an accurate bandgap reference (BGR) [9]. In these devices, BGRs provide the voltage references for other important functional blocks and are supposed to be working all the time. Thus, the required average current dissipation of BGR is in the range of several tens of nano-ampere [10][11][12].
To meet the requirement for low power, subthreshold voltage references without bipolar transistors have been developed and used widely [10][11][12]. However, these V TH -based references often suffer from degraded performance in accuracy since the threshold voltage (V TH ) of MOSFET changes too much (about 50-100mV) with process variation. Trimming is usually employed to solve this issue. However, the temperature coefficient would be worse after trimming [12]. A conventional bipolar junction transistor (BJT)-based BGR can provide a fairly precise reference voltage, but it requests larger power consumption. When we try to budget a lower current consumption for BJT-based BGR, resistors with very large values are needed, and the V BE of BJT also varies dramatically. V BE variation introduces large fluctuations to the output reference voltage. Even for relatively larger budgeted power consumption, trimming is still generally required for BJT-based BGR because of the existence of mismatch and offset [13].
In this paper, an ultra-low power, high accuracy BGR is presented. The proposed reference provides a 1.17 V output under 2.8 V supply voltage with 78 nA average current consumption. An on-off bandgap combined with sample-and-hold switched-RC filter is developed to reduce power consumption and noise. The on-off mechanism increases the working current of the BJT-based BGR during the sample period, which decreases V BE spread. A correlated double sampling (CDS) strategy is adopted to cancel the offset of the operational amplifier (Opamp), which is fulfilled by a sampling capacitor block combined with chopper mechanism. The conflict between low power and high accuracy is preliminarily settled. The theoretical foundation and specific circuit design are described in Section 2. Section 3 presents the simulation and measurement results as well as a performance comparison. Finally, conclusions are summarized in Section 4.

Error Analysis of the BJT-Based BGR
The key point of this paper is to utilize the techniques of offset cancelling, correlated double sampling and switched-RC to improve the accuracy of the raw BGRs under stringent power consumption constraints. A conventional BJT-based BGR is employed here for demonstration. The core circuit of the BJT-based BGR is shown in Figure 1. The reference voltage generated by it is given by: When considering non-ideal factors relevant with V BE and Opamp offset, Equation (1) can be approximately rewritten as where the superscript denotes the erroneous quantity. High mismatch characteristic of MOS transistors can introduce considerate offsets to Opamp especially under extreme low power consumption. The V BE spread is also critical because it directly translates an error in V REF . The proposed circuit concentrates on canceling these two sources of errors which have large magnitudes of effects on the accuracy of BGR output voltage. junction transistor (BJT)-based BGR can provide a fairly precise reference voltage, but it requests larger power consumption. When we try to budget a lower current consumption for BJT-based BGR, resistors with very large values are needed, and the VBE of BJT also varies dramatically. VBE variation introduces large fluctuations to the output reference voltage. Even for relatively larger budgeted power consumption, trimming is still generally required for BJT-based BGR because of the existence of mismatch and offset [13]. In this paper, an ultra-low power, high accuracy BGR is presented. The proposed reference provides a 1.17 V output under 2.8 V supply voltage with 78 nA average current consumption. An on-off bandgap combined with sample-and-hold switched-RC filter is developed to reduce power consumption and noise. The on-off mechanism increases the working current of the BJT-based BGR during the sample period, which decreases VBE spread. A correlated double sampling (CDS) strategy is adopted to cancel the offset of the operational amplifier (Opamp), which is fulfilled by a sampling capacitor block combined with chopper mechanism. The conflict between low power and high accuracy is preliminarily settled. The theoretical foundation and specific circuit design are described in Section II. Section III presents the simulation and measurement results as well as a performance comparison. Finally, conclusions are summarized in Section IV. The key point of this paper is to utilize the techniques of offset cancelling, correlated double sampling and switched-RC to improve the accuracy of the raw BGRs under stringent power consumption constraints. A conventional BJT-based BGR is employed here for demonstration. The core circuit of the BJT-based BGR is shown in Figure 1. The reference voltage generated by it is given by:

Architecture of the Proposed BGR Circuit
The systematic architecture of the proposed BGR is shown in Figure 2, which consists of an on-off V BE -based BGR with chopper mechanism, a sampling-capacitor block, and a sample-and-hold switched-RC filter. Also, there is a digital block to generate the low-duty-cycle clocks used in the on-off BGR, which is manually designed as the analog circuits to reduce the turnover rate of the clocks and thus save power. The on-off BGR takes advantages of the conventional V BE -based BGR topology. When consuming dozens of microampere (µA), the conventional V BE -based BGR operates reliably and has little process variation spread. During the hold period, the on-off BGR is turned off to save power. The sampling-capacitor block is based on the technique of correlated double sampling (CDS), which samples twice in a working (on) period, before and after the conversion of the chopper connection state in the on-off BGR, respectively. Therefore, the offset of the Opamp V os is cancelled out. When the BGR block entered the off state, the switched-RC filter takes the average of the last twice sampled voltages, holds it until next working (on) state, and gets rid of the out-of-band noise through the function of filtering.

Architecture of the Proposed BGR Circuit
The systematic architecture of the proposed BGR is shown in Figure 2, which consists of an onoff VBE-based BGR with chopper mechanism, a sampling-capacitor block, and a sample-and-hold switched-RC filter. Also, there is a digital block to generate the low-duty-cycle clocks used in the onoff BGR, which is manually designed as the analog circuits to reduce the turnover rate of the clocks and thus save power. The on-off BGR takes advantages of the conventional VBE-based BGR topology. When consuming dozens of microampere (μA), the conventional VBE-based BGR operates reliably and has little process variation spread. During the hold period, the on-off BGR is turned off to save power. The sampling-capacitor block is based on the technique of correlated double sampling (CDS), which samples twice in a working (on) period, before and after the conversion of the chopper connection state in the on-off BGR, respectively. Therefore, the offset of the Opamp Vos is cancelled out. When the BGR block entered the off state, the switched-RC filter takes the average of the last twice sampled voltages, holds it until next working (on) state, and gets rid of the out-of-band noise through the function of filtering.  Figure 3 shows the implementation of the on-off BGR which employs chopper mechanism. A near-zero power consumption start-up structure is adopted. The parameter values of the main components in the BGR core circuit are as follows. The emitter area of Q1 and Q2 is 2 × 2 μm. R1 = 10 kΩ and R2 = 80 kΩ. The size of MP1/2 is 8 μm/16 μm × 6 while the size of the switch transistors is 4μm/1μm × 1. The sizes of the transistors are designed to be large for good matching and low flicker noise. Considering the low speed characteristic of the designed circuit, the lengths of the transistors are selected at least 3 times of the 350 nm minimum channel length for lower static leakage current.

Chopper Mechanism and Correlated Double Sampling
Under phase Φ1 and Φ2, the BGR power cycle is controlled by the clock ON/OFF CLK as shown in Figure 3b. With the duty cycle D = 0.25% (TON = 250 us, TON + TOFF = 100 ms), a working current of 16 uA is budgeted for the BGR block to achieve an average power consumption as low as 40 nA. The base-emitter voltage of transistor Q2 is given by where IC and JS are the working collector current and reverse saturation current per unit area of the transistor, respectively, and A is the emitter area. We assume the current variation is IX. Then the relative error can be deduced as in Equation (5).  Figure 3 shows the implementation of the on-off BGR which employs chopper mechanism. A near-zero power consumption start-up structure is adopted. The parameter values of the main components in the BGR core circuit are as follows. The emitter area of Q 1 and Q 2 is 2 × 2 µm. R 1 = 10 kΩ and R 2 = 80 kΩ. The size of MP 1/2 is 8 µm/16 µm × 6 while the size of the switch transistors is 4 µm/1 µm × 1. The sizes of the transistors are designed to be large for good matching and low flicker noise. Considering the low speed characteristic of the designed circuit, the lengths of the transistors are selected at least 3 times of the 350 nm minimum channel length for lower static leakage current.

Chopper Mechanism and Correlated Double Sampling
Under phase Φ 1 and Φ 2 , the BGR power cycle is controlled by the clock ON/OFF CLK as shown in Figure 3b. With the duty cycle D = 0.25% (T ON = 250 us, T ON + T OFF = 100 ms), a working current of 16 uA is budgeted for the BGR block to achieve an average power consumption as low as 40 nA. The base-emitter voltage of transistor Q 2 is given by where I C and J S are the working collector current and reverse saturation current per unit area of the transistor, respectively, and A is the emitter area. We assume the current variation is I X . Then the relative error can be deduced as in Equation (5). where ε represents the relative error, and I A = I C . D is the average current. When the working collector current I C is increased by an on/off duty cycle of 0.25%, the relative error spread of V BE is 400 times less. The chopper blocks are controlled by the 10Hz CH_CLK to cancel the offset of the Opamp under phases Φ 3 and Φ 4 . In the middle of the on-phase of BGR, the chopper blocks convert connection status from (X 2 -A, X 1 -B) to (X 1 -A, X 2 -B). In the next on-phase, the connection status changes back. Another chopper block is introduced in the signal path of the designed Opamp to assure that a negative feedback loop be formed according to the chopper status in the on-off BGR.
In the next on-phase, the connection status changes back. Another chopper block is introduced in the signal path of the designed Opamp to assure that a negative feedback loop be formed according to the chopper status in the on-off BGR.  Figure 4 shows the sampling-capacitor circuit using the technique of correlated double sampling (CDS) [14,15]. The values of the sampling capacitors are selected as C1 = C2 = C0 = 40 μm × 40 μm (1.6 pF). In the control of double sampling clocks CLK_1 and CLK_2, whose clock timings are shown in Figure 4b, C1 and C2 sample the output of the on-off BGR VREF before and after the chopper connection state conversion during TS1 and TS2, respectively, in a working (on) period. C0 samples during the interval TS and sums up the two sampled voltages in it. Using Equation (2), only the Opamp offset is considered,  Figure 4 shows the sampling-capacitor circuit using the technique of correlated double sampling (CDS) [14,15]. The values of the sampling capacitors are selected as C 1 = C 2 = C 0 = 40 µm × 40 µm (1.6 pF). In the control of double sampling clocks CLK_1 and CLK_2, whose clock timings are shown in Figure 4b, C 1 and C 2 sample the output of the on-off BGR V REF before and after the chopper connection state conversion during T S1 and T S2 , respectively, in a working (on) period. C 0 samples during the interval T S and sums up the two sampled voltages in it. Using Equation (2), only the Opamp offset is considered, where C 1 = C 2 = C 0 = C, V 1 is the voltage on C 1 which is sampled before the connection state conversion, V 2 is the voltage on C 2 sampled after the conversion, V 0 is the current voltage on C 0 and V 0 is the sample voltage in next cycle on C 0 . Eventually, V des is the original design value of V REF .
When the stable condition is reached, V 0 is the average value of V 1 and V 2 , canceling the error of V REF caused by the Opamp offset.
Electronics 2019, 8, x FOR PEER REVIEW 5 of 11 where C1 = C2 = C0 = C, V1' is the voltage on C1 which is sampled before the connection state conversion, V2' is the voltage on C2 sampled after the conversion, V0 is the current voltage on C0 and V0' is the sample voltage in next cycle on C0. Eventually, Vdes is the original design value of VREF. When the stable condition is reached, V0 is the average value of V1' and V2', canceling the error of VREF caused by the Opamp offset.   Figure 5 shows the circuit implementation of the sample-and-hold switched-RC filter. A MOS-R is used to achieve a high RC filtering resistance of 25 MΩ with small chip area. To alleviate the effect of injection and clock feedthrough, a dummy MOS switch M2 is added in series with the actual switch M1 [13].

Sample-and-Hold Switched-RC Filter
Since the drain-bulk and drain-source leakage is critical to the accuracy and stability of VREF output, especially during a long hold time of 100 ms, a simple feedback buffer A1 is used to reduce the voltage drop. In the hold phase, the bulk and source nodes of M1 are buffered to VREF through M7, eliminating charge leakage at CS. Moreover, the filter emulates a much lower filter pole frequency by pulse-switching them. Compared to the RC filter in Figure 2, the effective pole frequency in Figure 5 is given by [13]: with CS = 10 pF, RS = 25 MΩ, and D = 0.06% (TS = 60 us, TH + TS = 100 ms), a filter pole of 0.4 Hz can be achieved, which is about two decades lower than the noise integration bandwidth. Consequently, out-of-band noise could be filtered more thoroughly.  Figure 5 shows the circuit implementation of the sample-and-hold switched-RC filter. A MOS-R is used to achieve a high RC filtering resistance of 25 MΩ with small chip area. To alleviate the effect of injection and clock feedthrough, a dummy MOS switch M 2 is added in series with the actual switch M 1 [13].

Sample-and-Hold Switched-RC Filter
Since the drain-bulk and drain-source leakage is critical to the accuracy and stability of V REF output, especially during a long hold time of 100 ms, a simple feedback buffer A 1 is used to reduce the voltage drop. In the hold phase, the bulk and source nodes of M 1 are buffered to V REF through M 7 , eliminating charge leakage at C S . Moreover, the filter emulates a much lower filter pole frequency by pulse-switching them. Compared to the RC filter in Figure 2, the effective pole frequency in Figure 5 is given by [13]: with C S = 10 pF, R S = 25 MΩ, and D = 0.06% (T S = 60 us, T H + T S = 100 ms), a filter pole of 0.4 Hz can be achieved, which is about two decades lower than the noise integration bandwidth. Consequently, out-of-band noise could be filtered more thoroughly.

Simulation and Measurement Results
The Offset-Cancelation Switched-RC Bandgap Reference presented in this paper has been applied in an implanted cardiac pacemaker ASIC, featured with low power, high reliability and low speed. Consequently, 0.35 μm CMOS technology is employed, which is not advanced but adequately qualified for such applications [1,2]. Also, a lithium-iodine battery with a typical supply voltage of 2.8V is usually used for cardiac pacemakers, which has a sufficient level of safety and good discharging characteristics [4].
For on-off BGRs with small duty cycles, the settling time for start-up is usually concerned. Figure  6 shows the transient output voltage of the proposed circuit at the supply voltage of 2.8 V and temperature of 27 °C. It takes about 0.6 ms to reach steady state. Monte Carlo 200 simulation runs have been done after layout parasitic extraction, considering the process variation and mismatch. The results are presented in Figure 7a. The mean value (μ) of the proposed BGR is 1.1689 V with the standard deviation (σ) of 4.6 mV, and the coefficient of variation is calculated to be about 0.39%. The simulated temperature dependence of the output reference voltage VREF is plotted in Figure 7b. The temperature coefficient (TC) of the proposed BGR is 9.43 ppm/°C with temperature ranging from -20 to 80 °C.

Simulation and Measurement Results
The Offset-Cancelation Switched-RC Bandgap Reference presented in this paper has been applied in an implanted cardiac pacemaker ASIC, featured with low power, high reliability and low speed. Consequently, 0.35 µm CMOS technology is employed, which is not advanced but adequately qualified for such applications [1,2]. Also, a lithium-iodine battery with a typical supply voltage of 2.8 V is usually used for cardiac pacemakers, which has a sufficient level of safety and good discharging characteristics [4].
For on-off BGRs with small duty cycles, the settling time for start-up is usually concerned. Figure

Simulation and Measurement Results
The Offset-Cancelation Switched-RC Bandgap Reference presented in this paper has been applied in an implanted cardiac pacemaker ASIC, featured with low power, high reliability and low speed. Consequently, 0.35 μm CMOS technology is employed, which is not advanced but adequately qualified for such applications [1,2]. Also, a lithium-iodine battery with a typical supply voltage of 2.8V is usually used for cardiac pacemakers, which has a sufficient level of safety and good discharging characteristics [4].
For on-off BGRs with small duty cycles, the settling time for start-up is usually concerned. Figure  6 shows the transient output voltage of the proposed circuit at the supply voltage of 2.8 V and temperature of 27 °C. It takes about 0.6 ms to reach steady state. Monte Carlo 200 simulation runs have been done after layout parasitic extraction, considering the process variation and mismatch. The results are presented in Figure 7a. The mean value (μ) of the proposed BGR is 1.1689 V with the standard deviation (σ) of 4.6 mV, and the coefficient of variation is calculated to be about 0.39%. The simulated temperature dependence of the output reference voltage VREF is plotted in Figure 7b. The temperature coefficient (TC) of the proposed BGR is 9.43 ppm/°C with temperature ranging from -20 to 80 °C.   The proposed BGR circuit is implemented in 0.35 μm standard CMOS process. Figure 8 shows the BGR micrograph of the die. The core circuit occupies an area of 0.063 mm 2 , which could be optimized after an elaborate layout design. The total current consumption is measured as 78 nA on average from 30 samples. The digital clock generation block consumes 26 nA average current, which means that the percentage of the overhead power consumption by the clock generation block is 33.3% or one third. Figure 9 shows the distribution of the measured output voltage in 30 samples with 2.8 V supply voltage at 27 °C. The mean value (μ) is 1.167 V with the standard deviation (σ) of 8.1 mV. The proposed BGR can achieve an accuracy of 0.69% in the measurement. The accuracy of 0.69% is achieved without trimming and could be considered to be adequate for most implantable biomedical electronics. The low power feature is obtained due to the low duty cycle (D = 0.25%) operation of the on-off BRG. Moreover, the following correlated double sampler and the switched-RC filter just consume about 12 nA average current and occupy about 0.03 mm 2 chip area of the total 0.063 mm 2 chip area, but guaranteed the good performance of the on-off BRG. The on-off BGR achieves an untrimmed measured accuracy of 0.69%, which is comparable with the accuracy of BGRs with current consumptions of hundreds of times larger, just at a small price. The proposed BGR circuit is implemented in 0.35 µm standard CMOS process. Figure 8 shows the BGR micrograph of the die. The core circuit occupies an area of 0.063 mm 2 , which could be optimized after an elaborate layout design. The total current consumption is measured as 78 nA on average from 30 samples. The digital clock generation block consumes 26 nA average current, which means that the percentage of the overhead power consumption by the clock generation block is 33.3% or one third. Figure 9 shows the distribution of the measured output voltage in 30 samples with 2.8 V supply voltage at 27 • C. The mean value (µ) is 1.167 V with the standard deviation (σ) of 8.1 mV. The proposed BGR can achieve an accuracy of 0.69% in the measurement. The accuracy of 0.69% is achieved without trimming and could be considered to be adequate for most implantable biomedical electronics. The low power feature is obtained due to the low duty cycle (D = 0.25%) operation of the on-off BRG. Moreover, the following correlated double sampler and the switched-RC filter just consume about 12 nA average current and occupy about 0.03 mm 2 chip area of the total 0.063 mm 2 chip area, but guaranteed the good performance of the on-off BRG. The on-off BGR achieves an untrimmed measured accuracy of 0.69%, which is comparable with the accuracy of BGRs with current consumptions of hundreds of times larger, just at a small price.   Figure 10 shows VREF versus temperature ranging from -20 to 80 °C and the measured TC ranges from 13.7 ppm/°C to 38.2 ppm/°C with an average TC of 19.6 ppm/°C. Figure 11 shows the measured reference voltage versus the supply voltage at 27 °C. When the supply voltage changes from 1.8 V to 3.2 V, the BGR voltage variation is less than 0.83 mV. The reference voltage can achieve the line regulation of 0.59 mV/V. For measurement convenience, when measuring the power supply rejection ratio (PSRR), the on-off period is set at 10 ms instead of 100 ms, which will not affect the authenticity of the measured results. Figure 12 shows the PSRR results, which is better than 58.6 dB before 200 kHz. There are peaks at multiples of 100 Hz (1/10 ms) due to the characteristic of sampling. When the frequency of the fluctuation on the supply is the same as the sampling rate, the effect of the supply fluctuation on the sampled output voltage is also the same during the on phase in every sampling period and thus will be attenuated.
The performance of the proposed BGR circuit is summarized in Table 1, and these results are compared with other published references. From Table 1, it is observed that this work has the best line regulation and temperature coefficient in the untrimmed voltage references, while it also has advantages in the aspects of current consumption and untrimmed accuracy. However, the limitations of such on-off BGR are analyzed as follows. First, a small ripple at the switching moment still exists after switched-RC filtering. For continuous-time applications, this issue should be considered. Second, because the BGR output voltage is sampled in the capacitor, it has limited driving ability.   Figure 10 shows VREF versus temperature ranging from -20 to 80 °C and the measured TC ranges from 13.7 ppm/°C to 38.2 ppm/°C with an average TC of 19.6 ppm/°C. Figure 11 shows the measured reference voltage versus the supply voltage at 27 °C. When the supply voltage changes from 1.8 V to 3.2 V, the BGR voltage variation is less than 0.83 mV. The reference voltage can achieve the line regulation of 0.59 mV/V. For measurement convenience, when measuring the power supply rejection ratio (PSRR), the on-off period is set at 10 ms instead of 100 ms, which will not affect the authenticity of the measured results. Figure 12 shows the PSRR results, which is better than 58.6 dB before 200 kHz. There are peaks at multiples of 100 Hz (1/10 ms) due to the characteristic of sampling. When the frequency of the fluctuation on the supply is the same as the sampling rate, the effect of the supply fluctuation on the sampled output voltage is also the same during the on phase in every sampling period and thus will be attenuated.
The performance of the proposed BGR circuit is summarized in Table 1, and these results are compared with other published references. From Table 1, it is observed that this work has the best line regulation and temperature coefficient in the untrimmed voltage references, while it also has advantages in the aspects of current consumption and untrimmed accuracy. However, the limitations of such on-off BGR are analyzed as follows. First, a small ripple at the switching moment still exists after switched-RC filtering. For continuous-time applications, this issue should be considered. Second, because the BGR output voltage is sampled in the capacitor, it has limited driving ability.   Figure 11 shows the measured reference voltage versus the supply voltage at 27 • C. When the supply voltage changes from 1.8 V to 3.2 V, the BGR voltage variation is less than 0.83 mV. The reference voltage can achieve the line regulation of 0.59 mV/V. For measurement convenience, when measuring the power supply rejection ratio (PSRR), the on-off period is set at 10 ms instead of 100 ms, which will not affect the authenticity of the measured results. Figure 12 shows the PSRR results, which is better than 58.6 dB before 200 kHz. There are peaks at multiples of 100 Hz (1/10 ms) due to the characteristic of sampling. When the frequency of the fluctuation on the supply is the same as the sampling rate, the effect of the supply fluctuation on the sampled output voltage is also the same during the on phase in every sampling period and thus will be attenuated.
The performance of the proposed BGR circuit is summarized in Table 1, and these results are compared with other published references. From Table 1, it is observed that this work has the best line regulation and temperature coefficient in the untrimmed voltage references, while it also has advantages in the aspects of current consumption and untrimmed accuracy. However, the limitations of such on-off BGR are analyzed as follows. First, a small ripple at the switching moment still exists after switched-RC filtering. For continuous-time applications, this issue should be considered. Second, because the BGR output voltage is sampled in the capacitor, it has limited driving ability.

Conclusions
An ultra-low power, high accuracy BGR designed for implantable medical electronics is presented in this paper. To solve the conflict between low power and high accuracy, an on-off bandgap combined with sample-and-hold switched-RC filter is developed. A higher working current is allowed to alleviate V BE spread, which directly causes error to output voltage, but also keeps the average power consumption as low as 220 nW with the voltage supply of 2.8 V. Furthermore, to improve the accuracy ulteriorly, the error brought by the Opamp offset is eliminated by applying correlated double sampling strategy. As a result, the measured voltage accuracy of 0.69% is achieved without trimming, which is adequate for most implanted medical electronics. The circuit shows a line regulation of 0.59 mV/V in the supply voltage range of 1.8-3.2 V and a TC of 19.6 ppm/ • C in the temperature ranging from −20 to 80 • C. The proposed BGR circuit meets all the requirements of implantable medical electronics. It is very suitable for application in biomedical systems.