Improvements on the Carrier-Based Control Method for a Three-Level T-Type, Quasi-Impedance-Source Inverter

: The boost feature that characterizes Z-source and quasi-Z-source converters is usually achieved by means of a proper insertion of short-circuit states in the full DC-link. In this work, a novel pulse width modulation carrier-based strategy for a three-phase, three-level T-type, quasi-Z-source inverter is introduced, based on the addition of alternate short-circuits in the two halves of the DC-link bus. This technique achieves better performance, less electromagnetic interference, and lower harmonic distortion of the output line-to-line voltage compared to the traditional methods based on the full DC-link shoot-through. At the same time, generating the switching states is to easy implement. The proposed strategy permits the use of electronic devices with lower blocking voltage capability, thus improving converter reliability, size, and cost. The new method may be implemented in another multilevel inverter with an impedance-source network as well. A comprehensive simulation study is performed in order to validate the adopted method, with di ﬀ erent inverter input voltages, which is taken as representative of a photovoltaic array. Comparisons are conducted with conventional strategy insertions using the same topology in order to show the improvements achieved.


Introduction
The two-level, three-phase voltage source inverter (VSI) is probably one of the most widely used power electronic converters. Its area of application includes photovoltaic (PV) systems or drives for AC electric machines. Three-level VSIs have also been studied and used as an alternative to the standard two-level inverter because they offer a lower electromagnetic interference level, better waveform quality, lower semiconductor stress, and increased efficiency at higher switching frequencies [1][2][3]. Among the three-level VSI topologies, two main groups can be distinguished: the three-level, neutral-point clamped (3L-NPC) topology and the three-level T-type (3L-T-type) topology. The T-type inverter only uses one bidirectional power switch for clamping the middle node to the positive or negative DC-link, and it requires two diodes less per bridge leg [4]. As the external semiconductors of the T-type inverter must block the total DC-link voltage, the NPC variant seems a more suitable choice at higher switching frequencies, when switching losses become more significant [1]. However, both groups of inverters But, in a three-level inverter, a half DC-link short circuit is also possible. Therefore, besides the full shoot-through (FST) state previously mentioned, two new switching states emerge for three-level inverters: upper shoot-through (UST) and lower shoot-through (LST). These states were defined in [29]; the idea was applied to a 3L-NPC Z-source inverter [19], to a 3L-NPC-quasi-Z-source inverter [30], and to a 3L-T-type Z-source inverter [20]. Moreover, literature pieces dealing with the concept of UST/LST states have all used the modulation-based SVM technique. However, the association of a double quasi-Z-source network with a T-type inverter using a carrier-based modulation technique with UST/LST states has not been considered so far. In this work, a novel, pulse width modulation carrier-based technique for a three-phase, three-level T-type, quasi-Z-source inverter (3L-T-type qZS inverter) is introduced. It consists of the addition of the so-called UST and LST states, which achieves better performance, less electromagnetic interference (EMI), and lower harmonic content of the output voltage signal compared to modulation that uses only the FST state. It also permits the use of electronic devices with less blocking voltage capability, thus improving converter reliability and cost. The control method can be readily adapted to single-phase, multilevel-based, or other impedance source inverters.
The main contributions of this paper are: • Proposal of a carrier-based pulse width modulation able to generate alternating UST and LST states for a multilevel Z-source, which provides several benefits (aforementioned) compared to the conventional FST state strategies presented in [5,11,24]. • Development of the strategy as a carrier-based pulse width instead of SVM-based, as others reported in the literature [22,23,30], allowing easier implementation.

•
Application of the proposed strategy in a three-phase, 3L-T-type qZS inverter. This topology is considered quite promising for renewable energy applications [23,24], and it is validated by simulation.
The rest of this paper is organized as follows. The new modulation technique is developed in detail in Section 2. The theoretical ideas are tested by simulation in Section 3. Section 4 concludes this paper.

Theoretical Analysis
The power circuit is shown in Figure 1. Two identical quasi-Z-source networks are connected to a common node between capacitors C 2 and C 3 . These networks are linked to a T-type three-level VSI. inverter. But, in a three-level inverter, a half DC-link short circuit is also possible. Therefore, besides the full shoot-through (FST) state previously mentioned, two new switching states emerge for threelevel inverters: upper shoot-through (UST) and lower shoot-through (LST). These states were defined in [29]; the idea was applied to a 3L-NPC Z-source inverter [19], to a 3L-NPC-quasi-Z-source inverter [30], and to a 3L-T-type Z-source inverter [20]. Moreover, literature pieces dealing with the concept of UST/LST states have all used the modulation-based SVM technique. However, the association of a double quasi-Z-source network with a T-type inverter using a carrier-based modulation technique with UST/LST states has not been considered so far. In this work, a novel, pulse width modulation carrier-based technique for a three-phase, three-level T-type, quasi-Z-source inverter (3L-T-type qZS inverter) is introduced. It consists of the addition of the so-called UST and LST states, which achieves better performance, less electromagnetic interference (EMI), and lower harmonic content of the output voltage signal compared to modulation that uses only the FST state. It also permits the use of electronic devices with less blocking voltage capability, thus improving converter reliability and cost. The control method can be readily adapted to single-phase, multilevel-based, or other impedance source inverters.
The main contributions of this paper are: • Proposal of a carrier-based pulse width modulation able to generate alternating UST and LST states for a multilevel Z-source, which provides several benefits (aforementioned) compared to the conventional FST state strategies presented in [5,11,24]. • Development of the strategy as a carrier-based pulse width instead of SVM-based, as others reported in the literature [22,23,30], allowing easier implementation. • Application of the proposed strategy in a three-phase, 3L-T-type qZS inverter. This topology is considered quite promising for renewable energy applications [23,24], and it is validated by simulation. The rest of this paper is organized as follows. The new modulation technique is developed in detail in Section 2. The theoretical ideas are tested by simulation in Section 3. Section 4 concludes this paper.

Theoretical Analysis
The power circuit is shown in Figure 1. Two identical quasi-Z-source networks are connected to a common node between capacitors and . These networks are linked to a T-type three-level VSI.
Three-level T-type inverter Filter Load

Operation Principle with Upper and Lower Shoot-Through States
By means of diverse switching combinations, a voltage waveform with three possible voltage levels, -V PN /2, 0, and V PN /2, was obtained at each converter leg. In the switching scheme used in a traditional three-level VSI, the output of each phase (a, b, c) can be in either P-, 0-, or N-state (i.e., connected to the positive (P), the neutral (0), or the negative (N) terminal, respectively). Three phases and three states were combined to form 27 valid switching states, depicted in Figure 2, in the well-known space vector representation for a three-level converter.

Operation Principle with Upper and Lower Shoot-Through States
By means of diverse switching combinations, a voltage waveform with three possible voltage levels, -/2, 0, and /2, was obtained at each converter leg. In the switching scheme used in a traditional three-level VSI, the output of each phase (a, b, c) can be in either P-, 0-, or N-state (i.e., connected to the positive (P), the neutral (0), or the negative (N) terminal, respectively). Three phases and three states were combined to form 27 valid switching states, depicted in Figure 2, in the wellknown space vector representation for a three-level converter. There was one extra zero state when the load terminals were shorted through the on state of both the upper and lower switches ( and ) of any phase leg, combinations of any two phase legs, or all three phase legs. This ST zero state was not allowed in the traditional VSI because it caused a short circuit of the capacitors on the DC side. However, thanks to the quasi-Z-source network, ST states were allowed. Energy was stored in the inductors during ST states. Then, during the non-shootthrough (NST) states (comprising the 27 states of the conventional three-level VSI inverter), it was transferred to the capacitors and the load. By means of adjusting the ST duty cycle, the peak DC-link voltage was controlled, and, therefore, the inverter was provided with the desired buck-boost feature.
The ST state described was the so-called full shoot-through (FST) mode, in which short-circuits in the full DC-link, connecting terminals P with N, were produced. Besides the FST state used in the majority of the previous works, two new switching states named UST and LST states emerged in [29]. The UST state corresponds to the simultaneous activation of switches and in a phase leg. It produces a short circuit in the upper half DC-link, connecting terminals P and 0. On the other hand, the LST state takes place when switches and in a phase branch are simultaneously turned on. This produces a short circuit in the lower half DC-link, connecting the terminals 0 and N. Application of these new states reduces the harmonic distortion of the output line-to-line voltage compared to the FST. Table 1 describes the mentioned states for the phase-a case. Figure 3 includes the three equivalent circuits in NST, UST, and LST states, respectively. There was one extra zero state when the load terminals were shorted through the on state of both the upper and lower switches (S 1 and S 2 ) of any phase leg, combinations of any two phase legs, or all three phase legs. This ST zero state was not allowed in the traditional VSI because it caused a short circuit of the capacitors on the DC side. However, thanks to the quasi-Z-source network, ST states were allowed. Energy was stored in the inductors during ST states. Then, during the non-shoot-through (NST) states (comprising the 27 states of the conventional three-level VSI inverter), it was transferred to the capacitors and the load. By means of adjusting the ST duty cycle, the peak DC-link voltage was controlled, and, therefore, the inverter was provided with the desired buck-boost feature.
The ST state described was the so-called full shoot-through (FST) mode, in which short-circuits in the full DC-link, connecting terminals P with N, were produced. Besides the FST state used in the majority of the previous works, two new switching states named UST and LST states emerged in [29]. The UST state corresponds to the simultaneous activation of switches S 1 and S 3 in a phase leg. It produces a short circuit in the upper half DC-link, connecting terminals P and 0. On the other hand, the LST state takes place when switches S 4 and S 2 in a phase branch are simultaneously turned on. This produces a short circuit in the lower half DC-link, connecting the terminals 0 and N. Application of these new states reduces the harmonic distortion of the output line-to-line voltage compared to the FST. Table 1 describes the mentioned states for the phase-a case. Figure 3 includes the three equivalent circuits in NST, UST, and LST states, respectively.   Continuous conduction mode was assumed for the converter operation as well. Then, as the average voltage across inductors during one switching period should be zero in steady state, the boost factor (defined as = / , where is the peak DC-link voltage, present during NST states) can be calculated by the following Equation, [30]: Therefore, the amplitude of the fundamental output phase-to-neutral voltage is given by where m is the modulation index.

New Carrier-Based Modulation Method
A carrier-based level-shifted PWM (LS-PWM) with a modified constant boost control (MCBC) was proposed. Details of this novel modulation technique application are discussed below.
The reference and carrier signals are displayed in Figure 4 for the case of m = 0.7 and = 0.1.
A switching frequency value of 500 Hz (i.e., a frequency modulation index = 10) was used for better visualization. Three modulating signals * , * , and * were used as in the traditional PWM scheme. These signals were obtained by using the well-known technique based on the addition of a common offset voltage, Voff, to the three phase references [17,31]: Upper shoot through Lower shoot through T N , T U , and T L define NST, UST, and LST state durations, respectively. The corresponding duty ratios are With the aim of ensuring symmetric operation, D U and D L are set to be equal D U = D L = D 0 . If the quasi-Z-source network is assumed to be symmetric (i.e.,

the voltages across the inductors and capacitors are
Continuous conduction mode was assumed for the converter operation as well. Then, as the average voltage across inductors during one switching period should be zero in steady state, the boost factor (defined as B =V PN /V in , whereV PN is the peak DC-link voltage, present during NST states) can be calculated by the following Equation, [30]: Therefore, the amplitude of the fundamental output phase-to-neutral voltage is given bŷ where m is the modulation index.

New Carrier-Based Modulation Method
A carrier-based level-shifted PWM (LS-PWM) with a modified constant boost control (MCBC) was proposed. Details of this novel modulation technique application are discussed below.
The reference and carrier signals are displayed in Figure 4 for the case of m = 0.7 and D 0 = 0.1. A switching frequency value of 500 Hz (i.e., a frequency modulation index m f = 10) was used for better visualization. Three modulating signals v * a , v * b , and v * c were used as in the traditional PWM scheme. These signals were obtained by using the well-known technique based on the addition of a common offset voltage, V off , to the three phase references [17,31]: This approach permitted the modulation index m to be increased, avoiding the problems associated with overmodulation. In addition, it improved the waveform quality and reduced the switching losses significantly [32]. Another three modulating signals, ′ * , ′ * , and ′ * , were generated by shifting up and down the envelope of * , * , and * by the ST duty cycle ( 0 ). Then, the switching signals (including the ST states) were obtained by comparing the two sets of modulation signals with the two vertically disposed in-phase carrier signals, 1 and 2 , generating the upper and lower ST states (just one phase-leg; a, b, or c was shot-through).
Gate signal generation for switches 1 to 4 (x = a, b, and c) is demonstrated in Figure 5 for the switching cycle highlighted in Figure 4 (0.0620 to 0.0621 s). 3 and 2 would have complementary states to 1 and 4 , respectively, if there were no ST states. The existence of those states (UST and LST) can be observed on the overlapping of the corresponding on-states, pointed out in Figure 5.
By using these six reference signals, the converter was modulated as follows: for a phase-leg x, 1 was turned on when ′ * was greater than 1 , and 3 was turned on when * was smaller than 1 . On the other hand, 2 was turned on when ′ * was smaller than 2 , and 4 was turned on when * was greater than 2 .
It is interesting to note that to maintain the volt-second average per switching cycle, UST states should be added into the inverter states with the P terminal unconnected. These states are called Ntype small vectors in [20], and they are the states P00, PP0, 0P0, 0PP, 00P, and P0P in Figure 2. Similarly, LST states should be added into the inverter states with the N terminal unconnected (i.e., into the so-called P-type small vectors : 0NN, 00N, N0N, N00, NN0, 0N0). One can notice that when the N-and P-type small vectors contain two 0-states, UST and LST states can be achieved in two different ways, depending on the leg used to implement the ST condition. All the UST and LST states are collected in Table 2, where the letters L and U have been introduced in order to distinguish the NST states, and they must be interpreted as the connection of the corresponding phase-leg to the N or P terminal, respectively. This can be verified in Figure 5, where the states are P0P, P00, PN0, 0N0, PN0, P00, and P0P. UST insertion was performed in the state 0N0, while LST insertion was carried out in states P0P and P00.  This approach permitted the modulation index m to be increased, avoiding the problems associated with overmodulation. In addition, it improved the waveform quality and reduced the switching losses significantly [32].
Another three modulating signals, v * a , v * b , and v * c , were generated by shifting up and down the envelope of v * a , v * b , and v * c by the ST duty cycle (D 0 ). Then, the switching signals (including the ST states) were obtained by comparing the two sets of modulation signals with the two vertically disposed in-phase carrier signals, c 1 and c 2 , generating the upper and lower ST states (just one phase-leg; a, b, or c was shot-through).
Gate signal generation for switches S 1x to S 4x (x = a, b, and c) is demonstrated in Figure 5 for the switching cycle highlighted in Figure 4 (0.0620 s to 0.0621 s). S 3x and S 2x would have complementary states to S 1x and S 4x , respectively, if there were no ST states. The existence of those states (UST and LST) can be observed on the overlapping of the corresponding on-states, pointed out in Figure 5.
By using these six reference signals, the converter was modulated as follows: for a phase-leg x, S 1x was turned on when v * x was greater than c 1 , and S 3x was turned on when v * x was smaller than c 1 . On the other hand, S 2x was turned on when v * x was smaller than c 2 , and S 4x was turned on when v * x was greater than c 2 . It is interesting to note that to maintain the volt-second average per switching cycle, UST states should be added into the inverter states with the P terminal unconnected. These states are called N-type small vectors in [20], and they are the states P00, PP0, 0P0, 0PP, 00P, and P0P in Figure 2. Similarly, LST states should be added into the inverter states with the N terminal unconnected (i.e., into the so-called P-type small vectors: 0NN, 00N, N0N, N00, NN0, 0N0). One can notice that when the N-and P-type small vectors contain two 0-states, UST and LST states can be achieved in two different ways, depending on the leg used to implement the ST condition. All the UST and LST states are collected in Table 2, where the letters L and U have been introduced in order to distinguish the NST states, and they must be interpreted as the connection of the corresponding phase-leg to the N or P terminal, respectively. This can be verified in Figure 5, where the states are P0P, P00, PN0, 0N0, PN0, P00, and P0P. UST insertion was performed in the state 0N0, while LST insertion was carried out in states P0P and P00.

Simulation Results
The proposed approach was tested through a simulation study using the PSCAD (version X4 Simulation results of input voltage and current ( , ), DC-link voltage ( ), line-to-line voltages before filtering ( , , and ), and output currents ( , , and ) are shown in Figure  6 for the nonboosting case and in Figure 7 using the novel application of UST/LST pulse with

Simulation Results
The proposed approach was tested through a simulation study using the PSCAD (version X4 (4.5), Manitoba HVDC Research Centre, Winnipeg, Canada, 2014) simulation tool. The parameters of the chosen quasi-Z-source network ( Figure 1) were C 1 = C 2 = C 3 = C 4 = 470 µF and L 1 = L 2 = L 3 = L 4 = 0.5 mH, and the switching frequency was set at 10 kHz. A DC power supply of 500-800 V was used as inverter input, emulating the operation of a PV array. The converter supplied a balanced, three-phase, wye-connected resistive load, R L = 40 Ω, at 230/400 V and 50 Hz. A simple inductive filter was used with inductance L f = 7.5 mH.
Simulation results of input voltage and current (V in , I in ), DC-link voltage (V PN ), line-to-line voltages before filtering (v ab , v bc , and v ca ), and output currents (i a , i b , and i c ) are shown in Figure 6 for the nonboosting case and in Figure 7 using the novel application of UST/LST pulse with modulation approach. In order to show the improvements achieved, the traditional FST strategy was tested by simulation, and the main waveforms were shown in Figure 8. These cases are discussed in the following paragraphs.
First, it was assumed that the output voltage of the PV array was at its maximum value of 800 V. In this case, to synthesize the required output grid voltage (in the range 380-420 V line-to-line RMS), the modulation index and UST/LST duty cycle were fixed to m = 0.8 and D 0 = 0. Boost operation was not needed, so the inverter operated in the VSI mode. Figure 6 shows the simulated waveform for this case. The current drawn from the PV array (I in ) was almost ripple-free since no shoot-through states were activated. The DC-link voltage (V PN ) was not boosted (B = 1), and it was maintained at almost 800 V. The output line-to- line voltages (v a,b,c ) were composed of the levels 0, ±800/2 V, and ±800 V. The RMS value of the fundamental component was 390.9 V, which was within the desired range. The corresponding phase-to-neutral peak voltage of 319.16 V matched the expected value, according to Equation (2). modulation approach. In order to show the improvements achieved, the traditional FST strategy was tested by simulation, and the main waveforms were shown in Figure 8. These cases are discussed in the following paragraphs. First, it was assumed that the output voltage of the PV array was at its maximum value of 800 V. In this case, to synthesize the required output grid voltage (in the range 380-420 V line-to-line RMS), the modulation index and UST/LST duty cycle were fixed to m = 0.8 and 0 = 0. Boost operation was not needed, so the inverter operated in the VSI mode. Figure 6 shows the simulated waveform for this case. The current drawn from the PV array ( ) was almost ripple-free since no shoot-through states were activated. The DC-link voltage ( ) was not boosted (B = 1), and it was maintained at almost 800 V. The output line-to-line voltages ( , , ) were composed of the levels 0, ±800/2 V, and ±800 V. The RMS value of the fundamental component was 390.9 V, which was within the desired range. The corresponding phase-to-neutral peak voltage of 319.16 V matched the expected value, according to Equation (2). Next, to illustrate the boost performance operation, the PV panels output was at its minimum value of 500 V (due to bad weather, for example). Now, to synthesize the required output voltage to the grid, a boost operation was needed. This was achieved by maintaining the modulation index at 0.8 and changing the ratio 0 to 0.2. The results are shown in Figure 7. Now, the current from the PV array was in continuous conduction mode, with ripples resulting from the shoot-through states. The DC-link voltage was boosted, assuming two levels: and /2, where = 1/(1 − 2 0 ) was the boost factor (i.e., almost 827 V and 827/2 V). This was a unique feature of the UST/LST strategy, while for the FST strategy the levels were and 0. The output line-to-line voltages were composed of the levels 0, ± /2, and ± (i.e., 0, ±827/2, and ±827 V). The RMS value of the fundamental component was in this case 404.9 V, which was within the desired range. According to Equation (2), the corresponding phase-to-neutral peak voltage of 330.6 V was in good agreement with the expected value. In both cases, high-quality sinusoidal line currents were also obtained.
It is interesting to note that there were slight errors between the expected and simulated values, since the voltage dropped across the diodes and the inductors 1 and 2 were not considered when deriving the equations. Next, to illustrate the boost performance operation, the PV panels output was at its minimum value of 500 V (due to bad weather, for example). Now, to synthesize the required output voltage to the grid, a boost operation was needed. This was achieved by maintaining the modulation index at 0.8 and changing the ratio D 0 to 0.2. The results are shown in Figure 7. Now, the current from the PV array was in continuous conduction mode, with ripples resulting from the shoot-through states. The DC-link voltage was boosted, assuming two levels: BV in and BV in /2, where B = 1/(1 − 2D 0 ) was the boost factor (i.e., almost 827 V and 827/2 V). This was a unique feature of the UST/LST strategy, while for the FST strategy the levels were BV in and 0. The output line-to-line voltages were composed of the levels 0, ±BV in /2, and ±BV in (i.e., 0, ±827/2, and ±827 V). The RMS value of the fundamental component was in this case 404.9 V, which was within the desired range. According to Equation (2), the corresponding phase-to-neutral peak voltage of 330.6 V was in good agreement with the expected value. In both cases, high-quality sinusoidal line currents were also obtained.
It is interesting to note that there were slight errors between the expected and simulated values, since the voltage dropped across the diodes and the inductors L 1 and L 2 were not considered when deriving the equations.
To show the waveform differences and the improved harmonic performance of the proposed UST/LST strategy, compared to the FST strategy, a simulation test using the FST strategy was also carried out. In this case, an FST duty cycle D s = 0.2 was applied. The results are shown in Figure 8. To show the waveform differences and the improved harmonic performance of the proposed UST/LST strategy, compared to the FST strategy, a simulation test using the FST strategy was also carried out. In this case, an FST duty cycle = 0.2 was applied. The results are shown in Figure 8. Observing Figures 7 and 8, some of the advantages obtained by using the new UST/LST strategy compared to the conventional FST strategy were directly proven. Switches 1 and 2 (see Figure 1) had to block . Thus, semiconductors with less blocking voltage capability were required, reducing the cost and the size of the power converter. For the same reason, less EMI can be expected. Hence, the complexity of the control and measurement systems was reduced substantially.  To show the waveform differences and the improved harmonic performance of the proposed UST/LST strategy, compared to the FST strategy, a simulation test using the FST strategy was also carried out. In this case, an FST duty cycle = 0.2 was applied. The results are shown in Figure 8. Observing Figures 7 and 8, some of the advantages obtained by using the new UST/LST strategy compared to the conventional FST strategy were directly proven. Switches 1 and 2 (see Figure 1) had to block . Thus, semiconductors with less blocking voltage capability were required, reducing the cost and the size of the power converter. For the same reason, less EMI can be expected. Hence, the complexity of the control and measurement systems was reduced substantially. Observing Figures 7 and 8, some of the advantages obtained by using the new UST/LST strategy compared to the conventional FST strategy were directly proven. Switches S 1 and S 2 (see Figure 1) had to block V PN . Thus, semiconductors with less blocking voltage capability were required, reducing the cost and the size of the power converter. For the same reason, less EMI can be expected. Hence, the complexity of the control and measurement systems was reduced substantially.
At the same time, switching losses were determined as the energy that a semiconductor needed to switch on and switch off. The lower the blocking voltage, the fewer the switching losses were expected. To illustrate switching loss improvement, simulation tests were conducted applying the two strategies for several values of ST duty cycle, D 0 for UST/LST and D S for FST, where the modulation index was set at 1 − D 0 or 1 − D S , respectively. The influence of the switching frequency with constant D S in the converter efficiency for UST and UST/LST was also studied. The load was the same as before (40 Ω in the wye connection), and the input voltage was adjusted according to D 0 or D S to obtain the same output phase-to-neutral voltage (230 V) in all cases. The results, displayed in Figure 9, showed that the efficiency decreased with increasing ST duty cycle and with increasing switching frequency. However, the reduction was substantially lower for the proposed strategy. In other words, the new strategy exhibited lower global losses (conduction and switching). It is interesting to point out that this reduction mainly was due to switching loss decreases because the proposed strategy implied half the value of the semiconductor blocking voltage in the traditional strategy. Furthermore, for the same reason, semiconductor device stress was also reduced.
Voltage total harmonic distortion (THD), as a function of the D 0 or D S , was measured. The quality of the output voltage was higher with the new UST/LST for any value of the shoot-through duty cycle. This fact was predicted by comparing the magnitudes of line-to-line voltages before filtering (v ab , v bc , and v ca ) from Figures 7 and 8.
At the same time, switching losses were determined as the energy that a semiconductor needed to switch on and switch off. The lower the blocking voltage, the fewer the switching losses were expected. To illustrate switching loss improvement, simulation tests were conducted applying the two strategies for several values of ST duty cycle, for UST/LST and for FST, where the modulation index was set at 1 − or 1 − , respectively. The influence of the switching frequency with constant in the converter efficiency for UST and UST/LST was also studied. The load was the same as before (40 Ω in the wye connection), and the input voltage was adjusted according to or to obtain the same output phase-to-neutral voltage (230 V) in all cases. The results, displayed in Figure 9, showed that the efficiency decreased with increasing ST duty cycle and with increasing switching frequency. However, the reduction was substantially lower for the proposed strategy. In other words, the new strategy exhibited lower global losses (conduction and switching). It is interesting to point out that this reduction mainly was due to switching loss decreases because the proposed strategy implied half the value of the semiconductor blocking voltage in the traditional strategy. Furthermore, for the same reason, semiconductor device stress was also reduced.
Voltage total harmonic distortion (THD), as a function of the or , was measured. The quality of the output voltage was higher with the new UST/LST for any value of the shoot-through duty cycle. This fact was predicted by comparing the magnitudes of line-to-line voltages before filtering ( , , and ) from Figures 7 and 8.  Table 3 sums up performance comparisons of UST/LST and FST strategies in terms of voltage THD (calculated up to 500 harmonics) before filtering, power efficiency, semiconductor stress, and the complexity of implementation, and it points out the advantages of the proposed strategy. In addition, the fact that this strategy was a carrier-based type also implied advantages in its practical implementation; therefore, it is a competitive alternative for quasi-Z-source T-type inverter modulation.   Table 3 sums up performance comparisons of UST/LST and FST strategies in terms of voltage THD (calculated up to 500 harmonics) before filtering, power efficiency, semiconductor stress, and the complexity of implementation, and it points out the advantages of the proposed strategy. In addition, the fact that this strategy was a carrier-based type also implied advantages in its practical implementation; therefore, it is a competitive alternative for quasi-Z-source T-type inverter modulation.

Conclusions
The operating principles, circuit analysis, and modified new modulation carrier-based technique for a three-level T-type, quasi-Z-source inverter were presented. Using properly inserted short-circuits in the two halves of the DC-link voltage to the conventional three-level T-type inverter state sequence, the three-level T-type, quasi-Z-source inverter operated with voltage boosting capability and the correct volt-second average. This method was also simple to implement compared to the conventional UST/LST SVM. The proposed idea was successfully validated by simulations for different inverter input voltages, which were taken as representative values of a photovoltaic system under variable weather conditions. Besides, the comparison was carried out with different shoot-through duty cycles and different switching frequencies. The improvement allowed reduction in waveform distortions and switching losses, which led to passive component rating reductions and increased reliability compared to previously reported methods. Funding: This work was supported by Junta de Extremadura (Regional Government), Spain, under the Mobility Scholarship Program for Teaching and Research Staff of the Autonomous Community of Extremadura 2018, by the fund for research group (GR18087) and the regional project (IB18067).