A New Method to Extract Gate Bias-Dependent Parasitic Resistances in GaAs pHEMTs

Accurate large signal GaAs pHEMT models are essential for devices’ performance analysis and microwave circuit design. This, in turn, mandates precise small signal models. However, the accuracy of small signal models strongly depends on reliable parasitic parameter extraction of GaAs pHEMT, which also greatly influences the extraction of intrinsic elements. Specifically, the parasitic source and drain resistances, Rs and Rd, are gate bias-dependent, due to the two-dimensional charge variations. In this paper, we propose a new method to extract Rs and Rd directly from S-parameter measurements of the device under test (DUT), which save excessive measurements and complicated parameter extraction. We have validated the proposed method in both simulation and on-wafer measurement, which achieves better accuracy than the existing state-of-the-art in a frequency range of 0.5–40 GHz. Furthermore, we develop a GaAs pHEMT power amplifier (PA) to further validate the developed model. The measurement results of the PA at 9–15 GHz agree with the simulation results using the proposed model.


Introduction
Compared with the widely-used 4G mobile communication, 5G has obvious advantages in large-scale antenna arrays, resource utilization, transmission rate, and spectrum utilization.The capacity of 5G is 1000-times that of 4G, and the peak rate can reach 10 Gbps.In order to overcome the disadvantages of poor penetration ability and small coverage due to high frequency in 5G communication, a radio-frequency (RF) power amplifier must deliver high efficiency and linearity.5G power amplifiers (PAs) used in microcell and macrocells need to provide high P out , which can be realized by GaAs or GaN [1].In order to achieve high output power and efficiency, a 5G microcell/macrocell often utilizes GaAs pHEMTs due to their superior frequency response, breakdown performance, high charge density, and high electron mobility.In turn, an accurate and reliable GaAs pHEMT model is needed.
A number of available models for III-V devices have been published, such as physics-based models [2,3], ANNs-based models [4,5], and empirical-based models [6][7][8].ANNs-based models are not physical and often result in a slow convergence in the simulation.Physical-based models are complicated and could lead to long simulation times.In contrast, high-fidelity empirical-based compact models (i.e., equivalent circuit models) are desirable.First, an empirical-based compact model is simple and can facilitate simulations.Second, an empirical-based compact model offers a relatively smaller set of parameters, simplifying extraction and still abiding by device physics.Third, empirical-based compact models are scalable with regard to bias, temperature, and dimension, which is design friendly.
A large signal nonlinear model mandates a precise small signal model.However, the precision of small signal model strongly relies on parasitic parameter extraction of a GaAs pHEMT.In this paper, we focus on the extraction method for parasitic source and drain resistances, R s and R d .In [6][7][8][9][10][11], R s and R d were determined by S-parameters in the "cold" pinch-off condition, wherein the drain-to-source bias V ds was set to zero, and the gate electrode was in a pinch-off condition.The use of "ColdFET" measurements assumes that R s and R d are bias-independent.However, this assumption is not accurate because the space-charge layer extends into the gate-drain region and is also changed due to the two-dimensional charge control when the device gate bias varies [12].Therefore, R s and R d are gate bias-dependent.In III-V devices, the parasitic resistances R s and R d are closely related to g m and f T .For the electrons in the gate-source or gate-drain channel, a reduction in electron mobility (µ 0 ) induces an increase in R s and R d [12].The increase in R s and R d leads to a drop of g m and f T [13][14][15].In PAs, the output signal strength and linearity are determined by the input signal and device g m .Hence, it is preferred that g m remains constant [16,17].However, the drop of g m and f T induces gain reduction and seriously affects large signal linearity [17,18].Therefore, the gate bias-dependent parasitic resistances R s and R d play a key role in the nonlinearity of GaAs pHEMTs.
Aiming at analyzing the transistor performance, several methods have been developed in order to obtain R s and R d from experimental devices [12,[19][20][21].Pradeep [12] proposed a DC method to yield µ 0 , R s , and R d versus V gs simultaneously in an HEMT by using the I ds -V gs curves at a low drain-source voltage, V ds , of this device (short HEMT) and a much longer channel HEMT (long HEMT) and transfer length measurements (TLM) on ungated devices.However, this method mandates sophisticated DC measurements.The method in [19] uses the Y-function curve to obtain the series resistance through the curve of total resistance as a function of the inverse of the Y-function.The Y-function is calculated by I ds /g m 1/2 , where g m is the transconductance obtained by the derivative of I ds with respect to V gs .
However, this calculation process is complex and tends to introduce errors.A majorization of the iterative method was proposed in [20], where the complete process was iterated with an updated τ 0 value until internal consistency was achieved between the newly-determined τ and the updated seed value τ 0 .Obviously, this procedure needs a long calculating time.In Torres's method [21], two identical capacitances C gs = C gd were used to describe the depletion-layer in strong inversion at V ds = 0 V.This method is based on a common assumption, that the gate-to-source and gate-to-drain depletion-layer capacitances are equal for a symmetrical device structure in strong inversion.However, this assumption is not appropriate for pHEMTs due to the pHEMT devices' asymmetry [7,8].
In order to save excessive measurements and complicated parameter optimization, we propose a new method to determine R s and R d .The method utilizes desired device operation in strong inversion and attains on-wafer S-parameter measurements to derive R s and R d .The proposed method is verified in both simulation and on-wafer measurement, which achieves better accuracy than the existing state-of-the-art in a frequency range of 0.5-40 GHz.Furthermore, we develop a GaAs pHEMT PA to further validate the proposed method.The measurement results of the PA at 9-15 GHz agree well with the simulation results of the proposed method, which indicates the accuracy of the model and the effectiveness of the proposed extract method.
The remainder of this article is organized as follows.Section 2 is dedicated to the detailed extraction step of parasitic parameters R s and R d .Section 3 describes the test bench we built to verify the proposed method, and we discuss the results of the proposed model by comparing it with measurement data.The concluding remarks are drawn in the last section.

Modeling R s and R d
As mentioned before, the prior state-of-the-art used "ColdFET" measurements [6][7][8][9][10][11], assumed R s and R d as bias-independent, DC measurements [12,19], needed complicated DC measurements, iterative optimization [20], needed a complex calculation process and S-parameter measurements [21], used invalid assumptions, etc.To simplify the test steps and save parameter extraction time, we proposed a new parameter extraction method to obtain R s and R d .
The source and drain resistances, R s and R d , are different due to the pHEMT devices' asymmetry.R s and R d both can be treated as two parts: the first part describes the parasitic effect of contact resistance and is assumed to be constant.The second part describes the resistance between source or drain contact at one side and the beginning of the space charge region below gate at the other side, which charges with gate bias, due to the two-dimensional charge control.In terms of the description above, we write R s and R d as [12]: where R s_const and R s_bias represent the gate bias independent and dependent components of the source resistance, respectively.R d_const and R d_bias represent the gate bias independent and dependent components of the drain resistance, respectively.In this work, a new extraction method is proposed for GaAs pHEMTs.Similar to the extraction of parasitic resistance for MOSFETs in [21], transconductance (g m ) is negligible when a pHEMT is biased at V ds = 0 V.Given this condition, a small signal equivalent circuit of the device is simplified as Figure 1.R g is the gate resistance, and C gs , C gd , and C ds are the intrinsic capacitances between terminals.Z-parameters associated with the circuit of Figure 1 are given by: Then, the real parts of the Z-parameters are expressed as: where, As shown in Equations ( 7)-( 9), our primary task is to derive R g , A, and 1 + C gs /C gd .The value of 1 + C gs /C gd is deduced from the ratio of the imaginary part of Z 21 and Z 22 [22].That is: The imaginary part of Z 22 is rearranged as [21,22]: Prior works [21,22] calculated A based on the value of C x and R ch , i.e., C x is determined from the slope m of the linear regression of −ω/imag(Z 22 ) against the ω 2 curve, and R ch is calculated from 1/ √ m × b, where b is the extrapolation to ω 2 = 0 of the linear regression.Figure 2 shows the figure to determine C x and R ch for a pHEMT.Subsequently, R g can be derived from: The value of R g derived from A and 1 + C gs /C gd may introduce calculation errors.In order to resolve this issue, we directly extracted R g under the device pinched-off condition (V ds = 0, V gs < V th ) [7,8] according to the assumption that parasitic resistance R g is bias independent.Different from the prior derivation, we can directly calculate A from the real part of Z 11 and Z 12 .Substituting Equation (12) into Equations ( 7) and (8), real(Z 11 ) and real(Z 12 ) were rewritten as: 15) Subsequently, we calculate A by solving Equations ( 15) and ( 16) and yield: Once R g , A, and 1 + C gs /C gd are determined, R s and R d can be obtained by the following equations: Consequently, we achieve a simple calculation and reduce derivation error.The parameter extraction uncertainty calculation is discussed in Appendix A.

Measurements
To validate the modeling and parameter extraction methodology proposed in this paper, a group of multi-finger microwave GaAs E-mode pHEMTs in a common source configuration with gate lengths L G = 0.15 µm have been fabricated in a 0.15-µm E-mode pHEMT GaAs process.For these devices, the per-finger channel-widths (W f ) were 25 µm, 50 µm, 75 µm, and 100 µm, and the number of fingers (N f ) were 2, 4, and 6, respectively.
Figure 3 illustrates the setup of a measurement system for on-wafer RF measurements.A controller (Labview test program) sends commands to instruments (vector network analyzer (VNA), power signal generators (PSG), DC I-V supply, etc.).A probe station performs the measurements for a specific DUT and gathers measured data for post-processing.The DC characteristics of DUT are measured by the Keysight B2902A.The small signal behavior (i.e., S-parameter) of DUT is measured in a frequency range of 0.5-40 GHz by the Keysight N5247A VNA.Large signal performance of the DUT is measured by the Keysight E8267D PSG.The measurement system also used two 150 µm pitch ground-signal-ground (GSG) probes for RF experiments and two Bias Tees for I-V curve measurement.To ensure the accuracy of measurements, a system-level calibration was performed before conducting any measurements on the DUT.Typically, system-level calibration for on-wafer measurements is done by the short-open-load-through (SOLT) algorithm to remove undesirable effects of cables and probes, as well as for establishing the reference impedance to 50 Ω.In addition, a two-step de-embedding procedure using the measurements of on-wafer "open" and "short" dummy structures was carried out to subtract the test structures parasitic effect (TSPE) of probe pads and the interconnection line (i.e., representing the connection between the probe pads and the actual pHEMT) from measurements.Please bear in mind that the effect of the extrinsic pHEMT's parasitics (e.g., the gate electrode resistance and capacitances, etc.) was not removed by the de-embedding procedure, as well as the dummy structures described in [23].These measurements were performed up to 40 GHz under different bias conditions, varying V gs from the subthreshold region to the saturation region.The small signal model in Figure 4 shows extrinsic elements (i.e., C pg , C pd ,C pgd , L g , L d , L s , R g , R d , and R s ) and intrinsic elements (i.e., C gs , C ds ,C gd , R i , g m , g ds , R gd , and τ).A 4 × 50 µm E-mode pHEMT was used in the extraction procedure.Before extracting R d and R s from RF measurements, TSPE had to be removed from experimental data [23].The S-parameters of the pinched-off device (V ds = 0 V, V gs = 0 V) were first taken and converted to equivalent admittance parameters to determine the parasitic capacitances [7,8].Subsequently, the gate resistances and parasitic inductances were extracted by a "ColdFET" pinched-off method [7] after de-embedding the parasitic capacitors.
After we obtained the values of parasitic capacitances, parasitic inductances, and gate resistances, the proposed method was employed to extract R d and R s .Figure 5 shows the extracted value of 1/(1 + C gs /C gd ).It is seen that the value of 1/(1 + C gs /C gd ) is inversely proportional to V gs .The bias-dependence of 1/(1 + C gs /C gd ) shown in Figure 5 is associated with C gs and C gd .Because C gs increases with V gs dramatically, while C gd changes slightly with V gs , therefore C gs /C gd increases as a whole, meaning that 1/(1 + C gs /C gd ) drops. Figure 5 also indicates that the assumption in [21] is not appropriate for pHEMTs [7,8].Figure 6 shows that the value of A increases with V gs .Because the term ω 2 C 2 x R ch decreases with V gs dramatically while 1/R ch increases with V gs slightly, the term 1/R ch + ω 2 C 2 x R ch decreases and A increases accordingly with V gs .Figure 7 shows the extracted R d and R s for different V gs by the proposed method.Figure 7 shows that R d and R s increase with the rise of gate voltage, in which R d changes about 239% and R s changes about 270% with V gs from 0.25 V-0.7 V. Since R d and R s are defined as the sum of contact resistance and bulk resistance up to the edge of the gate depletion region, the extracted bias-dependent R d and R s are consistent with the previously-described physical principle.Once R d and R s have been extracted by the proposed method, the intrinsic elements' values of the pHEMT can be directly extracted by the intrinsic Y-parameters [24].Figure 8 displays the value of each intrinsic parameter at various biases (V gs = 0.25-0.7 V with an interval of 0.05 V and V ds = 0.5-5 V with a step of 0.5 V).C gs is low when the pHEMT is in the pinched-off region.C gs rapidly increases after the pHEMT is turned on.C ds is substantially constant near the saturation region.C gd decreases as V ds increases and varies slightly with V gs .g m increases rapidly as V gs increases.R i varies greatly in the linear region and is substantially constant in the saturation region.τ and g ds are associated with V gs .In addition, Figure 8a,c shows that C gd is far less than C gs for the pHEMTs and further verifies the assumption in [21] that it is not appropriate for pHEMTs [7,8].(e) g m characteristics.
(h) R i characteristics.Figure 9 shows the comparison between measured and simulated S-parameters before and after applying the "open-short" de-embedding procedure.S-parameters are taken at different drain and gate voltages, where the DUT operates from the pinch-off region (V ds = 0.5 V, V gs = 0.25 V) to the saturation region (V ds = 4.5 V, V gs = 0.70 V).As can be clearly observed, significant changes in the behavior of the S-parameters were detected by de-embedding the contributions associated with the "open" and "short" dummy structures.The experimental results verify the validity of the proposed extraction method to determine small signal extrinsic elements.The measurements agree with the simulated S-parameters across the entire frequency and bias range.As can be observed in Figure 9, the kink effect (KE) appears in S 22 only after de-embedding the extrinsic contributions for a certain bias point (i.e., Figure 9c,d).This is because the extrinsic contributions tend to mask the KE or even lead to its vanishing, and this finding is in line with the fact that the KE is inherently rooted in the intrinsic FET [9,25,26].It was confirmed by previous studies that have already demonstrated that the appearance or disappearance of the KE in S 22 is mostly due to the relatively high g m [9,25,26].Figure 10 shows the values of g m for pHEMT at four different bias conditions.As shown in Figures 9 and 10, the KE in S 22 vanishes when g m is small, while the KE in S 22 appears when g m is large.In order to evaluate the quantitative precision of the simulated S-parameter, the percentage error expression E ij between simulated and measured S-parameters is defined as follows: where f min and f max denote the frequency start point and stop point, respectively, N f presents the number of frequency points, and is 80 in this experiment.The total percentage error E total between models simulated and measured is formulated as follows: The bias-dependent S-parameter simulation for the same device was performed at 100 bias points covering V gs from 0.25-0.7 V and V ds from 0.5-5 V with a frequency range from 0.5-40 GHz.This simulation was then compared with measured data.
In Figure 11, the bias-dependent plots of E ij are given.Figure 11a shows the percentage error of S 11 , where the minimum value is 4.43%, the average value is 6.53%, and the maximum value is 8.64%.It is clearly seen from the figure that the error in the entire saturation region is 4%-6%.Figure 11b illustrates the percentage error of S 12 .The error range when V gs < 0.55 V was 2.46%-6.5%,which is acceptable.However, when V gs > = 0.55 V, the error increased to at most 8.22%, because S 12 became smaller at high V gs .Figure 11c illustrates the simulation error of S 21 , where the average error is 5.58% and the minimum error is 2.20%.It is shown that the error is pretty low except some discrete bias points, such as V ds = 4.5V, V gs = 0.5 V. Figure 11d illustrates the simulation error of S 22 , where the average error is 6.14% and the minimum value is 3.05%.It is shown that the measurement matches the simulation very well except some discrete bias points.In Figure 12, the bias-dependent plots of the total percentage error E total are given.The minimum value was 4.04%, the average error 6.07%, and the maximum error 7.65%.It is shown that the total percentage error is pretty low except some discrete bias points, such as V ds = 1.0 V, V gs = 0.7 V. Figures 11 and 12 both illustrate that the measured S-parameters match the simulation results very well, which verifies the effectiveness of the proposed extract method.In order to further examine the precision of the small signal equivalent circuit model based on the proposed extraction method, a large signal model based on Verilog-A was built to estimate the large signal RF behavior of GaAs E-mode pHEMTs.Figure 13 compares the measured and simulated results of the output power for 4 × 50 µm GaAs E-mode pHEMTs at V ds = 4 V, V gs = 0.55 V and frequency = 9, 15, 21, and 30 GHz, respectively.P out and gain-compression were accurately reproduced by the nonlinear model, which indicates an accurate nonlinear model and further verifies the effectiveness of the proposed extract method.In order to make the model flexible and facilitate circuit design.We have investigated the scaling of the intrinsic elements with respect to N f and W f .In Figure 14, we plot C gs , C ds , C gd , R i , R gd , g m , and g ds versus N f and W f at V ds = 4 V and V gs = 0.55 V, respectively.Figure 14a,b,d,e shows that C gs , C ds , C gd , g m , and g ds increase as N f and W f increase at the same bias condition.Figure 14c,f illustrates that R i and R gd decrease as N f and W f increase at the same bias condition.Figure 14 directly demonstrates the linear scaling rule adopted for pHEMT.The total gate width (W G ) is straightforwardly proportional to these two parameters: By doing so, we can build the scaling model for circuit design.To validate the scalability of the proposed model, a GaAs E-mode pHEMT PA (two-stage, with W f = 50 µm and N f = 8) has been designed and fabricated.Figure 15 shows the block diagram (left) of the power measurement setup and chip micrograph (right).One-tone large signal measurements were performed at different input driving levels.Figure 16 reveals good matching between the measured and simulated results of the output power for GaAs E-mode pHEMT PA at V cc = 4.5 V, V B1 = 1 V, V B2 = 0.9 V, and at frequency = 9, 10, 14, and 15 GHz, respectively.Figure 16 indicates the accuracy of the scaled nonlinear model and further verifies the effectiveness of the proposed extraction method.

Conclusions
The conventional "ColdFET" method determined R s and R d are not accurate in GaAs E-mode pHEMTs.In this letter, we propose an analytical method to extract R s and R d directly from S-parameter measurements of the target device.Including the bias dependence of R s and R d in small signal modeling has significant impacts on the accuracy of the GaAs E-mode pHEMTs model.The proposed method is verified in both S-parameter simulation and on-wafer measurement, which achieves a good accuracy in a frequency range of 0.5-40 GHz.Furthermore, this paper develops a GaAs E-mode pHEMT PA for verification.The fundamental output power at 9-15 GHz has been measured, which indicates the accuracy of the model and the effectiveness of the proposed extraction method.In this paper, the parasitic element values (i.e., C pg , C pd , C pgd , L g , L d , L s , R g ) can be derived with high accuracy.According to Equation (A1), the relative sensitivity of 1/(1 + C gs /C gd ), which is related to imag(Z 21 ) and imag(Z 22 ), can be expressed as: The relative sensitivity of A can be expressed as: Once S-parameters have been measured and parameters have been extracted by the proposed method, the corresponding uncertainties can be estimated.

Figure 1 .
Figure 1.Small signal equivalent circuits used for extraction.Equivalent circuit of pHEMT in strong inversion at V ds = 0 V (left).Simplified circuit for calculation of Z 22 (right).

Figure 2 .
Figure 2. Measured data and linear regression to calculate C x and R ch for a pHEMT.
(a) Measurement setup for S-parameters, block diagram (left) and photograph (right).(b) Measurement setup for power, block diagram (left) and photograph (right).

Figure 3 .
Figure 3. Measurement setup to perform RF measurements under different bias conditions.Block diagram and photograph for S-parameters (a) and power (b); the inset is the photograph of the 4 × 50 µm GaAs E-mode pHEMTs chip.VNA, vector network analyzer.

Figure 4 .
Figure 4.The pHEMT's small-signal equivalent circuit model shows the extrinsic and intrinsic elements.

Figure 6 .
Figure 6.The value of A against V gs .

Figure 7 .
Figure 7.The extracted R d and R s against V gs , in which R d changes about 239% and R s changes about 270% with V gs from 0.25 V-0.7 V.

Figure 8 .
Figure 8. Intrinsic element characteristics of the small-signal equivalent circuit for pHEMT as a function of gate-to-source and drain-to-source voltage (V).

Figure 9 .
Figure 9.Comparison between simulated (symbol) and measured (solid) S-parameters before (red) and after (blue) applying the "open-short" de-embedding procedure for pHEMT at four different bias conditions, where the DUT operates from the pinch-off region to the saturation region.

Figure 10 .
Figure 10.The values of g m for pHEMT at four different bias conditions, where the DUT operates from the pinch-off region to the saturation region.
(a) E 11 at various biases.(b) E 12 at various biases.(c) E 21 at various biases.(d) E 22 at various biases.

Figure 11 .
Figure 11.Errors between simulated and measured S-parameters.

Figure 12 .
Figure 12.The total percentage error E total between simulated and measured models.

Figure 13 .
Figure 13.Comparison between modeled and measured P out and gain as functions of available input power (P in ) for V ds = 4 V and V gs = 0.55 V.
(a) C gs , C ds , C gd versus N f .(b) g m , g ds versus N f .(c) R i , R gd versus 1/N f .(d) C gs , C ds , C gd versus W f .(e)g m , g ds versus W f .(f) R i , R gd versus 1/W f .

Figure 14 .
Figure 14.Plots of C gs , C ds , C gd , R i , R gd , g m , and g ds with respect to N f and W f at V ds = 4 V and V gs = 0.55 V, respectively.

Figure 15 .
Figure 15.Experimental setup to perform power amplifier (PA) measurements under frequency = 9-15 GHz, V cc = 4.5 V, V B1 = 1 V, V B2 = 0.9 V; block diagram (left) of power; the right is the photograph of PA.

Figure 16 .
Figure 16.Comparison results of the GaAs E-mode pHEMT PA module.