2 ppm / ◦ C 81 nW High PSRR Dual-Output Voltage Reference for Portable Biomedical Application

Abstract: A dual-output voltage reference circuit with two reference voltages of 281 mV (Vref1) and 320.5 mV (Vref2) is presented in this paper. With a novel and precise circuit structure, the proposed circuit, operating in the subthreshold region, integrates two different output voltages into a circuit to form a dual-output voltage reference, and cascode current mirrors are used to enhance the power supply rejection ratio (PSRR). The proposed circuit was designed in a standard 0.18-μm CMOS process and has a series of attractive features: low-temperature coefficient (TC), high-PSRR, low-Line sensitivity (LS), small-chip area and low-power consumption. Monte Carlo simulations for 2000 samples showed that the output voltages 281 mV and 320.5 mV had a variation coefficient of 1.73% and 1.44%, respectively. The minimum power consumption was 84.1 nW at 0.9 V supply, proving that the circuit is suitable for portable biomedical application. The active area of the proposed voltage reference was only 0.0086 mm2.


Introduction
With the development of human body area networks such as wearable medical devices and medical measurements, a serious challenge is put forward to low-power and high-performance ICs [1].As an essential module in analog and digital circuit systems, multiple output voltage references have been the most important part of low-power and high-performance ICs, and have been attracting increasing attention.
In recent years, even though several voltage references have been developed, traditional voltage references have many problems.In the literature [2], the traditional bandgap reference, which adopts BJTs, can generate stable voltage.However, this kind of circuit consumes too much area and power, and only has one output voltage, which cannot satisfy the development of ultra-low power and high-performance applications.In the literature [3], multiple circuits are used to generate multiple output voltages, which consists of two different start-up circuits, two different current reference circuits, and two different voltage reference circuits.Even though this technique can achieve dual-output voltage reference, this technique has many limitations, such as the structure of the circuit is complex, and the chip area and power consumption are larger.In the literature [4], the characteristics of subthreshold MOSFETs is used to build a low power voltage reference without resistors.Although this effectively reduces the power consumption and temperature coefficient, the PSRR is not ideal.In the literature [5], a method to improve the PSRR by using the structure of feedback loop is presented, but the TC is not ideal, this technique cannot achieve dual-output voltage reference, and the overall power consumption of the circuit is larger.None of these circuits [1][2][3][4][5] meet the requirements for low power, low voltage, high precision, low area, and compatibility of CMOS process.
To overcome the existing mentioned problem, and to improve the overall performance of the multiple voltage reference, a novel and precise dual-output voltage reference circuit with low power consumption, low TC and high PSRR is proposed in this paper.The proposed circuit architecture consists of one start-up circuit, one current reference circuit, and two different simpler voltage reference circuits.The proposed voltage reference circuit is smaller and simpler.

Circuit Design
The proposed dual-output voltage reference circuit is illustrated in Figure 1.It consists of two parts, namely a start-up circuit and a core dual-output voltage reference circuit, and transistors of dual-output voltage reference circuit are operating in subthreshold region, except transistors of start-up circuit.characteristics of subthreshold MOSFETs is used to build a low power voltage reference without resistors.Although this effectively reduces the power consumption and temperature coefficient, the PSRR is not ideal.In the literature [5], a method to improve the PSRR by using the structure of feedback loop is presented, but the TC is not ideal, this technique cannot achieve dual-output voltage reference, and the overall power consumption of the circuit is larger.None of these circuits [1][2][3][4][5] meet the requirements for low power, low voltage, high precision, low area, and compatibility of CMOS process.
To overcome the existing mentioned problem, and to improve the overall performance of the multiple voltage reference, a novel and precise dual-output voltage reference circuit with low power consumption, low TC and high PSRR is proposed in this paper.The proposed circuit architecture consists of one start-up circuit, one current reference circuit, and two different simpler voltage reference circuits.The proposed voltage reference circuit is smaller and simpler.

Circuit Design
The proposed dual-output voltage reference circuit is illustrated in Figure 1.It consists of two parts, namely a start-up circuit and a core dual-output voltage reference circuit, and transistors of dual-output voltage reference circuit are operating in subthreshold region, except transistors of start-up circuit.

Core double voltage reference circuit
The first voltage reference Vref1 The second voltage reference Vref2

Start-up Circuit
The start-up circuit is composed of M1, M2, M3, M4 and capacitor C0.When the system works normally, it will turn-off the start-up circuit and can reduce power consumption.The start-up circuit is used to obtain start-up current and get rid of the degenerate bias points.

Current Source Circuit
The Current source circuit is used to provide bias current for dual-output voltage reference circuit.M5 and M6, operating in the subthreshold region with the same aspect ratio, is a cascode current mirror.The bias current of the current source circuit is copied to the core dual voltage reference circuit through the cascode current mirror.The current, which is generated by the MOS operating in the subthreshold region, is nano-ampere magnitude [6].
The current-voltage (I-V) characteristic of MOSFETs in the subthreshold region is expressed as [7]: ID is the drain-current, K is the aspect ratio of the MOSFETs, VGS is the gate-source voltage, VDS is the drain-source voltage, VTH is the threshold voltage, η is the sub-threshold slope factor, I0 =

Start-up Circuit
The start-up circuit is composed of M1, M2, M3, M4 and capacitor C 0 .When the system works normally, it will turn-off the start-up circuit and can reduce power consumption.The start-up circuit is used to obtain start-up current and get rid of the degenerate bias points.

Current Source Circuit
The Current source circuit is used to provide bias current for dual-output voltage reference circuit.M5 and M6, operating in the subthreshold region with the same aspect ratio, is a cascode current mirror.The bias current of the current source circuit is copied to the core dual voltage reference circuit through the cascode current mirror.The current, which is generated by the MOS operating in the subthreshold region, is nano-ampere magnitude [6].
The current-voltage (I-V) characteristic of MOSFETs in the subthreshold region is expressed as [7]: I D is the drain-current, K is the aspect ratio of the MOSFETs, V GS is the gate-source voltage, V DS is the drain-source voltage, V TH is the threshold voltage, η is the sub-threshold slope factor, q is the elementary charge, µ = µ 0 (T 0 /T) m is the carrier mobility, in which µ 0 is the electron migration rate of MOSFETs at room temperature, T 0 is reference temperature, T is the absolute temperature, and m is the mobility temperature exponent [8,9].When V DS > 4V T , the effect of V DS can be ignored, and Equation ( 1) is simplified as Equation (2).
V GS in the subthreshold region can be expressed as Equation (3).
In Figure 1, the current source circuit current I D is obtained by R1, M11 and M12, and can be expressed as Equation ( 4).
From the above equation, the relationship between the current source circuit current I D and the temperature can be expressed as Equation (5).
Current I D is copied from current source circuit to voltage reference circuit by setting a proper aspect ratio of the current mirror; a bias current is provided for M13-M20 in voltage reference circuit.

The Vref1 Generator Circuit
The first voltage reference Vref1 is shown in Figure 1; the formula of the output Vref1 can be obtained as Equation ( 6) [10].
V TH = V TH0 − kT is the threshold voltage.When m = 0, we can obtain the relationship between the first output reference voltage Vref1 and the temperature as Equation (7).
Solving for dVref1/dT = 0, the condition of zero temperature drift of the output voltage can be obtained as Equation (8). ln From Equation ( 8), we can see that the first output reference voltage Vref1 with low temperature coefficient can be produced, with proper adjustment of K 11 , K 12 , K 20 and R 1 .

The Vref2 Generator Circuit
The second voltage reference Vref2 is shown in Figure 1.Low Temperature coefficient of Vref2 is generated by the difference voltage between the gate-source voltages of 3.3-V MOS transistor M17 and 1.8-V MOS transistor M18, and overdrive voltages of 1.8-V MOS transistor M 13 , M 14 , M 15 , and M 16 .The output Vref2 can be obtained as Equation ( 9) [4].
∆V TH = V TH17 − V TH18 is the difference of V TH with negative temperature coefficient, V T = k B T/q is the thermal voltage with positive temperature coefficient, so the voltage reference Vref2 with low temperature coefficient can be produced.V OVi is the overdrive voltage of M i .t OX,i is the oxide thickness of M i .κ = dV TH /dT is the temperature coefficient of V TH , as Equation (11), where E g is the bandgap, ε Si is the relatively dielectric constant of Si-substrate, N C is the effective density of states of conduction band, and N V is the effective density of states of valence band.
V TH can be expressed as Equation (12).
The relationship between the voltage reference Vref2 and the temperature can be expressed as Equation (13).
Solving for dVref2/dT = 0, the condition of zero temperature drift of the output voltage can be obtained as Equation ( 14).
With proper adjustment of K 13 , K 14 , K 15 , K 16 , K 17 and K 18 , the voltage reference Vref2 with low temperature coefficient can be produced.
Table 1 provides the dimensions of key components in the proposed circuit, including the aspect ratio of transistors and resistance value.

Simulation Results
The proposed dual-output voltage reference circuit was designed in TSMC 0.18-µm CMOS process.Figure 2 shows the layout of this circuit, which has an area of 362.6 × 282.4 µm 2 , and an enlarged view of the core circuit, which takes an active area of 103.1 × 84.1 µm 2 .
With proper adjustment of K13, K14, K15, K16, K17 and K18, the voltage reference Vref2 with low temperature coefficient can be produced.
Table 1 provides the dimensions of key components in the proposed circuit, including the aspect ratio of transistors and resistance value.

Simulation Results
The proposed dual-output voltage reference circuit was designed in TSMC 0.18-µm CMOS process.Figure 2 shows the layout of this circuit, which has an area of 362.6 × 282.4 µm 2 , and an enlarged view of the core circuit, which takes an active area of 103.1 × 84.1 µm 2 .To evaluate the performance of the proposed voltage reference and validate the design procedure, a series of simulations was carried out with the aid of SPICE simulator using TSMC 0.18-µm Mixed Signal/RF technology.Using the device's mismatch model, Monte Carlo simulation To evaluate the performance of the proposed voltage reference and validate the design procedure, a series of simulations was carried out with the aid of SPICE simulator using TSMC 0.18-µm Mixed Signal/RF technology.Using the device's mismatch model, Monte Carlo simulation was run over a set of 2000 samples on a typical process corner and at room temperature.The results are illustrated in Figure 3.The mean values of the dual-output voltages Vref1 and Vref2 were 281.28 mV with a variation coefficient of 1.73% and 320.52 mV with a variation coefficient of 1.44%, respectively.was run over a set of 2000 samples on a typical process corner and at room temperature.The results are illustrated in Figure 3.The mean values of the dual-output voltages Vref1 and Vref2 were 281.28 mV with a variation coefficient of 1.73% and 320.52 mV with a variation coefficient of 1.44%, respectively.A series of simulations was done to verify the performance of the proposed voltage reference.Figures 4 and 5 show the simulation results in different process corners.A series of simulations was done to verify the performance of the proposed voltage reference.Figures 4 and 5 show the simulation results in different process corners.A series of simulations was done to verify the performance of the proposed voltage reference.Figures 4 and 5 show the simulation results in different process corners.

Figure 2 .
Figure 2. Layout of the dual-output voltage reference circuit.

Figure 2 .
Figure 2. Layout of the dual-output voltage reference circuit.

Table 1 .
Device size of the proposed circuit.

Table 1 .
Device size of the proposed circuit.