A Reformatory Model Incorporating PNGV Battery and Three-Terminal-Switch Models to Design and Implement Feedback Compensations of LiFePO 4 Battery Chargers

This study developed and implemented a LiFePO4 battery pack (LBP) rapid charger. Using the three-terminal switch and partnership for a new generation of vehicles (PNGV) battery models, this study could obtain a small-signal system matrix to derive transfer functions and further analyze frequency responses for the charge voltage and current loops; therefore, both voltage and current feedback controllers could be designed to fulfill the constant-voltage (CV) and constant-current (CC) charges. To address practical applications, the proposed equivalent model also considered the wire resistance-inductance of the power cable. According to the derived high-order transfer function, the pole-zero break frequency in the Bode plot was observed that approximated the practical measurement; therefore, the pole-zero compensation could be accomplished for both charge loop requirements. Moreover, the design features for implementing the CV and CC charges are presented in detail herein, and the current overshoot during the start-up phase could be mitigated using the method of zero break frequency shifting and a novel proportional shifting proportional-integral control. The LBP parameter estimations, model construction processes, and frequency response analyses are also presented. The feedback compensation design based on the proposed model was validated through simulations and experiments. The results were determined to be in excellent agreement with theoretical derivations.


Introduction
The greenhouse effect, resulting in climate change, has become a major problem, and ecofriendly technologies for producing clean energy are paramount to alleviating greenhouse gas emissions.Commonly-used rechargeable batteries including lead-acid, Ni-Cd, Ni-MH, and Li-ion batteries have been applied in smartphones, laptops, electric screwdrivers, and other portable instruments as well as in electric forklifts and other electric vehicles.Compared with other secondary batteries, Li-ion batteries have the highest power and energy density [1]; therefore, Li-ion cells inside a battery pack are a suitable choice for electric vehicles [1][2][3].
The Lithium iron phosphate (LiFePO 4 ) is suitable for the positive electrode material in batteries because the strong P-O covalent bonds in the LiFePO 4 lattices do not decompose easily.The LiFePO 4 battery possesses excellent thermal stability; even under high-temperature or overcharge conditions, they rarely overheat because the LiFePO 4 lattice does not easily collapse and oxidize.Moreover, LiFePO 4 batteries are suitable for powering electric vehicles because they offer multicycle charge/discharge and nontoxicity [4][5][6].However, the energy density of LiFePO 4 battery is lower than LiMn 2 O 4 and LiCoO 2 batteries.
The constant-voltage (CV) and constant-current (CC) outputs of rapid chargers are necessary functions for the charge of large-capacity LiFePO 4 battery pack (LBP).To accomplish CV and CC charges, the voltage feedback controller (VFC) and current feedback controller (CFC) must be designed based on the frequency responses of charge loops.The battery electrical model is a critical role because a suitable model can present a practical frequency response.The suitable electrical model for a Li-ion battery include the R int model, the resistance-capacitance (RC) model, the Thevenin model, the modified Thevenin model, and the Partnership for a New Generation of Vehicles (PNGV) battery model [7][8][9].The PNGV battery model [10][11][12] was adopted in this study because its parameters can be estimated using the pulse-current charge method to obtain the battery voltage-time characteristic, and the formula for the electric charge can be adopted to calculate the model parameter [10].
In this study, the developed LBP rapid charger (LBPRC) comprised a safety-standard circuit, a power factor corrector, and a DC-DC converter.The topology of the DC-DC converter was a phase-shifted full-bridge with parallel current-doubler rectification (PSFB-PCDR) incorporating the VFC and CFC to achieve the CV or CC output mode.In addition, a three-terminal switch (TTS) model was applied to simplify the PSFB-PCDR [13][14][15].Moreover, studies [16][17][18][19] have mentioned several charge strategies for rechargeable batteries.In [16], the power stage topology of the battery charger was a boost converter, which could step up the low input voltage from the photovoltaic cell, and using the control technologies of the maximum power point tracking and the pulse-charge scheme, the fast maximum power point tracking could be achieved during a narrow charge period.In [17], the battery charge combined the bridgeless power factor correction (PFC) with the PSFB converter; this power topology design could easily achieve the series or parallel combination of battery charger for electric vehicle applications.Moreover, the CC-CC-CV charge strategy was applied; this charge method should be effective to extend the LiFePO 4 battery lifespan.In [18], a two-switch buck converter was used as the power stage topology, which could be applied in an electrically controlled pneumatic brake system; the CC-CV charge strategy was implemented to charge the LiFePO 4 battery.In [19], the series resonant converter with the synchronous rectification was the power stage topology of battery charger; the charge strategy adopted the CC-CV method.From [16][17][18][19], comparisons of power converter topologies and charge strategies are listed in Table 1.  Figure 2a illustrates the system measurement configuration for estimating the parameter of the PNGV battery model.The LBPRC inlet was an AC source input, and the positive/negative electrode of the LBP was connected to the LBPRC outlet.The voltage-date collector GL240 (Graphtec Corp., Totsuka-ku, Yokohama, Japan) can be used to record the LBP voltages every 10 ms (the minimum sampling time of the GL240) and transmit them to the computer via USB; therefore, the LBP adopting a pulse-current charge method can obtain the voltage-time characteristics, as depicted in Figure 2b.
Both results produced by the charge equation and the Ohm's law can be used to calculate the parameter of the PNGV battery model.

Battery Capacity Capacitance
In this study, Cx represents the LBP capacity that can be expressed as Cx = ibat × ∆t / ∆vbat [10], this equation is from the charge ∆Q = Cx × ∆vbat = ibat × ∆t; the ∆vbat is the LBP voltage variation with the time interval ∆t; the ibat is the pulse-current peak.During the time interval [t2:t3], the LBP is charged by a pulse-current, hence the ∆t equals to t3 − t2.Moreover, because of the LBP is affected by the tardy ion diffusion process, the LBP open-loop voltage needs an emancipated time to recovery after the charge stop, and therefore, the ∆vbat equals to the LBP's voltage difference v5-v1 (Figure 2b).As a result, the Cx can be rewritten as follows: It is noticeable that the LBP voltage from v3 to v4 has a time delay from t3 to 3 t ′ , because the minimum sampling time of the GL240 should be considered.However, this time delay does not affect the Cx estimation.

Ohmic Internal Resistance
When the Li-ion battery is charged or discharged, migratory electrons pass through metallic elements and chemical materials; these substances inside the Li-ion batteries are similar to a resistance obstructing the electron movement, hence the PNGB battery model using the Roir (Figure 1) represents the LBP internal resistance.Moreover, the phenomenon of ohmic voltage drops occurring at the charge start (at t2) and stop (at t3) times are caused by the Roir; at t2 and t3, the Roir can be expressed as the Roir(st) and Roir(sp), respectively.According to the literature [10] and Ohm's law, the Roir(st) and Roir(sp) are respectively expressed as follows:

Battery Capacity Capacitance
In this study, C x represents the LBP capacity that can be expressed as C x = i bat × ∆t/∆v bat [10], this equation is from the charge ∆Q = C x × ∆v bat = i bat × ∆t; the ∆v bat is the LBP voltage variation with the time interval ∆t; the i bat is the pulse-current peak.During the time interval [t 2 :t 3 ], the LBP is charged by a pulse-current, hence the ∆t equals to t 3 − t 2 .Moreover, because of the LBP is affected by the tardy ion diffusion process, the LBP open-loop voltage needs an emancipated time to recovery after the charge stop, and therefore, the ∆v bat equals to the LBP's voltage difference v 5 −v 1 (Figure 2b).As a result, the C x can be rewritten as follows: It is noticeable that the LBP voltage from v 3 to v 4 has a time delay from t 3 to t 3 , because the minimum sampling time of the GL240 should be considered.However, this time delay does not affect the C x estimation.

Ohmic Internal Resistance
When the Li-ion battery is charged or discharged, migratory electrons pass through metallic elements and chemical materials; these substances inside the Li-ion batteries are similar to a resistance obstructing the electron movement, hence the PNGB battery model using the R oir (Figure 1) represents the LBP internal resistance.Moreover, the phenomenon of ohmic voltage drops occurring at the charge start (at t 2 ) and stop (at t 3 ) times are caused by the R oir ; at t 2 and t 3 , the R oir can be expressed as the R oir(st) and R oir(sp) , respectively.According to the literature [10] and Ohm's law, the R oir(st) and R oir(sp) are respectively expressed as follows: where v 2 − v 1 and v 3 − v 4 represent the LBP voltage differences.From practical measurement and estimation, R oir(st) can approximate to R oir(sp) .To simplify this study derivations, the equation [R oir(st) + R oir(sp) ]/2 can be used to obtain an average R oir for further analyses and designs.

Polarization Capacity Capacitance and Internal Resistance
Because of the charge transfer and diffusion of electrochemical reaction inside the battery, the v 2 exponentially changes to v' 2 during the time interval [t 2 :t 2 ].Moreover, the resistance-capacitance time constant τ can be obtained by the R t × C t , this rule can refer to the literature [7,10,25].From [10], C t can be expressed as τ/R t , R t can be calculated as follows: The time constant τ was undefined in [10].However, according to the definition of the resistance-capacitance time constant, complete response of an exponential corresponds to 5τ, hence the capacitance can be charged to 95% of the applied voltage.In this study, the 5τ = t 2 − t 2 is defined.Therefore, substituting the 5τ = t 2 − t 2 and C t = τ/R t can yield an expression as follows: It is noticeable that the LBP voltage from v 1 to v 2 has a time delay from t 2 to t 2 , because the minimum sampling time of the GL240 should be considered.However, this time delay does not affect both R t and C t estimations.

Open-Circuit Voltage
v ocv can be regarded as a short circuit in the small-signal analysis.Therefore, the v ocv is irrelevant to the parameter estimation in this study.

Battery Specification and Measurement
In this study, the model number of the LiFePO 4 cell is LYS4882160S(3005) (Lyang Energy Tech. Corp., Dongguan, China), and its specifications are listed in Table 3.As shown in Figure 2, the pulse-current peak was set to 17.5 A (0.5 C).For state of charges (SOCs) 30%, 50%, and 70%, the measured voltage-time characteristics are presented in Figure 3.The voltages and times are recorded in Table 4 in line with the definition in Figure 2b.Substitution of Table 4 parameters into (1)-( 5) could yield the parameters for the PNGV battery model that listed in Table 5. SOCs 30%, 50%, and 70%, were selected, the reasons explained as follows: First, for the LBP, its equivalent electrical parameters based on the PNGV battery model should be measured to observe the system responses for the low, half, and high SOCs.Second, for the LBPRC, the charge system would result in different frequency responses under the light, medium, and heavy loads.In Figure 4, the TTS model can replace the circuit inside the a-frame, as illustrated in Figure 5a.This model has a dependent voltage source v r , two current sources (i r1 and i r2 ), and a resistance R eqs .The V inps can be reflected to the T 1 secondary side becoming v r , as follows:

Small-Signal System Matrix
where n is the T 1 turns ratio, it equals to the formula N p /N s1 = N p /N s2 .The rising and falling slopes of the T 1 input current indicate that they are affected by the PSFB-PCDR operating switching frequency f sw and transformer leakage inductance L k .According to the method from the [15], using an equivalent resistance R eqs can model the slope change.Therefore, the R eqs is given by side voltage vtp across T1; the Tsw is the operating switching period for va to vd; the dy represents the PSFB-PCDR operating duty cycle ratio.
In Figure 4, the TTS model can replace the circuit inside the a-frame, as illustrated in Figure 5a.This model has a dependent voltage source vr, two current sources (ir1 and ir2), and a resistance Reqs.The Vinps can be reflected to the T1 secondary side becoming vr, as follows: where n is the T1 turns ratio, it equals to the formula Np / Ns1 = Np / Ns2.The rising and falling slopes of the T1 input current indicate that they are affected by the PSFB-PCDR operating switching frequency fsw and transformer leakage inductance Lk.According to the method from the [15], using an equivalent resistance Reqs can model the slope change.Therefore, the Reqs is given by  Because of fsw, Lk and n are fixative values in the design, and the derivation of the system transfer function will focus on the LPBRC output voltage and current to the operating duty cycle; therefore, using (7) to represent the dynamic influence of Lk can be acceptable.
The PSFB-PCDR secondary-side operations can be regarded as the buck converter, and the Lcdr1 to Lcdr4 have the same inductance value; therefore, the four inductances can be treated as parallel connections, and they can be expressed as an inductance Lcdr.As a result, the output inductance Lo equals to Lcdr/4 [13,14,26].Moreover, the Co contains an equivalent series resistance Resr.
A CV or CC power replenishes the LBP by way of the power cable; the wire resistanceinductance would influence the gain and phase of the system frequency response.Therefore, the model considers the wire resistance Rc and inductance Lc, which lie between the PSFB-PCDR outlet and LBP.The illustration in Figure 5b is an equivalent circuit.Because of f sw , L k and n are fixative values in the design, and the derivation of the system transfer function will focus on the LPBRC output voltage and current to the operating duty cycle; therefore, using (7) to represent the dynamic influence of L k can be acceptable.
The PSFB-PCDR secondary-side operations can be regarded as the buck converter, and the L cdr1 to L cdr4 have the same inductance value; therefore, the four inductances can be treated as parallel connections, and they can be expressed as an inductance L cdr .As a result, the output inductance L o equals to L cdr /4 [13,14,26].Moreover, the C o contains an equivalent series resistance R esr .
A CV or CC power replenishes the LBP by way of the power cable; the wire resistance-inductance would influence the gain and phase of the system frequency response.Therefore, the model considers the wire resistance R c and inductance L c , which lie between the PSFB-PCDR outlet and LBP.The illustration in Figure 5b is an equivalent circuit.
In Figure 5b, the R c connects with the R oir in series; hence, R c + R oir equal to R x .The final equivalent circuit, depicted in Figure 5c, is in accordance with these conditions.Using Kirchhoff's voltage and current laws and the mesh-current method, the loop equations can be obtained as follows: i Co = i p − i bat (10) The LBPRC voltage can be expressed as: Substitution of (6) and v Lo = L o (di p /dt) in (8), v Lc = L c (di bat /dt) in (9), and i Ct = C t (dv ct /dt) in (11), the state-space representations can be expressed as follows: ) The state-space variables can accede to a DC value plus a small-signal perturbation; therefore, substitution of i p = I p + i p , 13)-( 17) can yield the small-signal system matrix of PSFB-PCDR as follows:   6.
Substitution of ( 6) and vLo = Lo(dip / dt) in (8), vLc = Lc(dibat / dt) in (9), and iCt = Ct(dvct / dt) in (11), the state-space representations can be expressed as follows: The state-space variables can accede to a DC value plus a small-signal perturbation; therefore, substitution of ip = Ip +        6a is the developed charge system's configuration.From Figure 6a, the open-loop block diagram of charge voltage is illustrated in Figure 6b, where the charge voltage gain of PSFB-PCDR is the G psfbv and the PSFB controller gain is the G cltr .Using the characteristic equation and matrix, (18) and (19), can yield the following transfer function: According to (21) and (23), the transfer function of the charge voltage in open-loop condition can be obtained as follows:  When the DC charge current is 17.5 A, the power cable must sustain this continuous current until LBP replenishment.To avoid the cable temperature rising over 75 • C, in this study, the length and diameter of the power cable were selected as 200 cm and 0.259 cm (No. 10 American wire gauge), respectively; in accordance with the data in [27,28], the R c = 6.55 mΩ and L c = 2.91 µH (Figure 5) can be obtained.According to the average parameters in Table 5, the R x = R c + R oir = 28.34mΩ.Substituting these parameters into Table 6 can yield the elements of matrices A, B, and C in ( 18) and ( 19).

Notation
Value Unit

µH
The characteristics of the operating duty cycle d y with input voltage v i is illustrated in Figure 7. Using the MATLAB curve-fitting function, a linear polynomial can be expressed as follows: Using MATLAB, the frequency response simulation of Gov (s) was completed and plotted in Figure 8.In this Bode plot, the low-frequency gain (LFG) was 11.4 dB, and the bandwidth (BW) was 237 Hz.The frequency and phase at 0 dB were 1.7 kHz and −49.9°, respectively.Moreover, in this study, the TTS model with the PNGV battery model in the LBPRC application is proposed for the first time, along with the complete design procedures for the CV and CC feedback compensations.Therefore, the gain and phase slopes in three bands 0.1 to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, can be observed to compare and confirm the proposed model, which is feasible.At 0.1 to 1 kHz, the gain and phase slopes were −10.85 dB/decade and −31.4°/decade, respectively.At 1 to 10 kHz, the gain and phase slopes were 6.15 dB/decade and 15.7°/decade; at 10 to 100 kHz, the gain and phase slopes were −27.3 dB/decade and −92.5°/decade.
Furthermore, break frequencies included fopv1 = 98.04 Hz (pole), fozv1 = 1.05 kHz (zero), and fopv2 = 9.8 kHz (pole).From Figure 8, several circumstances could be observed: 1) The steady-state error of charge voltage would be severe during the feedback operation, because the low-frequency gain of 11.4 dB was too low.2) A narrow bandwidth of 237 Hz was observed.
3) Two poles (fopv1 and fopv2) and one zero (fozv1) can be found in the Bode plot.
According to ( 21) and ( 23), the transfer function of the charge voltage in open-loop condition can be obtained as follows: Using MATLAB, the frequency response simulation of G ov (s) was completed and plotted in Figure 8.In this Bode plot, the low-frequency gain (LFG) was 11.4 dB, and the bandwidth (BW) was 237 Hz.The frequency and phase at 0 dB were 1.7 kHz and −49.9 • , respectively.Moreover, in this study, the TTS model with the PNGV battery model in the LBPRC application is proposed for the first time, along with the complete design procedures for the CV and CC feedback compensations.Therefore, the gain and phase slopes in three bands 0.1 to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, can be observed to compare and confirm the proposed model, which is feasible.At 0.1 to 1 kHz, the gain and phase slopes were −10.85 dB/decade and −31.4 • /decade, respectively.At 1 to 10 kHz, the gain and phase slopes were 6.15 dB/decade and 15.7 • /decade; at 10 to 100 kHz, the gain and phase slopes were −27.3 dB/decade and −92.5 • /decade.Furthermore, break frequencies included fopv1 = 98.04 Hz (pole), fozv1 = 1.05 kHz (zero), and fopv2 = 9.8 kHz (pole).From Figure 8, several circumstances could be observed: 1) The steady-state error of charge voltage would be severe during the feedback operation, because the low-frequency gain of 11.4 dB was too low.2) A narrow bandwidth of 237 Hz was observed.
3) Two poles (fopv1 and fopv2) and one zero (fozv1) can be found in the Bode plot.

Comparison of Frequency Response Using the Different SOC Parameters and the Battery Model
From Table 5, different SOC parameters resulted in different frequency responses of Gov (s), as illustrated in Figure 9a.Expanding the magnitude and phase scales from Figure 9a, it could be observed that three SOC (30%, 50%, and 70%) frequency responses approximated to the average Furthermore, break frequencies included f opv1 = 98.04 Hz (pole), f ozv1 = 1.05 kHz (zero), and f opv2 = 9.8 kHz (pole).From Figure 8, several circumstances could be observed: (1) The steady-state error of charge voltage would be severe during the feedback operation, because the low-frequency gain of 11.4 dB was too low.(2) A narrow bandwidth of 237 Hz was observed.
(3) Two poles (f opv1 and f opv2 ) and one zero (f ozv1 ) can be found in the Bode plot.

Comparison of Frequency Response Using the Different SOC Parameters and the Battery Model
From Table 5, different SOC parameters resulted in different frequency responses of G ov (s), as illustrated in Figure 9a.Expanding the magnitude and phase scales from Figure 9a, it could be observed that three SOC (30%, 50%, and 70%) frequency responses approximated to the average result (blue solid-line).Therefore, the proposed PNGV battery model in this study can employ the average value (Table 5) to analyze and simulate the system Bode plot.
Electronics 2018, 7, x FOR PEER REVIEW 12 of 29 result (blue solid-line).Therefore, the proposed PNGV battery model in this study can employ the average value (Table 5) to analyze and simulate the system Bode plot.
To compare the frequency response discrepancies in the PNGV model, the RC model, and the no-wire resistance-inductance, these simulations presented in Figure 10.From Figure 10, several circumstances can be observed that are described in the following.1) No-wire resistance-inductance: The Rc and Lc (Figure 5) were neglected; therefore, the Gov (s) from ( 24) could be replaced with the Gov1 (s).The phase of Gov1 (s) deviated the Gov (s) seriously, and the gain of Gov1 (s) was less than the Gov (s), the band ranges were from 20 to 100 kHz (Figure 10).2) Using the RC model: The Resr, Rc, Lc, Rt, and Ct (Figure 5) were neglected; therefore, the Gov (s) from ( 24) could be replaced with Gov2 (s).The gain and phase slopes for the Gov2 (s) could not present the break frequency changes, such as the pole-zero of Gov (s).From these simulations, the stability analysis and the pole-zero compensation were difficult to implement for the LBPRC design.Therefore, the LBPRC analysis adopting the PNGV battery model is a feasible method to obtain the system frequency response, and further to design the VFC and CFC for the CV and CC charges.The Bode plot of Gov (s) in practice will be measured; both simulation and measurement correspond to the anticipated result of the theory.

Open-Loop Gain of Charge Current
From Figure 6a, the open-loop block diagram of charge current is illustrated in Figure 6c, the Gpsfbc represents the charge current gain of PSFB-PCDR.Using the characteristic equation and matrix, ( 18) and ( 20), can obtain the following transfer function: (25) where the elements of matrix E can be obtained from Table 6.According to ( 23) and ( 25), the transfer function of charge current in open-loop condition can be obtained as follows:  To compare the frequency response discrepancies in the PNGV model, the RC model, and the no-wire resistance-inductance, these simulations presented in Figure 10.From Figure 10, several circumstances can be observed that are described in the following.
(1) No-wire resistance-inductance: The R c and L c (Figure 5) were neglected; therefore, the G ov (s) from ( 24) could be replaced with the G ov1 (s).The phase of G ov1 (s) deviated the G ov (s) seriously, and the gain of G ov1 (s) was less than the G ov (s), the band ranges were from 20 to 100 kHz (Figure 10).
(2) Using the RC model: The R esr , R c , L c , R t , and C t (Figure 5) were neglected; therefore, the G ov (s) from ( 24) could be replaced with G ov2 (s).The gain and phase slopes for the G ov2 (s) could not present the break frequency changes, such as the pole-zero of G ov (s).
Electronics 2018, 7, x FOR PEER REVIEW 13 of 29 Using MATLAB, the frequency response simulation of Goc (s) was completed and plotted in Figure 11.In this Bode plot, the low-frequency gain was 35.6 dB, and the bandwidth was 200 Hz.The frequency and phase at 0 dB were 50 kHz and −140°, respectively.Moreover, at 0.1 to 1 kHz, the gain and phase slopes were −10.8 dB/decade and −30.2°/decade; at 1 to 10 kHz, the gain and phase slopes were 7.7 dB/decade and 15.5°/decade, respectively; at 10 to 100 kHz, the gain and phase slopes were −4.9 dB/decade and −92.3°/decade, respectively.Furthermore, break frequencies included the fopc1 = 98.04 Hz (pole), fozc1 = 1.05 kHz (zero), and fopc2 = 9.8 kHz (pole).From Figure 11, three circumstances can be observed that are described in the following.1) A narrow bandwidth of 200 Hz was observed.

Open-Loop Frequency Response
Design considerations and procedures will be discussed in the following.

VFC for CV Charge
According to the simulation of Gov (Figure 8), the VFC design is as follows: 1) The low-frequency gain must be heightened to reduce the steady-state error of charge voltage.
2) The system bandwidth should be extended to accelerate the response speed.
3) The phase margin should be greater than −135° to ensure the stability of the CV charge loop.
In Figure 6a, the voltage divider and VFC circuit are illustrated as Figure 12a, including voltage divider resistances (Rvd1 and Rvd2), an operational amplifier OP1, a charge voltage reference command From these simulations, the stability analysis and the pole-zero compensation were difficult to implement for the LBPRC design.Therefore, the LBPRC analysis adopting the PNGV battery model is a feasible method to obtain the system frequency response, and further to design the VFC and CFC for the CV and CC charges.The Bode plot of G ov (s) in practice will be measured; both simulation and measurement correspond to the anticipated result of the theory.

Open-Loop Gain of Charge Current
From Figure 6a, the open-loop block diagram of charge current is illustrated in Figure 6c, the G psfbc represents the charge current gain of PSFB-PCDR.Using the characteristic equation and matrix, (18) and (20), can obtain the following transfer function: where the elements of matrix E can be obtained from Table 6.According to (23) and ( 25), the transfer function of charge current in open-loop condition can be obtained as follows: Using MATLAB, the frequency response simulation of G oc (s) was completed and plotted in Figure 11.In this Bode plot, the low-frequency gain was 35.6 dB, and the bandwidth was 200 Hz.The frequency and phase at 0 dB were 50 kHz and −140 • , respectively.Moreover, at 0.1 to 1 kHz, the gain and phase slopes were −10.8 dB/decade and −30.2 • /decade; at 1 to 10 kHz, the gain and phase slopes were 7.7 dB/decade and 15.5 • /decade, respectively; at 10 to 100 kHz, the gain and phase slopes were −4.9 dB/decade and −92.3 • /decade, respectively.Furthermore, break frequencies included the f opc1 = 98.04 Hz (pole), f ozc1 = 1.05 kHz (zero), and f opc2 = 9.8 kHz (pole).From Figure 11, three circumstances can be observed that are described in the following.
(1) A narrow bandwidth of 200 Hz was observed.
(2) The phase margin was less than −135 • (at 50 kHz), which has acceded to the allowable tolerance of 45 ; therefore, the charge current loop was regarded as unstable.
(3) Two poles (f opc1 and f opc2 ) and one zero (f ozc1 ) can be found in the Bode plot.

Open-Loop Frequency Response
Design considerations and procedures will be discussed in the following.

VFC for CV Charge
According to the simulation of Gov (Figure 8), the VFC design is as follows: 1) The low-frequency gain must be heightened to reduce the steady-state error of charge voltage.
2) The system bandwidth should be extended to accelerate the response speed.
3) The phase margin should be greater than −135° to ensure the stability of the CV charge loop.
In Figure 6a, the voltage divider and VFC circuit are illustrated as Figure 12a, including voltage divider resistances (Rvd1 and Rvd2), an operational amplifier OP1, a charge voltage reference command Vrefv, resistances (Rfv1 and Rfv2), and capacitances (Cfv1 and Cfv2).The control block diagram of charge

Open-Loop Frequency Response
Design considerations and procedures will be discussed in the following.

VFC for CV Charge
According to the simulation of G ov (Figure 8), the VFC design is as follows: (1) The low-frequency gain must be heightened to reduce the steady-state error of charge voltage.
(2) The system bandwidth should be extended to accelerate the response speed.
(3) The phase margin should be greater than −135 • to ensure the stability of the CV charge loop.
In Figure 6a, the voltage divider and VFC circuit are illustrated as Figure 12a, including voltage divider resistances (R vd1 and R vd2 ), an operational amplifier OP 1 , a charge voltage reference command V refv , resistances (R fv1 and R fv2 ), and capacitances (C fv1 and C fv2 ).The control block diagram of charge voltage in closed-loop operation is depicted in Figure 12b.The k v is a constant that can be calculated by the formula R vd2 /(R vd1 +R vd2 ).The VFC gain is G vfc , whose transfer function is given by and its corner frequencies at the pole and zero, both are given in Moreover, g av represents the gain, it can be expressed as: From Figure 12b, a transfer function of the open-loop voltage is Substitution of k v = 0.073 and ( 24) in (31) yields G v (s), whose frequency response simulation is plotted in Figure 13.According to this Bode plot, the VFC design procedures can be performed to compensate the charge voltage loop.They are described in the following.
From Figure 12b, a transfer function of the open-loop voltage is Substitution of kv = 0.073 and ( 24) in (31) yields Gv (s), whose frequency response simulation is plotted in Figure 13.According to this Bode plot, the VFC design procedures can be performed to compensate the charge voltage loop.They are described in the following.

VFC Design Procedure
Step 1: Setting crossover frequency In the switching power supply applications, the crossover frequency range can be determined between fsw / 100 to fsw / 10.In this study, we considered the PNGV battery model for obtaining the frequency responses of Gov (s) and Goc (s).Therefore, the aforementioned crossover frequency range can be directly applied in the LBPRC design.
The crossover frequency of the charge voltage loop, fcov, can be set at the minimum frequency 1 kHz (fcov = fsw / 100 = 100k / 100), because the voltage-time change rate of charge voltage is slow.Moreover, to prevent the resonant factor from influencing the system stability, the fcov should be kept away from the output filter resonant frequency (fopv1 = 98.01 Hz); therefore, the frequency ranges can be expressed as fopv1 << fcov, as depicted in Figure 14.
Step 2: Gain heave at the crossover frequency According to Figure 13, at 1 kHz, the Gv should be hove from −22 to 0 dB; hence, the gv and Rfv1 of (30) can be set to 12.6 and 10 kΩ, respectively, and then Rfv2 = 126 kΩ can be obtained.Step 3: Pole break frequency of VFC To reduce the charge voltage ripple, the pole break frequency fpv must be less than fsw.Moreover, the phase margin should be increased if the fpv was greater than fcov.Therefore, substitution of the fpv = fsw / 2 = 50 kHz and Rfv2 = 126 kΩ into (29) can yield Cfv2 = 25.26 pF.Under these conditions, the frequency range can be expressed as fcov < fpv < fsw, as depicted in Figure 14.Step 4: Zero break frequency of VFC To prevent the phase shift from being less than −180°, the zero break frequency fzv should be less than fopv1.Thus, substitution of the fzv = fopv1 / 2 = 49 Hz and the Rfv2 = 126 kΩ into (28) can yield Cfv1 = 25.78 nF.Under these conditions, the frequency range can be expressed as fzv < fopv1, as depicted in Figure 14.
Moreover, the transfer function of closed-loop voltage gain, Gfbv (s), was simulated in Figure 13.From Figure 13, the feedback operation for the charge voltage loop could observe that the lowfrequency gain of Gfbv (s) was 22.7 dB; the phase was greater than −135° when the band ranges were from 1 to 26.8 kHz.
From Figure 13, the simulation could comprehend that the LBPRC incorporating the VFC could address the stable requirement for the CV charge.Two reasons explain as follows: 1) Determining the system stability from the phase of Gcomv (s) is a critical method which has been mentioned in previous studies [29,30] for the design of switching power supplies.Because the phase −51.1° of Gcomv (s) at 0 dB was greater than −135°, a stable charge voltage loop could be fulfilled.
2) It was a rational condition that the phase of Gfbv (s) was less than −135° at 0 dB, because the negative feedback operation may become unstable influencing the system stability in the high frequencies [31][32][33].However, from Figure 13, the bandwidth of Gfbv (s) was extended; this result was one of the advantages when the LBPRC operated in the negative feedback mode [32,33].

VFC Design Procedure
Step 1: Setting crossover frequency In the switching power supply applications, the crossover frequency range can be determined between f sw /100 to f sw /10.In this study, we considered the PNGV battery model for obtaining the frequency responses of G ov (s) and G oc (s).Therefore, the aforementioned crossover frequency range can be directly applied in the LBPRC design.
The crossover frequency of the charge voltage loop, f cov , can be set at the minimum frequency 1 kHz (f cov = f sw /100 = 100k/100), because the voltage-time change rate of charge voltage is slow.Moreover, to prevent the resonant factor from influencing the system stability, the f cov should be kept away from the output filter resonant frequency (f opv1 = 98.01 Hz); therefore, the frequency ranges can be expressed as f opv1 << f cov , as depicted in Figure 14.
Step 3: Pole break frequency of VFC To reduce the charge voltage ripple, the pole break frequency fpv must be less than fsw.Moreover, the phase margin should be increased if the fpv was greater than fcov.Therefore, substitution of the fpv = fsw / 2 = 50 kHz and Rfv2 = 126 kΩ into (29) can yield Cfv2 = 25.26 pF.Under these conditions, the frequency range can be expressed as fcov < fpv < fsw, as depicted in Figure 14.Step 4: Zero break frequency of VFC To prevent the phase shift from being less than −180°, the zero break frequency fzv should be less than fopv1.Thus, substitution of the fzv = fopv1 / 2 = 49 Hz and the Rfv2 = 126 kΩ into (28) can yield Cfv1 = 25.78 nF.Under these conditions, the frequency range can be expressed as fzv < fopv1, as depicted in Figure 14.
Moreover, the transfer function of closed-loop voltage gain, Gfbv (s), was simulated in Figure 13.From Figure 13, the feedback operation for the charge voltage loop could observe that the lowfrequency gain of Gfbv (s) was 22.7 dB; the phase was greater than −135° when the band ranges were from 1 to 26.8 kHz.
From Figure 13, the simulation could comprehend that the LBPRC incorporating the VFC could address the stable requirement for the CV charge.Two reasons explain as follows: 1) Determining the system stability from the phase of Gcomv (s) is a critical method which has been mentioned in previous studies [29,30] for the design of switching power supplies.Because the phase −51.1° of Gcomv (s) at 0 dB was greater than −135°, a stable charge voltage loop could be fulfilled.
2) It was a rational condition that the phase of Gfbv (s) was less than −135° at 0 dB, because the negative feedback operation may become unstable influencing the system stability in the high frequencies [31][32][33].However, from Figure 13, the bandwidth of Gfbv (s) was extended; this result was one of the advantages when the LBPRC operated in the negative feedback mode [32,33].Step 2: Gain heave at the crossover frequency According to Figure 13, at 1 kHz, the G v should be hove from −22 to 0 dB; hence, the g v and R fv1 of (30) can be set to 12.6 and 10 kΩ, respectively, and then R fv2 = 126 kΩ can be obtained.
Step 3: Pole break frequency of VFC To reduce the charge voltage ripple, the pole break frequency f pv must be less than f sw .Moreover, the phase margin should be increased if the f pv was greater than f cov .Therefore, substitution of the f pv = f sw /2 = 50 kHz and R fv2 = 126 kΩ into (29) can yield C fv2 = 25.26 pF.Under these conditions, the frequency range can be expressed as f cov < f pv < f sw , as depicted in Figure 14.
Step 4: Zero break frequency of VFC To prevent the phase shift from being less than −180 • , the zero break frequency f zv should be less than f opv1 .Thus, substitution of the f zv = f opv1 /2 = 49 Hz and the R fv2 = 126 kΩ into (28) can yield C fv1 = 25.78 nF.Under these conditions, the frequency range can be expressed as f zv < f opv1 , as depicted in Figure 14.
Substitution of the R fv1 =10 kΩ, R fv2 = 126 kΩ, C fv1 = 25.78 nF, and C fv2 = 25.26 pF into ( 27) and ( 31) could yield the transfer function of open-loop voltage gain for the LBPRC with the VFC, G comv (s), the frequency response simulation was plotted in Figure 13.From Figure 13, the low-frequency gain of G comv (s) was increased to 45.4 dB; at crossover frequency f cov = 1 kHz, the phase was −51.1 • , which was greater than −135 • and was over the tolerance of 45 • (|−180 • −135 • | = 45 • ), hence the proposed VFC design could meet the stability requirement.
Moreover, the transfer function of closed-loop voltage gain, G fbv (s), was simulated in Figure 13.From Figure 13, the feedback operation for the charge voltage loop could observe that the low-frequency gain of G fbv (s) was 22.7 dB; the phase was greater than −135 • when the band ranges were from 1 to 26.8 kHz.
From Figure 13, the simulation could comprehend that the LBPRC incorporating the VFC could address the stable requirement for the CV charge.Two reasons explain as follows: (1) Determining the system stability from the phase of G comv (s) is a critical method which has been mentioned in previous studies [29,30] for the design of switching power supplies.Because the phase −51.1 • of G comv (s) at 0 dB was greater than −135 • , a stable charge voltage loop could be fulfilled.(2) It was a rational condition that the phase of G fbv (s) was less than −135 • at 0 dB, because the negative feedback operation may become unstable influencing the system stability in the high frequencies [31][32][33].However, from Figure 13, the bandwidth of G fbv (s) was extended; this result was one of the advantages when the LBPRC operated in the negative feedback mode [32,33].

CFC for CC Charge
According to the simulation of G oc (Figure 11), the CFC design consideration is described as follows: (1) The low-frequency gain must be heightened to reduce the steady-state errors of charge current.
(2) The 0 dB frequency should be decreased because the initial 50 kHz was higher than the suggested frequency of 10 kHz (f sw /10).(3) The phase margin should be greater than −135 • to ensure the stable operation for the CC charge loop.
From Figure 6a, the signal amplifier (SA) and CFC circuit are illustrated in Figure 15a, including the current shunt R s , an operational amplifier OP 2 , a charge current reference command V refc , resistances (R fc1 and R fc2 ), and capacitances (C fc1 and C fc2 ), hence using the OP 2 , V refc , R fc1 , R fc2 , C fc1 , and C fc2 , can compose an error amplifier to implement a proportional-integral control.The control block diagram of charge current in the closed-loop operation is depicted in Figure 15b.The k c is a constant that can be calculated by the R s × g sa (DC gain of SA).The CFC gain is G cfc , whose transfer function is given by (32) and its corner frequencies at the pole and zero are both given in Moreover, g c represents the gain, it can be expressed as: From Figure 15b, the open-loop transfer function is Substitution of the k c = 0.097 and ( 26) in (36) can yield G c (s), whose frequency response simulation is plotted in Figure 16.According to this Bode plot, the CFC design procedure can be performed to compensate charge current loop.They are described in the following.
3) The phase margin should be greater than −135° to ensure the stable operation for the CC charge loop.
From Figure 6a, the signal amplifier (SA) and CFC circuit are illustrated in Figure 15a, including the current shunt Rs, an operational amplifier OP2, a charge current reference command Vrefc, resistances (Rfc1 and Rfc2), and capacitances (Cfc1 and Cfc2), hence using the OP2, Vrefc, Rfc1, Rfc2, Cfc1, and Cfc2, can compose an error amplifier to implement a proportional-integral control.The control block diagram of charge current in the closed-loop operation is depicted in Figure 15b.The kc is a constant that can be calculated by the Rs × gsa (DC gain of SA).The CFC gain is Gcfc, whose transfer function is given by and its corner frequencies at the pole and zero are both given in Moreover, gc represents the gain, it can be expressed as: From Figure 15b, the open-loop transfer function is Substitution of the kc = 0.097 and ( 26) in (36) can yield Gc (s), whose frequency response simulation is plotted in Figure 16.According to this Bode plot, the CFC design procedure can be performed to compensate charge current loop.They are described in the following.

CFC Design Procedure
Step 1: Setting crossover frequency The crossover frequency of charge current loop, fcoc, can be set to the minimum frequency 10 kHz (fcoc = fsw / 10 = 100k / 10) because the current-time change rate of charge current is fast.Moreover, to

CFC Design Procedure
Step 1: Setting crossover frequency The crossover frequency of charge current loop, f coc , can be set to the minimum frequency 10 kHz (f coc = f sw /10 = 100k/10) because the current-time change rate of charge current is fast.Moreover, to prevent the resonant factor from influencing the system stability, the f coc should be kept away from the output filter resonant-frequency (f opc1 = 98.01 Hz); therefore, the frequency ranges can be expressed as f opc1 << f coc , as depicted in Figure 17a.Figure 19a shows the CFC circuit with PSPI control composed of an operational amplifier OP3, compensative elements (Zin, Zfc1, and Zfc2), and the Io(ref).Using Zin and Zfc2 can yield the P gain to implement the P control; the Zin combines Zfc1 with Zfc2 can achieve the PI control.
Moreover, the shifting certification for the Scfc is defined as follows: During Phases I and II, the vcfco is greater than the Vcfci to cut in the Scfc, the integral component Zfc1 is invalid and the unique P control can be implemented through Zfc2 and Zin for the CFC.In Phase III, the Scfc is cut off, thus the CFC can employ the Zin, Zfc1, and Zfc2 to implement the PI control.Therefore, from the time interval [tp1:tp2] (Figure 19), the CFC control can shift from P to PI; this control method is effective to mitigate the charge current overshoot.Moreover, the designing parameters from Section 5.2.1 and 5.2.2 can completely apply to Zin, Zfc1, and Zfc2 without readjusting and redesigning.Step 2: Gain heave at the crossover frequency According to Figure 16, at 10 kHz, the G c should to be heaved from -2.25 to 0 dB.Therefore, the g c and R fc1 in (35) can be set to 1.296 and 10 kΩ, respectively.The R fc2 = 12.96 kΩ can then be obtained.
Step 3: Pole break frequency of CFC To reduce charge current ripple, the pole break frequency f pc must be less than f sw .Moreover, the phase margin should be increased if the f pc is greater than f coc .Therefore, substitution of the f pc = f sw /4 = 25 kHz and R fv2 = 12.96 kΩ into (34) can yield C fc2 = 491.22pF.Under these conditions, the frequency range can be expressed as f coc < f pc < f sw , as depicted in Figure 17a.
Step 4: Zero break frequency setting of CFC To prevent the phase shift from being less than −180 • , the zero break frequency, f zc , should be less than f opc1 .Thus, substitution of the f zc = f opc1 /2 = 49 Hz and R fc2 = 12.96 kΩ into (33) can yield C fc1 = 250.62nF.Under these conditions, the frequency range can be expressed as f zc < f opc1 , as depicted in Figure 17a.
Substitution of the R fc1 =10 kΩ, R fc2 = 12.96 kΩ, C fc1 = 250.62nF, and C fc2 = 491.22pF into ( 32) and (36) could yield the transfer function of open-loop gain for the LBPRC with the CFC, G comc (s), whose frequency response simulation was plotted in Figure 16.From Figure 16, the low-frequency gain was increased to 52.9 dB.At the f coc = 10 kHz, the phase was −88.7 • , which was greater than −135 • .Moreover, the transfer function of the negative feedback operation for the charge current loop was G fbc (s), whose low-frequency gain was 18.6 dB; the phase was greater than −135 • when the band ranges were from 1 to 26.8 kHz; therefore, the CC charge could address the stability requirement.

Current Overshoot Mitigation Using Zero Break Frequency Shift (ZBFS)
As shown in Figure 16, the G fbc gain presented a lapse shape from 1 to 20 kHz.This situation would influence the response speeds of charge current loop, resulting in the current overshoot i oc of the start-up phase and a long settling time, as illustrated in Figure 18a.According to the step 4 of Section 5.2.1., because the f zc = 49 Hz, a large capacitance C fc1 = 250.62nF was obtained; in consequence, the long-time integral action of PI control became a problem to limiting the CFC response speed.However, shifting f zc to a high frequency was an effective method that could resolve this problem, as depicted in Figure 18b; therefore, the f zc was increased to 5 kHz from the zero break frequency of 49 Hz, and then the frequency range could be expressed as f zc < f coc , as depicted in Figure 17b  Figure 19a shows the CFC circuit with PSPI control composed of an operational amplifier OP3, compensative elements (Zin, Zfc1, and Zfc2), and the Io(ref).Using Zin and Zfc2 can yield the P gain to implement the P control; the Zin combines Zfc1 with Zfc2 can achieve the PI control.
Moreover, the shifting certification for the Scfc is defined as follows:

Current Overshoot Mitigation Using PSPI Control
Figure 19a presents a PSPI configuration and a practical circuit schema that can be applied to mitigate the charge current overshoot during the LBPRC start-up phase.The R s and SA are used to detect and amplify the charge current signal v ibat , then the SA generates a voltage signal v cfci ; thus, the CFC compares v cfci with a charge current reference command I o(ref ) to generate an error voltage v cfco undergoing proportional (P) or PI compensation to control the PSFB controller (Figure 6).

LBPRC Charge Strategy
In practice, the SOC and state of health (SOH) of the battery should be evaluated by the battery management system (BMS).This is because the LBP electrical-chemical characteristics would be affected under different operating conditions.According to the SOC and SOH, the BMS can manipulate the LBPRC to implement a CV or CC charge.Therefore, an optimum charge strategy can be determined by the BMS, rather than the LBPRC.Supplying a stable CV or CC power to charge the LBP is the principal responsibility of the LBPRC.
Because of the LBPRC should be designed as an ideal voltage or current source to replenish LBPs; therefore, this study focused on the VFC design for the CV output operation of LBPRC, and the CFC design for the CC output operation of LBPRC.In [16][17][18][19], the CC-CV charge strategy was a suitable method for the LiFePO4 battery charge.Therefore, the CC-CV charge strategy is the first case of charge strategy.Moreover, to fulfill the battery charge requirement, the LBP can be rapidly charged by the LBPRC within one hour.The second case of charge strategy can use the CC to replenish the LBP.Charge conditions of both cases are defined as follows: Case 1: When the SOC of the LBP approximates to zero, the voltage of the empty LBP is approximately 22 V; if the LBP SOC ranges from empty to 20% (LBP voltage is 27.2 V), the LBP is charged by a 35-A (1C) CC.If the LBP SOC is higher than 20%, then the LBPRC can operate in the CV output mode to charge the LPB.This case can confirm that LBPRC supplying the CV power to charge the LBP is feasible for low to high LPB SOCs.This charge profile will be presented.
Case 2: The LBP SOC ranges from empty to 83% (LBP voltage is 29.2 V).The LBP is charged by a 35-A CC.This case can confirm that LBPRC supplying the CC power to charge the LBP is feasible for low to high LPB SOCs.This charge profile will be presented present.

Experimental Results
The measurement system of frequency response for the LBPRC is depicted in Figure 20.This system comprised a computer, a USB/GPIB interface (National Instruments Inc., Austin, TX, USA), and a frequency response analyzer (FRA) MODEL3120 (Veneable Corp., Austin, TX, USA).The FRA setting parameter and data can be controlled and transmitted through the USB/GPIB interface.From Figure 19b, during Phase I, the LBPRC is dominated by the VFC with the soft-start (SS) control, and the V bat slowly increases, thus avoiding the voltage overshoot occurrence at the LBPRC output side.As the I bat increases to reach the current setting for the I set , the shifting component S cfc (Figure 19a) is connected to the position p 1 , enabling the CFC to implement P control during the Phase II; hence, the CFC response speed can be enhanced to prevent the charge current overshoot.In the Phase III, the I bat reaches the target charge CC I const , the S cfc is sifted to the position p 2 , and then the CFC implements the PI control to stabilize the LBP charge current for achieving the CC charge.
Figure 19a shows the CFC circuit with PSPI control composed of an operational amplifier OP 3 , compensative elements (Z in , Z fc1 , and Z fc2 ), and the I o(ref ) .Using Z in and Z fc2 can yield the P gain to implement the P control; the Z in combines Z fc1 with Z fc2 can achieve the PI control.
Moreover, the shifting certification for the S cfc is defined as follows: During Phases I and II, the v cfco is greater than the V cfci to cut in the S cfc , the integral component Z fc1 is invalid and the unique P control can be implemented through Z fc2 and Z in for the CFC.In Phase III, the S cfc is cut off, thus the CFC can employ the Z in , Z fc1 , and Z fc2 to implement the PI control.Therefore, from the time interval [t p1 :t p2 ] (Figure 19), the CFC control can shift from P to PI; this control method is effective to mitigate the charge current overshoot.Moreover, the designing parameters from Sections 5.2.1 and 5.2.2 can completely apply to Z in , Z fc1 , and Z fc2 without readjusting and redesigning.

LBPRC Charge Strategy
In practice, the SOC and state of health (SOH) of the battery should be evaluated by the battery management system (BMS).This is because the LBP electrical-chemical characteristics would be affected under different operating conditions.According to the SOC and SOH, the BMS can manipulate the LBPRC to implement a CV or CC charge.Therefore, an optimum charge strategy can be determined by the BMS, rather than the LBPRC.Supplying a stable CV or CC power to charge the LBP is the principal responsibility of the LBPRC.
Because of the LBPRC should be designed as an ideal voltage or current source to replenish LBPs; therefore, this study focused on the VFC design for the CV output operation of LBPRC, and the CFC design for the CC output operation of LBPRC.In [16][17][18][19], the CC-CV charge strategy was a suitable method for the LiFePO 4 battery charge.Therefore, the CC-CV charge strategy is the first case of charge strategy.Moreover, to fulfill the battery charge requirement, the LBP can be rapidly charged by the LBPRC within one hour.The second case of charge strategy can use the CC to replenish the LBP.Charge conditions of both cases are defined as follows: Case 1: When the SOC of the LBP approximates to zero, the voltage of the empty LBP is approximately 22 V; if the LBP SOC ranges from empty to 20% (LBP voltage is 27.2 V), the LBP is charged by a 35-A (1C) CC.If the LBP SOC is higher than 20%, then the LBPRC can operate in the CV output mode to charge the LPB.This case can confirm that LBPRC supplying the CV power to charge the LBP is feasible for low to high LPB SOCs.This charge profile will be presented.
Case 2: The LBP SOC ranges from empty to 83% (LBP voltage is 29.2 V).The LBP is charged by a 35-A CC.This case can confirm that LBPRC supplying the CC power to charge the LBP is feasible for low to high LPB SOCs.This charge profile will be presented.

Experimental Results
The measurement system of frequency response for the LBPRC is depicted in Figure 20.This system comprised a computer, a USB/GPIB interface (National Instruments Inc., Austin, TX, USA), and a frequency response analyzer (FRA) MODEL3120 (Veneable Corp., Austin, TX, USA).The FRA setting parameter and data can be controlled and transmitted through the USB/GPIB interface.Therefore, the fluctuant small signals v i , v v f ci , and v c f ci generating by the FRA can be respectively output to the PSFB controller and adders (A 1 and A 2 ).Subsequently, the fluctuant charge voltage v bat and current i bat can be recorded and transmitted to the FRA.Finally, the Bode plot is presented on the computer monitor.Frequency response measurement of open-loop charge voltage: As indicated in Figure 20, when both S1 and S2 were turned off, the FRA output was i v ~; the fluctuant bat v ~ could then be measured and input to the FRA.The Bode plot of Gov was displayed in Figure 21a.The low-frequency gain was 10 dB (simulation: 11.4 dB), and the bandwidth was 250 Hz (simulation: 237 Hz).At gain of 0 dB, the frequency and phase were 1.6 kHz (simulation: 1.7 kHz) and −58° (simulation: −49.9°), respectively.Moreover, for the break frequencies, the fopc1 = 100 Hz had a pole (simulation: 98.04 Hz), the fozc1 = 1.5 kHz had a zero (simulation: 1.05 Hz), and the fopc2 = 12 kHz had a pole (simulation: 9.8 kHz).The gain and phase slopes in the different bands were listed in Table 8.
Frequency response measurement of open-loop charge current: As indicated in Figure 20, when both S1 and S2 were turned off, the FRA output was v ~; the fluctuant i ~ could then be measured and Frequency response measurement of open-loop charge voltage: As indicated in Figure 20, when both S 1 and S 2 were turned off, the FRA output was v i ; the fluctuant v bat could then be measured and input to the FRA.The Bode plot of G ov was displayed in Figure 21a.The low-frequency gain was 10 dB (simulation: 11.4 dB), and the bandwidth was 250 Hz (simulation: 237 Hz).At gain of 0 dB, the frequency and phase were 1.6 kHz (simulation: 1.7 kHz) and −58 • (simulation: −49.9 • ), respectively.Moreover, for the break frequencies, the f opc1 = 100 Hz had a pole (simulation: 98.04 Hz), the f ozc1 = 1.5 kHz had a zero (simulation: 1.05 Hz), and the f opc2 = 12 kHz had a pole (simulation: 9.8 kHz).The gain and phase slopes in the different bands were listed in Table 8.Frequency response measurement of closed-loop charge voltage: As shown in Figure 20, with the S1 turned on and the S2 turned off, the FRA generated vfci v ~, which was input to A1, the bat v ~ could then be measured by the FRA.The Bode plot of Gfbv is displayed in Figure 22a.The low-frequency gain was 22 dB (simulation: 22.7 dB).At the gain 0 dB, its frequency was 30 kHz (simulation: 40 kHz).
Frequency response measurement of closed-loop charge current: As shown in Figure 20, with the S2 turned on and the S1 turned off, the FRA produced cfci v ~, which was input to A2; the bat i ~ could then be measured by the FRA, and the Bode plot of Gfbc was displayed in Figure 22b.The lowfrequency gain was 18 dB (simulation: 18.6 dB).At the gain 0 dB, the frequency was 80 kHz (simulation: 50 kHz).The gain exhibited a lapse from 1 to 40 kHz, which could influence the system response speed.Therefore, the fzc should be adjusted to 5 kHz to heave a lapse gain; the subsequent Bode plot is displayed in Figure 22c.Waveform of start-up current using PI control and ZBFS: Figures 23 to 27 present the waveforms of the charge voltage Vbat and current Ibat during the charge start-up phase.At the charge rate of 0.5 C and SOC level of 30% (Figure 23a), the LBP started to charge from a Vbat level of 26.92 V; the target value of average charge current was maintained at 17.5 A (0.5C).During the start-up phase, a large current overshoot occurred because the zero break frequency fzc was set to 49 Hz.The current overshoot peak was 34 A, which exceeded the operating CC of 16.5 A (i.e., 34 -17.5).As illustrated in Figure 23(b), the time scale of the waveform window was curtailed to 10 ms/division (ms/div.), and the following several circumstances were observed: 1) A prolonged start-up time of 30 ms was observed before the LBPRC operated in the CC charge mode.2) A low-frequency current ripple of 60 Hz was observed (Figure 23); this was because an AC power source served as the input source of the LBPRC, with a power factor correction providing a DC voltage of 400 V mixing the low-frequency ripple to the PSFB-PCDR.However, the lowfrequency current ripple did not damage the LBP in the charge state.3) The average charge current was 17.5 A, and the current overshoot peak was 34 A.
As illustrated in Figure 23c, when the charge start voltage was 27.05 V (SOC 50%), the start-up time was 34 ms, average charge current was 17.5 A, and current overshoot peak was 29 A. As shown in Figure 23d, when the charge start voltage was 27.23 V (SOC 70%), the start-up time was 40 ms, average charge current was 17.5 A, and current overshoot peak was 28 A.   20, when both S 1 and S 2 were turned off, the FRA output was v i ; the fluctuant i bat could then be measured and input to FRA.The Bode plot of G oc was displayed in Figure 21b.The low-frequency gain was 35 dB (simulation: 35.6 dB), and the bandwidth was 190 Hz (simulation: 200 Hz).At gain of 0 dB, the frequency and phase were 52 kHz (simulation: 50 kHz) and −130 • (simulation: −140 • ), respectively.Moreover, for the break frequencies, the f opv1 = 100 Hz had a pole (simulation: 98.04 Hz), the f ozv1 = 3.5 kHz had a zero (simulation: 1.05 kHz), and f opv2 = 15 kHz had a pole (simulation: 9.8 kHz).The gain and phase slopes in the different bands were listed in Table 8.These measurements demonstrate that the proposed equivalent models are suitable for establishing the small-signal transfer functions of LBPRC.
Frequency response measurement of closed-loop charge voltage: As shown in Figure 20, with the S 1 turned on and the S 2 turned off, the FRA generated v v f ci , which was input to A 1 , the v bat could then be measured by the FRA.The Bode plot of G fbv is displayed in Figure 22a.The low-frequency gain was 22 dB (simulation: 22.7 dB).At the gain 0 dB, its frequency was 30 kHz (simulation: 40 kHz).However, using the ZBFS method, the fzc of CFC can be shifted to 5 kHz to accelerate the response speed of the charge current loop, and the waveforms of the charge voltage and current are presented in Figure 24.In Figure 24a,b, the time scales of the waveform windows were 100 and 10 ms/div., respectively.The LBP started to charge from a Vbat level of 26.92 V (SOC 30%); the current overshoot peak could be reduced to 23 A, the start-up time was cut to 12 ms, which was lower than in Figure 23b.Notably, the current ripple peak and frequency were 1 A and 60 Hz, respectively; the lowfrequency ripple was the same as that in Figure 23(b).Hence, applying the proposed ZBFS method to the LBPRC did not influence system stability.As illustrated in Figure 24c, when the charge start voltage was 27.05 V (SOC 50%), the start-up time was 12 ms, average charge current was 17.5 A, and current overshoot peak was 22 A. As illustrated in Figure 24d, when the charge start voltage was 27.23 V (SOC 70%), the start-up time was 12 ms, average charge current was 17.5 A, and current overshoot peak was 21 A. Therefore, the fzc shifting effectively reduces the charge current overshoot, and does not cause system instability.Frequency response measurement of closed-loop charge current: As shown in Figure 20, with the S 2 turned on and the S 1 turned off, the FRA produced v c f ci , which was input to A 2 ; the i bat could then be measured by the FRA, and the Bode plot of G fbc was displayed in Figure 22b.The low-frequency gain was 18 dB (simulation: 18.6 dB).At the gain 0 dB, the frequency was 80 kHz (simulation: 50 kHz).The gain exhibited a lapse from 1 to 40 kHz, which could influence the system response speed.Therefore, the f zc should be adjusted to 5 kHz to heave a lapse gain; the subsequent Bode plot is displayed in Figure 22c.
Waveform of start-up current using PI control and ZBFS: Figure 23, Figure 24 , Figures 25-27 present the waveforms of the charge voltage V bat and current I bat during the charge start-up phase.At the charge rate of 0.5 C and SOC level of 30% (Figure 23a), the LBP started to charge from a V bat level of 26.92 V; the target value of average charge current was maintained at 17.5 A (0.5C).During the start-up phase, a large current overshoot occurred because the zero break frequency f zc was set to 49 Hz.The current overshoot peak was 34 A, which exceeded the operating CC of 16.5 A (i.e., 34 -17.5).As illustrated in Figure 23b, the time scale of the waveform window was curtailed to 10 ms/division (ms/div.), and the following several circumstances were observed: (1) A prolonged start-up time of 30 ms was observed before the LBPRC operated in the CC charge mode.(2) A low-frequency current ripple of 60 Hz was observed (Figure 23); this was because an AC power source served as the input source of the LBPRC, with a power factor correction providing a DC voltage of 400 V mixing the low-frequency ripple to the PSFB-PCDR.However, the low-frequency current ripple did not damage the LBP in the charge state.(3) The average charge current was 17.5 A, and the current overshoot peak was 34 A.  Waveform of current overshoot mitigation using PSPI control: The start-charge voltage and current when the LBPRC incorporates the CFC with the PSPI control are presented in Figure 25.As illustrated in Figure 25a,b, the time scale of the waveform window was 100 and 10 ms/div., respectively.The LBP started to charge from a Vbat level of 26.92 V (SOC 30%), the current overshoot peak was reduced to 19 A, and the start-up time was cut to 11 ms; they were lower than those in Figures 23 and 24.As illustrated in Figure 25c, when the charge start voltage was 27.05 V (SOC 50%), the start-up time was 11 ms, average charge current was 17.5 A, and current overshoot peak was 19 A. As illustrated in Figure 25d, when the charge start voltage was 27.23 V (SOC 70%), the start-up time was 10 ms, average charge current was 17.5 A, and current overshoot peak was 19 A. Compared with the PI control, ZBFS method, and PSPI control, the control method incorporating the PSPI control technology into the CFC was determined to be more effective since the current overshoot peak could be reduced to 19 A, thereby approximating the average charge current of 17.5 A; moreover, the start-up time could be curtailed to 10 ms.
Waveform of 1C charge using PSPI control: At the charge rate of 1C (CC of 35 A) in Figure 26a,b, the time scales of the waveform windows were 100 and 10 ms/div., respectively.The charge start voltage was the minimum cut-off voltage 22 V, no current overshoot was observed, and the average charge current was the CC 35 A; therefore, the proposed PSPI control was also effective for the charge rate of 1C.CV and CC charge profiles: Figure 27 presents the LBP charge profile using the developed LBPRC.Figure 27a presented the CC-CV charge strategy; during the CC 35 A charge, the battery voltage increased gradually from 22 to 27.2 V; then, LBPRC took over as the CV output mode to charge the LBP, and the charge current gradually decreased.This experiment demonstrated that LBPRC could implement the CV charge when the LBP SOC was increased from low (20%) to high.
In Figure 27b, the single CC 35 A charges the LBP, hence the LBP voltage increased gradually from 22 to 29.2 V; the total charge time was about 52 min.This experiment demonstrated that the LBP could be charged from a low SOC of 20% to a high LBP of 83% (LBP voltage is 29.2 V) using the CC charge strategy.Both experiments confirmed that the LBPRC design was implemented using the VFC and CFC, both CV and CC charge functions could replenish the LBP.According to Figure 27b, the maximum output power of the LBPRC was 1022 W (i.e., 29.2 V × 35 A) and the charge current was 35    LBPRC conversion efficiency: In this study, the power stage of the LBPRC was composed of a PFC and a PSFB-PCDR.To measure the LBPRC conversion efficiency, the LBPRC inlet inputted a single-phase AC power source, whose output voltage and frequency were 230 Vrms and 60 Hz, respectively.Figure 28 reports the LBPRC conversion efficiencies with different loads; the maximum efficiency was 88.8% when the output power was at 525 W; the minimum efficiency was 86.1% at 315 W. When the LBPRC operated at the maximum output power of 1050 W, the conversion efficiency was 86.7%.
In Figure 8, the maximum efficiency of the LBPRC, 88.8%, was obtained when PFC and PSFB-PCDR efficiencies were 95% and 93%, respectively.Therefore, the maximum LBPRC efficiency could be calculated as 88.8% (95% × 93% = 88%).Under this operating condition, power switches (Qa to Qd) were operated in zero-voltage switching, hence the single-stage PSFB-PCDR efficiency can reach 93%; however, because of the PSFB-PCDR secondary side used diode rectification, power losses of the As illustrated in Figure 23c, when the charge start voltage was 27.05 V (SOC 50%), the start-up time was 34 ms, average charge current was 17.5 A, and current overshoot peak was 29 A. As shown in Figure 23d, when the charge start voltage was 27.23 V (SOC 70%), the start-up time was 40 ms, average charge current was 17.5 A, and current overshoot peak was 28 A.
However, using the ZBFS method, the f zc of CFC can be shifted to 5 kHz to accelerate the response speed of the charge current loop, and the waveforms of the charge voltage and current are presented in Figure 24.In Figure 24a,b, the time scales of the waveform windows were 100 and 10 ms/div., respectively.The LBP started to charge from a V bat level of 26.92 V (SOC 30%); the current overshoot peak could be reduced to 23 A, the start-up time was cut to 12 ms, which was lower than in Figure 23b.Notably, the current ripple peak and frequency were 1 A and 60 Hz, respectively; the low-frequency ripple was the same as that in Figure 23b.Hence, applying the proposed ZBFS method to the LBPRC did not influence system stability.As illustrated in Figure 24c, when the charge start voltage was 27.05 V (SOC 50%), the start-up time was 12 ms, average charge current was 17.5 A, and current overshoot peak was 22 A. As illustrated in Figure 24d, when the charge start voltage was 27.23 V (SOC 70%), the start-up time was 12 ms, average charge current was 17.5 A, and current overshoot peak was 21 A. Therefore, the f zc shifting effectively reduces the charge current overshoot, and does not cause system instability.
Waveform of current overshoot mitigation using PSPI control: The start-charge voltage and current when the LBPRC incorporates the CFC with the PSPI control are presented in Figure 25.As illustrated in Figure 25a,b, the time scale of the waveform window was 100 and 10 ms/div., respectively.The LBP started to charge from a V bat level of 26.92 V (SOC 30%), the current overshoot peak was reduced to 19 A, and the start-up time was cut to 11 ms; they were lower than those in Figures 23 and 24.As illustrated in Figure 25c, when the charge start voltage was 27.05 V (SOC 50%), the start-up time was 11 ms, average charge current was 17.5 A, and current overshoot peak was 19 A. As illustrated in Figure 25d, when the charge start voltage was 27.23 V (SOC 70%), the start-up time was 10 ms, average charge current was 17.5 A, and current overshoot peak was 19 A. Compared with the PI control, ZBFS method, and PSPI control, the control method incorporating the PSPI control technology into the CFC was determined to be more effective since the current overshoot peak could be reduced to 19 A, thereby approximating the average charge current of 17.5 A; moreover, the start-up time could be curtailed to 10 ms.
Waveform of 1C charge using PSPI control: At the charge rate of 1C (CC of 35 A) in Figure 26a,b, the time scales of the waveform windows were 100 and 10 ms/div., respectively.The charge start voltage was the minimum cut-off voltage 22 V, no current overshoot was observed, and the average charge current was the CC 35 A; therefore, the proposed PSPI control was also effective for the charge rate of 1C.
CV and CC charge profiles: Figure 27 presents the LBP charge profile using the developed LBPRC.Figure 27a presented the CC-CV charge strategy; during the CC 35 A charge, the battery voltage increased gradually from 22 to 27.2 V; then, LBPRC took over as the CV output mode to charge the LBP, and the charge current gradually decreased.This experiment demonstrated that LBPRC could implement the CV charge when the LBP SOC was increased from low (20%) to high.
In Figure 27b, the single CC 35 A charges the LBP, hence the LBP voltage increased gradually from 22 to 29.2 V; the total charge time was about 52 min.This experiment demonstrated that the LBP could be charged from a low SOC of 20% to a high LBP of 83% (LBP voltage is 29.2 V) using the CC charge strategy.Both experiments confirmed that the LBPRC design was implemented using the VFC and CFC, both CV and CC charge functions could replenish the LBP.According to Figure 27b, the maximum output power of the LBPRC was 1022 W (i.e., 29.2 V × 35 A) and the charge current was 35 A (1C); therefore, the LBPRC rapid charge could be achieved for the LBP.
Moreover, the power rating of LBPRC was approximately 1 kW, and its charge current at the 1C rate was 35 A. Thus, the proposed PSFB-PCDR topology has several benefits for LBPRC applications, including zero-voltage switching, high conversion efficiency, and low-frequency current ripple reduction.The PSFB-PCDR is a commonly used topology for high-power DC-DC converter applications; the circuit component cost can be reduced in mass production to make it cost-effective.
LBPRC conversion efficiency: In this study, the power stage of the LBPRC was composed of a PFC and a PSFB-PCDR.To measure the LBPRC conversion efficiency, the LBPRC inlet inputted a single-phase AC power source, whose output voltage and frequency were 230 V rms and 60 Hz, respectively.Figure 28 reports the LBPRC conversion efficiencies with different loads; the maximum efficiency was 88.8% when the output power was at 525 W; the minimum efficiency was 86.1% at 315 W. When the LBPRC operated at the maximum output power of 1050 W, the conversion efficiency was 86.7%.
In Figure 8, the maximum efficiency of the LBPRC, 88.8%, was obtained when PFC and PSFB-PCDR efficiencies were 95% and 93%, respectively.Therefore, the maximum LBPRC efficiency could be calculated as 88.8% (95% × 93% = 88%).Under this operating condition, power switches (Q a to Q d ) were operated in zero-voltage switching, hence the single-stage PSFB-PCDR efficiency can reach 93%; however, because of the PSFB-PCDR secondary side used diode rectification, power losses of the diodes were high.The synchronous rectification can replace the diode rectification to promote LBPRC conversion efficiency.LBPRC conversion efficiency: In this study, the power stage of the LBPRC was composed of a PFC and a PSFB-PCDR.To measure the LBPRC conversion efficiency, the LBPRC inlet inputted a single-phase AC power source, whose output voltage and frequency were 230 Vrms and 60 Hz, respectively.Figure 28 reports the LBPRC conversion efficiencies with different loads; the maximum efficiency was 88.8% when the output power was at 525 W; the minimum efficiency was 86.1% at 315 W. When the LBPRC operated at the maximum output power of 1050 W, the conversion efficiency was 86.7%.
In Figure 8, the maximum efficiency of the LBPRC, 88.8%, was obtained when PFC and PSFB-PCDR efficiencies were 95% and 93%, respectively.Therefore, the maximum LBPRC efficiency could be calculated as 88.8% (95% × 93% = 88%).Under this operating condition, power switches (Qa to Qd) were operated in zero-voltage switching, hence the single-stage PSFB-PCDR efficiency can reach 93%; however, because of the PSFB-PCDR secondary side used diode rectification, power losses of the diodes were high.The synchronous rectification can replace the diode rectification to promote LBPRC conversion efficiency.Comparison of performance index: Figure 29 illustrates five performance indexes for three CFC control methods.The PSPI control method achieved excellent performance indices, including the start-up current overshoot reducing, a short setting time, the small steady-state errors, a short rising time, and a short start-up time.For the ZBFS control method, four performance indices were between those observed for the PSPI and PI control methods.Finally, the PI control method integrated with the CFC was the poorest combination because four performance indices were extremely poor.Comparison of performance index: Figure 29 illustrates five performance indexes for three CFC control methods.The PSPI control method achieved excellent performance indices, including the start-up current overshoot reducing, a short setting time, the small steady-state errors, a short rising time, and a short start-up time.For the ZBFS control method, four performance indices were between those observed for the PSPI and PI control methods.Finally, the PI control method integrated with the CFC was the poorest combination because four performance indices were extremely poor.Moreover, because the three control methods can implement the PI control during the steady-state operation, they have small steady-state errors.Moreover, because the three control methods can implement the PI control during the steady-state operation, they have small steady-state errors.LBPRC prototype: Figure 30 is a photo of the practical charge system.The input power of the LBPRC prototype comes from the AC source, and its output side connects to the LBP.To analyze the frequency response, the FRA is required and the Bode plot measurements can be displayed on the computer monitor.In addition, the experimental waveforms can be measured and displayed by the oscilloscope.LBPRC prototype: Figure 30 is a photo of the practical charge system.The input power of the LBPRC prototype comes from the AC source, and its output side connects to the LBP.To analyze the frequency response, the FRA is required and the Bode plot measurements can be displayed on the computer monitor.In addition, the experimental waveforms can be measured and displayed by the oscilloscope. oscilloscope.

Conclusions
This study presented the development and implementation of an LBPRC for the charge of LiFePO4 battery packs.The focus was on frequency response analyses of charge voltage and current; therefore, the TTS and PNGV battery models were applied to derive small-signal transfer functions.Consequently, the LBPRC could utilize both CV and CC power to replenish the LBP.This study makes the following contributions: 1) This study is the first to propose combinations of TTS and PNGV battery models in an LBPRC application alongside ZBFS and PSPI controls to mitigate the problem of current overshooting.
2) The proposed equivalent circuit, which incorporates the TTS and PNGV battery models with the wire resistance-inductance of the power cable, is a reformatory model for the small-signal analysis in the LBPRC application.3) On the basis of the TTS and PNGV battery models, high-order transfer functions were derived for the charge voltage and current loops.Although establishing the mathematical model was a complex and time-consuming process, the frequency response simulations could approximate the practical system.Therefore, the loop compensation could follow the proposed design procedure to achieve the zero-pole frequency setting, low-frequency gain heaving, and phase margin enhancement.4) Few studies have discussed CC control designs or how to mitigate charge current overshoot.
According to the Bode plot of the feedback current loop, the CFC compensation uses ZBFS; therefore, the current overshoot can be effectively reduced in the charge start-up phase.5) The study also presents a new control method, namely PSPI control, integrated into a CFC to mitigate the problem of charge current overshoot during the LBPRC start-up phase.The benefit

Conclusions
This study presented the development and implementation of an LBPRC for the charge of LiFePO 4 battery packs.The focus was on frequency response analyses of charge voltage and current; therefore, the TTS and PNGV battery models were applied to derive small-signal transfer functions.Consequently, the LBPRC could utilize both CV and CC power to replenish the LBP.This study makes the following contributions: (1) This study is the first to propose combinations of TTS and PNGV battery models in an LBPRC application alongside ZBFS and PSPI controls to mitigate the problem of current overshooting.(2) The proposed equivalent circuit, which incorporates the TTS and PNGV battery models with the wire resistance-inductance of the power cable, is a reformatory model for the small-signal analysis in the LBPRC application.(3) On the basis of the TTS and PNGV battery models, high-order transfer functions were derived for the charge voltage and current loops.Although establishing the mathematical model was a complex and time-consuming process, the frequency response simulations could approximate the practical system.Therefore, the loop compensation could follow the proposed design procedure to achieve the zero-pole frequency setting, low-frequency gain heaving, and phase margin enhancement.(4) Few studies have discussed CC control designs or how to mitigate charge current overshoot.
According to the Bode plot of the feedback current loop, the CFC compensation uses ZBFS; therefore, the current overshoot can be effectively reduced in the charge start-up phase.(5) The study also presents a new control method, namely PSPI control, integrated into a CFC to mitigate the problem of charge current overshoot during the LBPRC start-up phase.The benefit of this method is that no compensative element needs to be readjusted or redesigned, hence the prototypal PI parameter can be applied to achieve the PSPI control.(6) Three measurement methods, including the electrical parameter of PNGV battery model, the open-loop frequency response of LBPRC, and the closed-loop frequency response of LBPRC, were presented and discussed in this study.These methods are prerequisite designing processes to develop LBPRCs.Finally, an LBPRC prototype and practical charge system are also presented in this paper.

Figure 2 .
Figure 2. Parameter measurement of PNGV battery model.(a) Measurement configuration diagram.(b) Voltage−time characteristic using pulse-current charge.

Figure 2 .
Figure 2. Parameter measurement of PNGV battery model.(a) Measurement configuration diagram.(b) Voltage−time characteristic using pulse-current charge.

Figure
Figure 4a depicts the PSFB-PCDR circuit, including the DC input source V inps , power switches Q a to Q d , a blocking capacitance C b , a transformer T 1 , rectification diodes D f1 to D f4 , current-doubler inductances "L cdr1 to L cdr4 ", and an output capacitance C o .The positive and negative electrodes of the LBP are respectively connected to the PSFB-PCDR outlets o 1 and o 2 .Figure 4b presents the operating timing diagram of PSFB-PCDR that includes the driving signals v a to v d for Q a to Q d and the primary-side voltage v tp across T 1 ; the T sw is the operating switching period for v a to v d ; the d y represents the PSFB-PCDR operating duty cycle ratio.In Figure4, the TTS model can replace the circuit inside the a-frame, as illustrated in Figure5a.This model has a dependent voltage source v r , two current sources (i r1 and i r2 ), and a resistance R eqs .The V inps can be reflected to the T 1 secondary side becoming v r , as follows:
i bat = E i p v Co i bat v Ct v Cx T = e 1 e 2 e 3 e 4 e 5 i p v Co i bat v Ct v Cx T (20) where x' 1 = d i p /dt, x' 2 = d v Co /dt, x' 3 = d i bat /dt, x' 4 = d v Ct /dt, and x' 5 = d v Cx /dt.The calculations for the elements in matrices A, B, C, and E are listed in Table ibat = Ibat + bat i ~, vCo = VCo + Co v ~, vCt = VCt + Ct v ~, and vCx = VCx + Cx v ~ into (13)-(17) can yield the small-signal system matrix of PSFB-PCDR as follows:

Figure 6 .
Figure 6.Charge system configuration.(a) System block diagram.(b) Block diagram for open-loop gain of charge voltage.(c) Block diagram for open-loop gain of charge current.

Figure 6 .
Figure 6.Charge system configuration.(a) System block diagram.(b) Block diagram for open-loop gain of charge voltage.(c) Block diagram for open-loop gain of charge current.Table 7 lists the PSFB-PCDR circuit parameters (Figure 4).Substitution of the L k = 20 µH, f sw = 100 kHz, n = 14/6 = 2.33 in (7) yields R eqs = 184.2mΩ and L o = L cdr1 /4 = 2.25 µH.When the DC charge current is 17.5 A, the power cable must sustain this continuous current until LBP replenishment.To avoid the cable temperature rising over 75 • C, in this study, the length and diameter of the power cable were selected as 200 cm and 0.259 cm (No. 10 American wire gauge), respectively; in accordance with the data in[27,28], the R c = 6.55 mΩ and L c = 2.91 µH (Figure5) can be obtained.According to the average parameters in Table5, the R x = R c + R oir = 28.34mΩ.Substituting these parameters into Table6can yield the elements of matrices A, B, and C in (18) and(19).

Figure 7 .
Figure 7. Relationship of operating duty cycle dy to input voltage vi.

Figure 7 .
Figure 7. Relationship of operating duty cycle d y to input voltage v i. Substitution of v i = V i + v i and d = D y + d y in (22) yields the PSFB controller gain as follows:

Figure 9 .
Figure 9. Different SOCs of Gov (s).(a) Using the three SOCs and the average parameters.(b) Expanding scale from Figure 9a.

Figure 9 .
Figure 9. Different SOCs of G ov (s).(a) Using the three SOCs and the average parameters.(b) Expanding scale from Figure 9a.

Figure 10 .
Figure 10.Frequency response simulation using different battery models.

Figure 10 .
Figure 10.Frequency response simulation using different battery models.

Figure 12 .
Figure 12.Charge voltage loop.(a) Voltage divider and voltage feedback controller (VFC) circuit.(b) Control block diagram of closed-loop operation.

Figure 12 .
Figure 12.Charge voltage loop.(a) Voltage divider and voltage feedback controller (VFC) circuit.(b) Control block diagram of closed-loop operation.

Figure 14 .
Figure 14.Frequency point setting of charge voltage loop.Figure 14.Frequency point setting of charge voltage loop.

Figure 14 .
Figure 14.Frequency point setting of charge voltage loop.Figure 14.Frequency point setting of charge voltage loop.

Figure 15 .
Figure 15.Charge current loop.(a) SA and current feedback controller (CFC) circuit.(b) Control block diagram of closed-loop operation.

Figure 17 .
Figure 17.Frequency point design of charge current loop.(a) Normal PI design.(b) Using the zero break frequency shift (ZBFS) method.

Figure 17 .Figure 18 .
Figure 17.Frequency point design of charge current loop.(a) Normal PI design.(b) Using the zero break frequency shift (ZBFS) method.

Figure 18 .
Figure 18.During start-up phase, different control technologies result in current overshoot occurrence.(a) Normal PI design.(b) Using the ZBFS method.

Figure 19 .
Figure 19.A novel PSPI control.(a) PSPI configuration diagram and practical circuit.(b) Phases I to III.

Figure 19 .
Figure 19.A novel PSPI control.(a) PSPI configuration diagram and practical circuit.(b) Phases I to III.

Electronics 2018, 7 ,
x FOR PEER REVIEW 20 of 29 and current bat i ~ can be recorded and transmitted to the FRA.Finally, the Bode plot is presented on the computer monitor.

Figure 20 .
Figure 20.Measurement system of frequency response for LBPRC.

Figure 20 .
Figure 20.Measurement system of frequency response for LBPRC.

Figure 22 .
Figure 22.Bode plot measurements for G fbv and G fbc : (a) G fbv using PI control.(b) G fbc using PI control.(c) G fbc using the ZBFS method.

Figure 29 .
Figure 29.Performance indices for PSPI control, the ZBFS method, and PI control.Figure 29.Performance indices for PSPI control, the ZBFS method, and PI control.

Figure 29 .
Figure 29.Performance indices for PSPI control, the ZBFS method, and PI control.Figure 29.Performance indices for PSPI control, the ZBFS method, and PI control.

Figure 29 .
Figure 29.Performance indices for PSPI control, the ZBFS method, and PI control.

Figure 30 .
Figure 30.A photo of the practical charge and measurement system.

Figure 30 .
Figure 30.A photo of the practical charge and measurement system.

Table 4 .
Records of voltages and times.

Table 5 .
Parameter value of PNGV battery model.

Table 4 .
Records of voltages and times.

Table 5 .
Parameter value of PNGV battery model.
a 11 a 12 a 13 a 14 a 15 a 21 a 22 a 23 a 24 a 25 a 31 a 32 a 33 a 34 a 35 a 41 a 42 a 43 a 44 a 45 a 51 a 52 a 53 a 54 a 55

Table 6 .
Element calculations for matrices A

Table 6 .
Element calculations for matrices A

4. Open-Loop Frequency Response
)The characteristics of the operating duty cycle dy with input voltage vi is illustrated in Figure7.Using the MATLAB curve-fitting function, a linear polynomial can be expressed as follows:

Table 8 .
Gain and phase slopes.