A 1.8 V 18.13 MHz Inverter-Based On-Chip RC Oscillator with Flicker Noise Suppression Using Logic Transition Voltage Feedback

: An inverter-based on-chip resistor capacitor (RC) oscillator with logic transition voltage (LTV) tracking feedback for circuit delay compensation is presented. In order to achieve good frequency stability, the proposed technique considers the entire inverter chain as a comparator block and changes the LTV to control the oscillation frequency. Furthermore, the negative feedback structure also reduces low-frequency o ﬀ set phase noise. With a 1.8 V supply and at room temperature, the suggested oscillator operates at 18.13 MHz, consuming 245.7 µ W. Compared to the free-running case, the proposed technique reduces phase noise by 7.7 dB and 5.45 dB at 100 Hz and 1 kHz, respectively. The measured phase noise values are − 60.09 dBc / Hz at 1 kHz with a ﬁgure of merit (FOM) of 151.35 dB / Hz, and − 106.27 dBc / Hz at 100 KHz with an FOM of 157.53 dBc / Hz. The proposed oscillator occupies 0.056 mm 2 in a standard 0.18 µ m CMOS process.


Introduction
As smart devices become more popular and the market demand for wearable devices grows, the need for low-power, on-chip resistor capacitor (RC) oscillators in a standard CMOS process is increasing, to address the cost and board area issues in external crystal oscillators. Owing to their strengths compared with ring oscillators (better frequency stability, control linearity, and wide tuning range), fully integrated relaxation oscillators are widely used as on-chip reference clocks, or as sensor front-end interfaces [1,2]. However, since the figure of merit (FOM) of a relaxation oscillator still cannot reach its theoretical limit [3], several studies are currently ongoing to overcome these circuit issues.
Voltage-to-delay feedback and a switch-capacitor, swing-boosting (SCSB) circuit have been proposed to help improve frequency stability and phase noise characteristics [1], but an SCSB requires a large chip area due to its passive components. In order to reduce comparator noise effects, [2] suggests a differential swing-boosting method with a 162.1 dBc/Hz FOM. However, this scheme requires a high-speed comparator for output frequency stabilization [4]. Filtering the jitter noise in [3] yields a good FOM, while using a low-noise, milliwatt-level, power-hungry block. A feedback structure for frequency stabilization is also introduced in [5,6], but the power consumption in its analog feedback blocks limits its FOM. A low-frequency, inverter-chain-based RC oscillator scheme is presented in [7], achieving a high-voltage swing at its oscillating node. However, as this single-ended approach is vulnerable to circuit delay fluctuations, a regulated supply from a proportional-to-absolution-temperature (PTAT) reference is required, and this leads to a low operating frequency.
In this article, an inverter-based RC oscillator with a logic transition voltage (LTV) tracking feedback method is proposed. The LTV of an inverter is defined where the input and output voltages are the same. While maintaining a boosted voltage slope on the timing capacitor [7] for low-noise operation [2], we replace the local regulated supply scheme with an LTV tracking structure, utilizing a voltage averaging feedback (VAF) concept [5] to obtain a high-frequency oscillator (>1 MHz). The structure of the first-stage inverter is modified so that the feedback loop can control the LTV of this inverter. As a result, the effect of circuit delay on the oscillation frequency is reduced. The suggested structure is not only insensitive to circuit variations, but also suppresses low frequency offset phase noise and flicker noise, due to its negative feedback configuration.
This article consists of six sections. Section 2 demonstrates a conventional RC oscillator and the voltage-averaging feedback concept. In Section 3, the circuit level implementation of the proposed oscillator is described, followed by simulation and measurement results illustrated in Section 4. Finally, we present our conclusions in Section 5. Figure 1 shows a generally known, conventional RC relaxation oscillator and its timing diagram [8]. For a logical high Φ 1 (and a low Φ 2), the timing capacitor C 1 is charged by the constant current source I B , while C 2 is grounded. When the voltage across C 1 (V 1 in Figure 1) reaches the threshold level V REF , the output of the comparator toggles, causing C 1 to discharge and C 2 to charge. Conversely, when the voltage on C 2 crosses V REF , C 1 charges and C 2 discharges. This cycle repeats to create the oscillating function. As shown in the timing diagram in Figure 1, the oscillator output period consists of T OSC , as determined by the timing capacitors, plus the circuit delay. As this delay is sensitive to supply and temperature variation, several methods have been introduced [1,5,8] to stabilize the oscillation frequency. In addition, in order to achieve low noise, [2] introduced a method of increasing the charging/discharging slope of the timing capacitor voltages using a swing booster circuit. In this article, an inverter-based RC oscillator with a logic transition voltage (LTV) tracking feedback method is proposed. The LTV of an inverter is defined where the input and output voltages are the same. While maintaining a boosted voltage slope on the timing capacitor [7] for low-noise operation [2], we replace the local regulated supply scheme with an LTV tracking structure, utilizing a voltage averaging feedback (VAF) concept [5] to obtain a high-frequency oscillator (>1 MHz). The structure of the first-stage inverter is modified so that the feedback loop can control the LTV of this inverter. As a result, the effect of circuit delay on the oscillation frequency is reduced. The suggested structure is not only insensitive to circuit variations, but also suppresses low frequency offset phase noise and flicker noise, due to its negative feedback configuration.

Conventional RC Oscillator Structure
This article consists of six sections. Section 2 demonstrates a conventional RC oscillator and the voltage-averaging feedback concept. In Section 3, the circuit level implementation of the proposed oscillator is described, followed by simulation and measurement results illustrated in Section 4. Finally, we present our conclusions in Section 5. Figure 1 shows a generally known, conventional RC relaxation oscillator and its timing diagram [8]. For a logical high Φ 1 (and a low Φ 2), the timing capacitor C1 is charged by the constant current source IB, while C2 is grounded. When the voltage across C1 (V1 in Figure 1) reaches the threshold level , the output of the comparator toggles, causing C1 to discharge and C2 to charge. Conversely, when the voltage on C2 crosses , C1 charges and C2 discharges. This cycle repeats to create the oscillating function. As shown in the timing diagram in Figure 1, the oscillator output period consists of , as determined by the timing capacitors, plus the circuit delay. As this delay is sensitive to supply and temperature variation, several methods have been introduced [1,5,8] to stabilize the oscillation frequency. In addition, in order to achieve low noise, [2] introduced a method of increasing the charging/discharging slope of the timing capacitor voltages using a swing booster circuit.    Figure 2 shows the inverter-based RC oscillator scheme introduced in [7]. Biased by the PTAT reference current, a voltage regulator produces a local supply voltage (Local Supply in Figure 2). The circuit delay through the inverter chains causes the almost constant over supply of voltage and temperature variations, because this regulated supply tracks for both NMOS and PMOS thresholds, leading to a stable oscillation frequency. An increased voltage swing across its timing capacitor also helps this structure to achieve low-noise performance. However, a lower local supply voltage limits this scheme to a low oscillating frequency (33 kHz in [7]).

Voltage Averaging Feedback (VAF) Concept
A voltage-averaging feedback (VAF) method has been proposed in order to achieve good frequency stability in an on-chip CMOS relaxation oscillator [5]. The conceptual waveform is illustrated in Figure 3, where V TH,COMP and V REF are the threshold voltage of the comparators and the reference voltage of the VAF integrator, respectively. In its steady state, the active filter in the VAF loop equalizes V REF and the DC voltage of oscillation, creating the following relationship: Electronics 2019, 8, x FOR PEER REVIEW 3 of 11 Figure 2 shows the inverter-based RC oscillator scheme introduced in [7]. Biased by the PTAT reference current, a voltage regulator produces a local supply voltage (Local Supply in Figure 2). The circuit delay through the inverter chains causes the almost constant over supply of voltage and temperature variations, because this regulated supply tracks for both NMOS and PMOS thresholds, leading to a stable oscillation frequency. An increased voltage swing across its timing capacitor also helps this structure to achieve low-noise performance. However, a lower local supply voltage limits this scheme to a low oscillating frequency (33 kHz in [7]). A voltage-averaging feedback (VAF) method has been proposed in order to achieve good frequency stability in an on-chip CMOS relaxation oscillator [5]. The conceptual waveform is illustrated in Figure 3, where , and are the threshold voltage of the comparators and the reference voltage of the VAF integrator, respectively. In its steady state, the active filter in the VAF loop equalizes and the DC voltage of oscillation, creating the following relationship:

Voltage Averaging Feedback (VAF) Concept
In Equation (2), during , the areas of the and graphs are the same. If the comparator delay ( in Figure 3) increases while , maintains its value, the graph area configured by increases. Since the area under the graph enclosed by -the output of a resistive divider -is constant and insensitive to delay variation, the VAF loop lowers , to satisfy the integration relationship ( Figure 3b). In contrast, for a shorter , the feedback structure increases , to adjust the curve. In summary, if the circuit delay is constant, an increase/decrease in In Equation (2), during T H , the areas of the V OSC and V REF graphs are the same. If the comparator delay (δ COMP s in Figure 3) increases while V TH,COMP maintains its value, the graph area configured by V OSC increases. Since the area under the graph enclosed by V REF -the output of a resistive divider -is constant and insensitive to delay variation, the VAF loop lowers V TH,COMP to satisfy the integration relationship ( Figure 3b). In contrast, for a shorter δ COMP , the feedback structure increases V TH,COMP to adjust the V OSC curve.
In summary, if the circuit delay is constant, an increase/decrease in V TH,COMP causes a decrease/increase in the oscillation frequency. Therefore, the VAF technique, by changing the comparator threshold voltage, reduces the effect of circuit delay variation by controlling the frequency.

Oscillating Mechanism of an Inverter-Based RC Oscillator
A simple example of the structure and waveform of an inverter-based RC oscillator is shown in Figure 4. In practice, the gain of the inversion stages (INV1 and INV2 in Figure 4) should be large enough to allow for oscillation, and the proposed oscillator uses multiple inverters to allow for high gain [7]. When the V OSC , V A , and V B nodes are, respectively, high, low, and high, V OSC gradually decreases as R OSC discharges C OSC. When V OSC equals the LTV of INV1, where the input and output voltages are the same, V A and V B change to logical high and low states, respectively. Since the charge on the capacitor should be the same, the voltage change at the V B node lowers the V OSC equally, making V LOW equal to LTV INV1 − V DD . Next, since the V OSC node voltage decreases while V A stays in the high state, C OSC is charged through R OSC , and the V OSC node voltage increases. Similarly, when the charging V OSC passes the LTV INV1 level, the V OSC node voltage rises to V HIGH = LTV INV1 + V DD , due to the logic changes in the following inverters. The timing diagram in Figure 4 shows the charge and discharge cycles of the V OSC node, where t d1 and t d2 are the circuit delays of the inverter chain.

Oscillating Mechanism of an Inverter-Based RC r
A simple example of the structure and waveform of an inverter-based RC oscillator is shown in Figure 4. In practice, the gain of the inversion stages (INV1 and INV2 in Figure 4) should be large enough to allow for oscillation, and the proposed oscillator uses multiple inverters to allow for high gain [7]. When the , , and nodes are, respectively, high, low, and high, gradually decreases as discharges . When equals the LTV of INV1, where the input and output voltages are the same, and change to logical high and low states, respectively. Since the charge on the capacitor should be the same, the voltage change at the node lowers the equally, making equal to − . Next, since the node voltage decreases while stays in the high state, is charged through , and the node voltage increases. Similarly, when the charging passes the level, the node voltage rises to = + , due to the logic changes in the following inverters. The timing diagram in Figure 4 shows the charge and discharge cycles of the node, where td1 and td2 are the circuit delays of the inverter chain.
The discharge curve of is represented by the following equation: The charging equation of is: Therefore, ignoring the circuit delay, the ideal period of the inverter-based RC oscillator is calculated as being: If is equal to half of , the ideal oscillation period is , and the The discharge curve of V OSC is represented by the following equation: The charging equation of V OSC is: Therefore, ignoring the circuit delay, the ideal period of the inverter-based RC oscillator is calculated as being: If LTV INV1 is equal to half of V DD , the ideal oscillation period T OSC is R OSC C OSC ln(9), and the ideal duty cycle is 50% [7].
Taking circuit delay into consideration, the practical period of the oscillator is as follows:  Figure 5 shows the structure of the proposed inverter-based, on-chip RC oscillator. The inverter chain implemented is as small as possible to ensure low power operation. The second to sixth inverters have a standard structure, but the first-stage inverter (INV1 in Figure 5) has been reconfigured to control its LTV. The V REF from the resistive divider and V OSC are inputs to the LTV tracking feedback, and its output-V CONT -controls LTV INV1 . Charging and discharging at the V OSC node causes an oscillation due to the inverter logic switching, so the entire inverter chain can be seen to function as a comparator. INV1 is the most sensitive to noise and circuit fluctuations, as the slew rate at its input (V OSC ) is slower than that of the other nodes. Also, transistor noise in INV1 has a significant effect on circuit delay variation. Thus, because of this sensitivity, INV1 is considered to be the main comparator and its LTV is regarded as the reference voltage for comparison.  Figure 5 shows the structure of the proposed inverter-based, on-chip RC oscillator. The inverter chain implemented is as small as possible to ensure low power operation. The second to sixth inverters have a standard structure, but the first-stage inverter (INV1 in Figure 5) has been reconfigured to control its LTV. The from the resistive divider and are inputs to the LTV tracking feedback, and its output--controls . Charging and discharging at the node causes an oscillation due to the inverter logic switching, so the entire inverter chain can be seen to function as a comparator. INV1 is the most sensitive to noise and circuit fluctuations, as the slew rate at its input ( ) is slower than that of the other nodes. Also, transistor noise in INV1 has a significant effect on circuit delay variation. Thus, because of this sensitivity, INV1 is considered to be the main comparator and its LTV is regarded as the reference voltage for comparison. From Equation (5), the operating frequency of the inverter-based RC oscillator without circuit delay is a function of . Figure 6 illustrates ( = / ) of the oscillator as a function of with = 1.8 V, = 17 kΩ, and = 1.4 pF. is an inverted U-shaped curve with a maximum of 19.123 MHz when INV1 LTV is 900 mV, which is half of . In a practical oscillator, the frequency contains a circuit delay component as expressed in Equation (6), and delay variations degrade the oscillator's stability. Thus, in order to reduce the influence of these variations, a method is required to detect delay changes and to maintain a constant frequency. As shown in Figure 3, the VAF scheme senses delay variation by comparing graph areas,  Figure 5 shows the structure of the proposed inverter-based, on-chip RC oscillator. The inverter chain implemented is as small as possible to ensure low power operation. The second to sixth inverters have a standard structure, but the first-stage inverter (INV1 in Figure 5) has been reconfigured to control its LTV. The from the resistive divider and are inputs to the LTV tracking feedback, and its output--controls . Charging and discharging at the node causes an oscillation due to the inverter logic switching, so the entire inverter chain can be seen to function as a comparator. INV1 is the most sensitive to noise and circuit fluctuations, as the slew rate at its input ( ) is slower than that of the other nodes. Also, transistor noise in INV1 has a significant effect on circuit delay variation. Thus, because of this sensitivity, INV1 is considered to be the main comparator and its LTV is regarded as the reference voltage for comparison. is an inverted U-shaped curve with a maximum of 19.123 MHz when INV1 LTV is 900 mV, which is half of . In a practical oscillator, the frequency contains a circuit delay component as expressed in Equation (6), and delay variations degrade the oscillator's stability. Thus, in order to reduce the influence of these variations, a method is required to detect delay changes and to maintain a constant frequency. As shown in Figure 3, the VAF scheme senses delay variation by comparing graph areas, and the reference voltage of the comparator is changed to maintain a constant frequency.

Architecture of Proposed Oscillator
The suggested LTV tracking technique utilizes the VAF concept for control to reduce the effects of circuit delay variations. The proposed oscillator works by comparing the graph area configured by and , to estimate the delay variation. For example, if the circuit delay In a practical oscillator, the frequency contains a circuit delay component as expressed in Equation (6), and delay variations degrade the oscillator's stability. Thus, in order to reduce the influence of these variations, a method is required to detect delay changes and to maintain a constant frequency. As shown in Figure 3, the VAF scheme senses delay variation by comparing graph areas, and the reference voltage of the comparator is changed to maintain a constant frequency.
The suggested LTV tracking technique utilizes the VAF concept for LTV INV1 control to reduce the effects of circuit delay variations. The proposed oscillator works by comparing the graph area configured by V OSC and V REF , to estimate the delay variation. For example, if the circuit delay increases, the V OSC graph area grows while the area under V REF is unchanged. In addition, as demonstrated in Equation (6), this increased delay causes a decrease in oscillation frequency.
In order to achieve good frequency stability, an operating frequency compensation mechanism that responds to circuit delay variations is required. Figure 6 shows that the oscillation frequency of an inverter-based RC oscillator is determined by the LTV INV1 , unless the passive components (R OSC and C OSC ) change. Thus, the proposed LTV tracking scheme allows for the oscillator to have a constant operating frequency by adjusting the LTV INV1 from V CONT (the feedback loop output).
If the nominal value of LTV INV1 is 900 mV (half of the 1.8 V supply), the oscillation frequency variation for the LTV change is close to zero, as indicated by the horizontal tangent line in Figure 6. Furthermore, increasing or decreasing the LTV to around 900 mV only lowers the oscillator frequency relative to the maximum value, so the oscillator cannot cope with longer circuit delay situations. Therefore, because the integrator of the LTV tracking loop makes the DC voltage of V OSC equal to V REF , the proposed scheme raises the LTV INV1 by setting the resistive divider output to 1.1V, in order to control the oscillator frequency against any variations of LTV INV1 .
In this approach, the oscillator cannot sustain a 50% duty cycle, but the sensitivity of the operating frequency to LTV INV1 is increased (see the increased tangent line slope in Figure 6). When maintaining negative feedback, the increase/decrease of the LTV relative to 1.1 V causes frequency decrease/increase. Considering frequency controllability alone, LTV's larger than 1.1V can be used, but this will increase power consumption. The proposed structure enables high-frequency operation by connecting the chip supply to the inverter chain, rather than to the regulated supply, and the large voltage swing at the V OSC node reduces the comparator noise of the inverter chain [2].

The First-Stage Inverter
In a basic inverter structure consisting of one NMOS transistor and one PMOS transistor, it is not easy to change the LTV of the inverters, except for the supply voltage control. Therefore, a structural change of the inverter is required to control LTV INV1 . Figure 7a shows the proposed INV1 schematic for LTV control, where V CONT stands for the output of the feedback loop. Since the input DC voltage from LTV tracking feedback (V REF ) is 1.1 V for oscillation frequency control, the V CONT value is set so that LTV INV1 becomes 1.1 V. Transistors PM2 and NM2 are stacked in the output path, and the substrate of NM2 is connected to V CONT . PM3 and NM3, with V CONT as inputs, are connected to the main inverter path, forming an auxiliary path through a resistor connected to each source node. increases, the graph area grows while the area under is unchanged. In addition, as demonstrated in Equation (6), this increased delay causes a decrease in oscillation frequency.
In order to achieve good frequency stability, an operating frequency compensation mechanism that responds to circuit delay variations is required. Figure 6 shows that the oscillation frequency of an inverter-based RC oscillator is determined by the , unless the passive components ( and ) change. Thus, the proposed LTV tracking scheme allows for the oscillator to have a constant operating frequency by adjusting the from (the feedback loop output). If the nominal value of is 900 mV (half of the 1.8 V supply), the oscillation frequency variation for the LTV change is close to zero, as indicated by the horizontal tangent line in Figure 6. Furthermore, increasing or decreasing the LTV to around 900 mV only lowers the oscillator frequency relative to the maximum value, so the oscillator cannot cope with longer circuit delay situations. Therefore, because the integrator of the LTV tracking loop makes the DC voltage of equal to , the proposed scheme raises the by setting the resistive divider output to 1.1V , in order to control the oscillator frequency against any variations of . In this approach, the oscillator cannot sustain a 50% duty cycle, but the sensitivity of the operating frequency to is increased (see the increased tangent line slope in Figure 6). When maintaining negative feedback, the increase/decrease of the LTV relative to 1.1 V causes frequency decrease/increase. Considering frequency controllability alone, LTV's larger than 1.1V can be used, but this will increase power consumption. The proposed structure enables high-frequency operation by connecting the chip supply to the inverter chain, rather than to the regulated supply, and the large voltage swing at the node reduces the comparator noise of the inverter chain [2]. In a basic inverter structure consisting of one NMOS transistor and one PMOS transistor, it is not easy to change the LTV of the inverters, except for the supply voltage control. Therefore, a structural change of the inverter is required to control . Figure 7a shows the proposed INV1 schematic for LTV control, where stands for the output of the feedback loop. Since the input DC voltage from LTV tracking feedback ( ) is 1.1 V for oscillation frequency control, the value is set so that becomes 1.1 V. Transistors PM2 and NM2 are stacked in the output path, and the substrate of NM2 is connected to . PM3 and NM3, with as inputs, are connected to the main inverter path, forming an auxiliary path through a resistor connected to each source node.

The First-Stage Inverter
Changing the supply voltage to adjust the inverter's LTV further lowers the frequency stability Changing the supply voltage to adjust the inverter's LTV further lowers the frequency stability of the inverter chain-based RC oscillator. Also, to maintain the supply voltage, a large chip area is required to change the LTV, using the driving current from multiple connected transistors with switches.
However, the proposed method controls LTV INV1 relative to 1.1 V, by controlling the pull-down strength with V CONT while using a simple structure. An increased V CONT reduces the current drive capability of the NMOS pull-down path [9], resulting in a higher LTV INV1 . Thus, the oscillation frequency decreases according to Equation (5), as illustrated in Figure 6. In addition, because a decreased V CONT leads to a lower LTV INV1 , an increase/decrease in V CONT causes a decrease/increase in oscillator frequency. Figure 7b shows the change in LTV INV1 when the control voltage V CONT varies from 0.9 V to 1.4 V. Since the nominal voltage of LTV INV1 is set to 1.1 V, the positive V CONT turns on the PN diode between the substrate node and the source node of NM2 in Figure 7a. The increase in V CONT causes the drain-source current of NM2 to be reduced, by increasing its substrate-source diode current while the drain-source current of NM1 is constant. In this situation, LTV INV1 increases because the reduced I DS,NM2 weakens the inverter pull-down strength. Consequently, LTV INV1 is controlled by V CONT which determines the current capability. Furthermore, the auxiliary path consisting of PM3 and NM3 increases the sensitivity of INV1 to the control voltage. This is because the additional structure not only helps the LTV tracking loop settle the output, but also adjusts the amount of INV1 pull-down current.
In [5], the authors introduced an on-chip relaxation oscillator flicker noise suppression method, by modeling the relaxation oscillator as a voltage-controlled oscillator (VCO) and applying the VAF technique. Since the VAF loop creates a high-pass filter, closed-loop transfer function for phase noise, the low-frequency offset phase noise is reduced.
The suggested inverter-based RC oscillator is also a VCO, the frequency of which is controlled by LTV INV1 , and we use the VAF concept for the negative feedback structure. The proposed LTV tracking feedback decreases flicker noise in the oscillator, because the noise transfer function in [5] can be applied. Figure 8 shows the noise transfer model, especially for the oscillator phase noise. drive capability of the NMOS pull-down path [9], resulting in a higher . Thus, the oscillation frequency decreases according to Equation (5), as illustrated in Figure 6. In addition, because a decreased leads to a lower , an increase/decrease in causes a decrease/increase in oscillator frequency. Figure 7b shows the change in when the control voltage varies from 0.9 V to 1.4 V. Since the nominal voltage of is set to 1.1 V, the positive turns on the PN diode between the substrate node and the source node of NM2 in Figure 7a. The increase in causes the drain-source current of NM2 to be reduced, by increasing its substrate-source diode current while the drain-source current of NM1 is constant. In this situation, increases because the reduced , weakens the inverter pull-down strength. Consequently, is controlled by which determines the current capability. Furthermore, the auxiliary path consisting of PM3 and NM3 increases the sensitivity of INV1 to the control voltage. This is because the additional structure not only helps the LTV tracking loop settle the output, but also adjusts the amount of INV1 pull-down current.
In [5], the authors introduced an on-chip relaxation oscillator flicker noise suppression method, by modeling the relaxation oscillator as a voltage-controlled oscillator (VCO) and applying the VAF technique. Since the VAF loop creates a high-pass filter, closed-loop transfer function for phase noise, the low-frequency offset phase noise is reduced.
The suggested inverter-based RC oscillator is also a VCO, the frequency of which is controlled by LTVINV1, and we use the VAF concept for the negative feedback structure. The proposed LTV tracking feedback decreases flicker noise in the oscillator, because the noise transfer function in [5] can be applied. Figure 8 shows the noise transfer model, especially for the oscillator phase noise. The phase noise of the VCO part is formulated as follows: Unlike the phase noise transfer function in [5], Equation (7) requires a voltage scaling factor . This is because multiplying the output of the integrator by produces , which controls the frequency of the oscillator. Equation (7)-with a high-pass, closed-loop transfer function characteristic-has zero and pole at fz and fp, which are described in the following equations: Adjusting from 1 V to 1.4 V changes the from 1.183 V to 1.02 V, resulting in a value of 0.41 (absolute value without polarity). Under this condition, the calculated is 41.8 × 10 6 rad/sec•V, and the scaling factor γ is 0.38 V/MHz. Since and are 1.26 MΩ, and The phase noise of the VCO part is formulated as follows: Unlike the phase noise transfer function in [5], Equation (7) requires a voltage scaling factor K A . This is because multiplying the output of the integrator V CONT by K A produces LTV INV1 , which controls the frequency of the oscillator. Equation (7)-with a high-pass, closed-loop transfer function characteristic-has zero and pole at f z and f p , which are described in the following equations: Adjusting V CONT from 1 V to 1.4 V changes the LTV INV1 from 1.183 V to 1.02 V, resulting in a K A value of 0.41 (absolute value without polarity). Under this condition, the calculated K VCO is 41.8 × 10 6 rad/sec·V, and the scaling factor γ is 0.38 V/MHz. Since R INTG and C INTG are 1.26 MΩ, and 1.93 pF, respectively, the simulated f p is 652.864 kHz, which is large enough to suppress the low frequency offset phase noise.

Simulation and Measurement Results
The proposed LTV tracking, inverter-based RC oscillator was fabricated in a 0.18 µm standard CMOS process, and Figure 9a shows the layout of the suggested oscillator. Figure 9b illustrates the chip die photo, the active area of which is 310 µm × 180 µm. The passive components that make up the reference voltage divider and the VAF integrating node, especially the resistors, cover a large area. The suggested design, with a nominal 1.8 V power supply, oscillates at 18.13 MHz, consuming 245.7 µW. Figure 9c shows the simulated power distribution ratio of each block in the proposed oscillator. The highest power consumers are R OSC and the first-stage inverter due to the charge/discharge operation and LTV control 1.93 pF, respectively, the simulated is 652.864 kHz, which is large enough to suppress the low frequency offset phase noise. The proposed LTV tracking, inverter-based RC oscillator was fabricated in a 0.18 μm standard CMOS process, and Figure 9a shows the layout of the suggested oscillator. Figure 9b illustrates the chip die photo, the active area of which is 310 μm × 180 μm. The passive components that make up the reference voltage divider and the VAF integrating node, especially the resistors, cover a large area. The suggested design, with a nominal 1.8 V power supply, oscillates at 18.13 MHz, consuming 245.7 μW. Figure 9c shows the simulated power distribution ratio of each block in the proposed oscillator.

Simulation and Measurement Results
The highest power consumers are and the first-stage inverter due to the charge/discharge operation and LTV control  In the INV1 schematic of Figure 8a, the input V CONT of PM3 and NM3 is disconnected, and the substrate of NM2 is tied to ground in order to implement a feedback-free structure. Figure 10 illustrates the simulated phase noise characteristics. The technique proposed in the simulation reduces oscillator phase noise by 4 dBc/Hz and 2 dBc/Hz at low-and high-frequency offsets, respectively. Figure 11 shows the measured phase noise characteristics when there is (a) no feedback, and (b) the suggested method is applied. As a result of the negative feedback that constitutes the LTV tracking loop, the proposed scheme reduces phase noise at low-frequency offsets. The phase noise at both the 100 Hz and the 1 kHz frequency offsets is decreased by 7.7 dBc/Hz (from -44.72 dBc/Hz to 52.42 dBc/Hz) and 5.45 dBc/Hz (from -54.64 dBc/Hz to -60.09 dBc/Hz), respectively. In the feedback-free structure, circuit noise produces some unwanted tones near 100 kHz, degrading the phase noise characteristics, while the proposed LTV tracking technique filters these tones out but still produces the 400 kHz tones. Compared with the simulation, the overall phase noise level is increased in the measurement. However, the amount of noise suppression remains similar. 1.93 pF, respectively, the simulated is 652.864 kHz, which is large enough to suppress the low frequency offset phase noise. The proposed LTV tracking, inverter-based RC oscillator was fabricated in a 0.18 μm standard CMOS process, and Figure 9a shows the layout of the suggested oscillator. Figure 9b illustrates the chip die photo, the active area of which is 310 μm × 180 μm. The passive components that make up the reference voltage divider and the VAF integrating node, especially the resistors, cover a large area. The suggested design, with a nominal 1.8 V power supply, oscillates at 18.13 MHz, consuming 245.7 μW. Figure 9c shows the simulated power distribution ratio of each block in the proposed oscillator.

Simulation and Measurement Results
The highest power consumers are and the first-stage inverter due to the charge/discharge operation and LTV control    In the INV1 schematic of Figure 8a, the input of PM3 and NM3 is disconnected, and the substrate of NM2 is tied to ground in order to implement a feedback-free structure. Figure 10 illustrates the simulated phase noise characteristics. The technique proposed in the simulation reduces oscillator phase noise by 4 dBc/Hz and 2 dBc/Hz at low-and high-frequency offsets, respectively. Figure  11 shows the measured phase noise characteristics when there is (a) no feedback, and (b) the suggested Figure 11. Measured phase noise of the proposed oscillator: (a) without the feedback mechanism; (b) with the feedback mechanism.
The figure of merit (FOM), which measures the performance of an oscillator, can be expressed by the following two equations. L(∆ f ), f OSC , and P DISS represent phase noise at offset frequency, oscillation frequency, and power consumption, respectively.
Under the measurement conditions, the proposed oscillator has FOM 1 values of 151.35 and 157.53 at 1 kHz and 100 kHz frequency offsets, respectively, and shows an FOM 2 value of 108.7.
The oscillation frequency, with respect to supply voltage, is illustrated in Figure 12. The solid line depicts the frequency variation of the proposed approach, and the dotted line shows the results without feedback. For a range of 1.7 V to 2.4 V, the proposed oscillator's frequency variation is calculated as a maximum of 0.365(%/0.1 V), while without feedback, the effect of the supply voltage on the oscillation frequency is 0.522(%/0.1 V).
Electronics 2019, 8, x FOR PEER REVIEW 9 of 11 method is applied. As a result of the negative feedback that constitutes the LTV tracking loop, the proposed scheme reduces phase noise at low-frequency offsets. The phase noise at both the 100 Hz and the 1 kHz frequency offsets is decreased by 7.7 dBc/Hz (from -44.72 dBc/Hz to 52.42 dBc/Hz) and 5.45 dBc/Hz (from -54.64 dBc/Hz to -60.09 dBc/Hz), respectively. In the feedback-free structure, circuit noise produces some unwanted tones near 100 kHz, degrading the phase noise characteristics, while the proposed LTV tracking technique filters these tones out but still produces the 400 kHz tones. Compared with the simulation, the overall phase noise level is increased in the measurement. However, the amount of noise suppression remains similar. The figure of merit (FOM), which measures the performance of an oscillator, can be expressed by the following two equations. ∆ , , and represent phase noise at offset frequency, oscillation frequency, and power consumption, respectively.
Under the measurement conditions, the proposed oscillator has values of 151.35 and 157.53 at 1 kHz and 100 kHz frequency offsets, respectively, and shows an value of 108.7. The oscillation frequency, with respect to supply voltage, is illustrated in Figure 12. The solid line depicts the frequency variation of the proposed approach, and the dotted line shows the results without feedback. For a range of 1.7 V to 2.4 V, the proposed oscillator's frequency variation is calculated as a maximum of 0.365(%/0.1 V), while without feedback, the effect of the supply voltage on the oscillation frequency is 0.522(%/0.1 V). Table 1 tabulates the performance of the proposed LTV tracking oscillator and other state-ofthe-art designs. The oscillators of [5] and [8] display good frequency stability against supply variation, but their respective values are significantly low, due to the degradation of their phase noise characteristics at the offset frequencies. In [2], the highest value was demonstrated, but in comparison, our approach reduces frequency inaccuracy with supply variations. Although our proposal requires a larger chip area for passive components, the method displays FOMs comparable to other methods, due to suppressed phase noise and good frequency stability.  Table 1 tabulates the performance of the proposed LTV tracking oscillator and other state-of-the-art designs. The oscillators of [5] and [8] display good frequency stability against supply variation, but their respective FOM 1 values are significantly low, due to the degradation of their phase noise characteristics at the offset frequencies. In [2], the highest FOM 1 value was demonstrated, but in comparison, our approach reduces frequency inaccuracy with supply variations. Although our proposal requires a larger chip area for passive components, the method displays FOMs comparable to other methods, due to suppressed phase noise and good frequency stability.  1 Excludes the power of the anti-jitter comparator. 2 Includes the power of the anti-jitter comparator.

Discussion and Conclusions
This article suggests a method of suppressing flicker noise in an inverter-based, on-chip RC oscillator. By changing LTV INV1 with an adjusted pull-down strength in the first-stage inverter, the proposed LTV tracking feedback not only compensates for circuit delay variations, but also reduces low-frequency offset phase noise. The proposed oscillator operates at 18.13 MHz, consuming 245.7 µW from a 1.8 V power supply. The worst-case frequency variation with supply variation is 0.365%/0.1 V. The suggested technique reduces oscillator phase noise by 7.7 dBc/Hz and 5.45 dBc/Hz for 100 Hz and 1 kHz frequency offsets, respectively. Furthermore, the proposed oscillator shows FOM values comparable with those of the latest technologies.