A CMOS Transmitter Analog Baseband for 5G Mobile Communication

: CMOS analog baseband circuits including a low-pass ﬁlter (LPF) and a programmable gain ampliﬁer (PGA) are designed and implemented for the ﬁfth-generation (5G) mobile communication. The super source follower topology is adopted to achieve a wideband LPF with good linearity, while the constant current density gain control technique is used to implement gain cells of the PGA. The circuits are integrated as an analog baseband for a 5G transmitter (TX) and fabricated using TSMC 90-nm CMOS technology. The analog baseband exhibits the bandwidth from 1.03 to 1.05 GHz when the voltage gain is varied from − 18.9 dB to 3.8 dB in 1-dB steps. The gain step errors are within − 0.7 dB to + 0.9 dB. In the highest gain mode, the analog baseband achieves the IP 1dB of − 10 dBv and the IIP3 of − 0.2 dBv. Over the band of interest, the NF of the analog baseband is 24.4–40.0 dB.


Introduction
The vision, spectrum, and technology views of the fifth-generation (5G) mobile communication have been fully rolled out. In 2020, the definition of 5G technology will also be finalized. According to the 5G standard, IMT 2020, the total download capacity for a single 5G mobile cell must be at least 20 Gbps [1]. A channel bandwidth of at least 1 GHz would be demanded to accommodate the wideband signals. Therefore, it is necessary for analog baseband circuits in RF transceivers to achieve the bandwidth above 1 GHz. Figure 1 shows the block diagram of an RF transmitter for 5G mobile communication. The baseband signals from the digital-to-analog converter would be delivered to the analog baseband including the low-pass filter (LPF) and the programmable gain amplifier (PGA).
Then the LPF provides out-of-band rejection to solve the anti-aliasing issue, while the PGA maintains the adequate signal level for the up-conversion mixer. The object of this work is to design these analog baseband circuits.
For LPFs, large out-of-band rejection can be achieved by increasing the filter order or introducing transmission zeroes. Increasing the filter order usually leads to higher power consumption. Moreover, it may raise stability and noise issues. Therefore, filters equipped with transmission zeroes are better choices for wireless applications that require high out-of-band rejection. With transmission zeroes allocated in the stopband, Elliptic filters can achieve higher attenuation, as compared to Chebyshev or Butterworth filters, so they have been commonly used in modern wireless communication systems supporting multi-carrier modulation [2][3][4]. In general, dB-linear PGAs can be categorized into close-loop and open-loop amplifiers. For a closeloop amplifier, good linearity can be achieved due to the feedback architecture, while the dB-linear gain can be easily obtained since the gain is usually determined by the ratio between resistors [5]. However, it requires numerous resistors and switches to achieve the small gain step error, which results in large chip area. The transistors, as switches of the resistor array in the feedback network, usually operate in the triode region and introduce a significant source of nonlinearity. The open-loop amplifiers may be more suitable for 5G applications considering the low power and wideband characteristics, where the wide bandwidth can be easily achieved without stability issues. The required gain range can be obtained by connecting multiple gain stages in cascade and using several linear terms for each gain stage [6][7][8][9].
In this work, a transmitter analog baseband for 5G mobile communication is designed and implemented. The Elliptic filter is adopted to realize the LPF, while the open-loop amplifier is adopted to realize the dB-liner PGA. The rest of the paper is organized as follows. In Section 2, the design of the LPF and PGA would be presented. In Section 3, the measurement results of the LPF and the transmitter analog baseband would be reported. Finally, the conclusion would be given in Section 4.

A. Low-Pass-Filter (LPF)
Because of the characteristics of high input resistance and low output resistance, source followers are often used as buffers. In fact, they can be simply modified into continuous-time filters by synthesizing complex poles with the feedback and capacitors [3]. A super source follower is an improved version of the source follower. By adding an additional MOSFET to form a feedback loop, the output impedance can be reduced by a factor of the loop gain [4]. In this work, a super source follower based low-pass-filter is implemented. Figure 2a shows the schematic of a super-sourcefollower (SSF). The super source follower contains an additional local feedback formed by the transistor M2. Transistors M3 and M4 are current sources. The output resistance of the SSF can be analyzed as follows. The input voltage is kept constant and let us assume that the output now experiences a voltage drop. The voltage drop not only raises the drain current of M1 but also lowers the gate voltage of M2. Hence, the drain current of M2 would be increased. The output resistance is therefore reduced because of this incremental current flow through the output node. The output resistance of an SSF can be expressed as: Notably, the output resistance of SSF is lower by a factor of gm2ro3, as compared with that of a conventional source follower. The dc voltage gain A0, is given in Equation (2), where the output resistance ro of each transistor is considered: In general, dB-linear PGAs can be categorized into close-loop and open-loop amplifiers. For a close-loop amplifier, good linearity can be achieved due to the feedback architecture, while the dB-linear gain can be easily obtained since the gain is usually determined by the ratio between resistors [5]. However, it requires numerous resistors and switches to achieve the small gain step error, which results in large chip area. The transistors, as switches of the resistor array in the feedback network, usually operate in the triode region and introduce a significant source of nonlinearity. The open-loop amplifiers may be more suitable for 5G applications considering the low power and wideband characteristics, where the wide bandwidth can be easily achieved without stability issues. The required gain range can be obtained by connecting multiple gain stages in cascade and using several linear terms for each gain stage [6][7][8][9].
In this work, a transmitter analog baseband for 5G mobile communication is designed and implemented. The Elliptic filter is adopted to realize the LPF, while the open-loop amplifier is adopted to realize the dB-liner PGA. The rest of the paper is organized as follows. In Section 2, the design of the LPF and PGA would be presented. In Section 3, the measurement results of the LPF and the transmitter analog baseband would be reported. Finally, the conclusion would be given in Section 4.

Low-Pass-Filter (LPF)
Because of the characteristics of high input resistance and low output resistance, source followers are often used as buffers. In fact, they can be simply modified into continuous-time filters by synthesizing complex poles with the feedback and capacitors [3]. A super source follower is an improved version of the source follower. By adding an additional MOSFET to form a feedback loop, the output impedance can be reduced by a factor of the loop gain [4]. In this work, a super source follower based low-pass-filter is implemented. Figure 2a shows the schematic of a super-source-follower (SSF). The super source follower contains an additional local feedback formed by the transistor M 2 . Transistors M 3 and M 4 are current sources. The output resistance of the SSF can be analyzed as follows. The input voltage is kept constant and let us assume that the output now experiences a voltage drop. The voltage drop not only raises the drain current of M 1 but also lowers the gate voltage of M 2 . Hence, the drain current of M 2 would be increased. The output resistance is therefore reduced because of this incremental current flow through the output node. The output resistance of an SSF can be expressed as: Notably, the output resistance of SSF is lower by a factor of g m2 r o3 , as compared with that of a conventional source follower. The dc voltage gain A 0 , is given in Equation (2), where the output resistance r o of each transistor is considered: A 0 = (g m1 r o1 r o24 + g m1 g m2 r o1 r o3 r o24 )/(r o1 + r o3 + r o24 + g m1 r o1 r o24 + g m2 r o3 r o24 + g m1 g m2 r o1 r o3 r o24 ) ≈ 1. (2) The resistor r o24 represents the equivalent resistance of resistors r o2 and r o4 in parallel. With the reduced output resistance and improved gain, the SSF shows better driving capability, as compared to the traditional source follower.
The SSF is modified into a biquadratic low-pass filter, as shown in Figure 2b, where capacitors C 1 and C 2 are employed to synthesis poles. In parallel with the main signal path, the gate-source capacitance of M 1 (C gs1 ) is naturally associated with a high frequency zero. Since the LPF requires a transmission zero at 2.2 GHz, a capacitor C Z is included to move the transmission zero to the desired frequency. The transfer function of the SSF-based biquadratic filter is expressed in (3): From the formula (3), the complex pole ω 0 , the quality factor Q and the transmission zero ω z can be obtained, as expressed in (4), (5), and (6) respectively: In this work, a fourth-order Elliptic LPF is designed to provide anti-aliasing function for 5G mobile communication. The fourth-order LPF is formed from two SSF biquadratic low-pass filters in cascade, as shown in Figure 3, where the two filters use different types of input transistors so that the level shifting effect is compensated to obtain identical input and output common mode voltages [4]. At the initial stage of design, the software "Filter Solutions" is used to determine the key parameters for the fourth-order Elliptic LPF. According to the calculation results of "Filter Solutions", the cut-off frequency, transmission zero, and quality factor of the first biquadratic low-pass filter are set to 707 MHz, 2.2 GHz, and 0.73, respectively, while the cut-off frequency, transmission, and quality factor of the second biquadratic low-pass filter are set to 1.13 GHz, 5.27 GHz, and 3.45, respectively. Since small capacitors are used to synthesize high-frequency poles and zeroes, the LPF is very susceptible to parasitic capacitances. In order to achieve the desired frequency response, the capacitors C 1 , C 2 , and C Z in the biquadratic low-pass filter are chosen by considering all the inevitable parasitic capacitances in the circuit. Moreover, the capacitors C 1 and C 2 are realized with 2-bit programmable capacitors in the first biquadratic low-pass filter so that the corner frequency and transmission zero of the LPF can be tuned to cope with process-voltage-temperature variations. The resistor ro24 represents the equivalent resistance of resistors ro2 and ro4 in parallel. With the reduced output resistance and improved gain, the SSF shows better driving capability, as compared to the traditional source follower.
The SSF is modified into a biquadratic low-pass filter, as shown in Figure 2b, where capacitors C1 and C2 are employed to synthesis poles. In parallel with the main signal path, the gate-source capacitance of M1 (Cgs1) is naturally associated with a high frequency zero. Since the LPF requires a transmission zero at 2.2 GHz, a capacitor CZ is included to move the transmission zero to the desired frequency. The transfer function of the SSF-based biquadratic filter is expressed in (3): From the formula (3), the complex pole ω0, the quality factor Q and the transmission zero ωz can be obtained, as expressed in (4), (5), and (6) respectively: In this work, a fourth-order Elliptic LPF is designed to provide anti-aliasing function for 5G mobile communication. The fourth-order LPF is formed from two SSF biquadratic low-pass filters in cascade, as shown in Figure 3, where the two filters use different types of input transistors so that the level shifting effect is compensated to obtain identical input and output common mode voltages [4]. At the initial stage of design, the software "Filter Solutions" is used to determine the key parameters for the fourth-order Elliptic LPF. According to the calculation results of "Filter Solutions", the cut-off frequency, transmission zero, and quality factor of the first biquadratic low-pass filter are set to 707 MHz, 2.2 GHz, and 0.73, respectively, while the cut-off frequency, transmission, and quality factor of the second biquadratic low-pass filter are set to 1.13 GHz, 5.27 GHz, and 3.45, respectively. Since small capacitors are used to synthesize high-frequency poles and zeroes, the LPF is very susceptible to parasitic capacitances. In order to achieve the desired frequency response, the capacitors C1, C2, and CZ in the biquadratic low-pass filter are chosen by considering all the inevitable parasitic capacitances in the circuit. Moreover, the capacitors C1 and C2 are realized with 2-bit programmable capacitors in the first biquadratic low-pass filter so that the corner frequency and transmission zero of the LPF can be tuned to cope with process-voltage-temperature variations.

B. Programmable Gain Amplifier (PGA)
Unwanted spurs appearing in the output spectrum of an up-conversion mixer can cause serious spectrum regrowth. Since their levels are closely related to the input level of the mixer, it is necessary for the PGA to pass the mixer with a specified signal level so that these spurs can be down by 40-50 dBc. According to the simulation results of the up-conversion mixer, the desired input level of the mixer is 200 mVpp. Therefore, the PGA is designed to maintain the output level of 200 mVpp for an input dynamic range of 20 dB. With the programmable voltage gain from −16 dB to 4 dB, the PGA can handle the input level from 1.26 Vpp to 126 mVpp.
An open-loop-configured PGA is designed and implemented to achieve the required gain range. The block diagram of the programmable gain amplifier is shown in Figure 4. Considering the tradeoff between the power consumption and bandwidth, four gain cells are connected in cascade to achieve the desired gain range. The 5-bit binary control word B1-B5 is translated into the 20-bit thermometer code S1-S20 by a switch decoder, as shown in Figure 4. The first gain cell (A-type gain cell) of the PGA is a common-source amplifier with resistive source degeneration ( Figure 5). This gain cell provides the gain of −16 dB so that large baseband signals can be attenuated in the first stage. In this way, the linearity requirement of the rest gain cells can be relaxed.
The rest gain cells (B-type gain cell) are common-source amplifiers using the constant current density function ( Figure 6) [9]. Each B-type gain cell contains two transistor arrays (an input transistor array and an auxiliary array), connected in parallel, where each transistor in the arrays is connected with a switch in series. The switches controlled by the digital word S1-Sn would be used to turn on or off the corresponding transistors MS1-MSn in the input transistor array while the switches controlled by the digital word  would be used to turn on or off the corresponding transistors MS1-MSn in the auxiliary array. In particular, the auxiliary array is applied with same input DC level (VCM) and contains transistors identical to those in the input transistor array so that the output dc level can remain constant for each gain mode [9].
If KS0-KSn represent the W/L ratios of the corresponding transistors MS0-MSn, then the effective W/L ratio Kn of the input transistor array can be expressed as: The effective transconductance gmn can be expressed as: The gain equals the product of the effective transconductance gmn and the load resistor RL, and can be expressed as follows:

Programmable Gain Amplifier (PGA)
Unwanted spurs appearing in the output spectrum of an up-conversion mixer can cause serious spectrum regrowth. Since their levels are closely related to the input level of the mixer, it is necessary for the PGA to pass the mixer with a specified signal level so that these spurs can be down by 40-50 dBc. According to the simulation results of the up-conversion mixer, the desired input level of the mixer is 200 mV pp . Therefore, the PGA is designed to maintain the output level of 200 mV pp for an input dynamic range of 20 dB. With the programmable voltage gain from −16 dB to 4 dB, the PGA can handle the input level from 1.26 V pp to 126 mV pp .
An open-loop-configured PGA is designed and implemented to achieve the required gain range. The block diagram of the programmable gain amplifier is shown in Figure 4. Considering the tradeoff between the power consumption and bandwidth, four gain cells are connected in cascade to achieve the desired gain range. The 5-bit binary control word B 1 -B 5 is translated into the 20-bit thermometer code S 1 -S 20 by a switch decoder, as shown in Figure 4. The first gain cell (A-type gain cell) of the PGA is a common-source amplifier with resistive source degeneration ( Figure 5). This gain cell provides the gain of −16 dB so that large baseband signals can be attenuated in the first stage. In this way, the linearity requirement of the rest gain cells can be relaxed.
The rest gain cells (B-type gain cell) are common-source amplifiers using the constant current density function ( Figure 6) [9]. Each B-type gain cell contains two transistor arrays (an input transistor array and an auxiliary array), connected in parallel, where each transistor in the arrays is connected with a switch in series. The switches controlled by the digital word S 1 -S n would be used to turn on or off the corresponding transistors M S1 -M Sn in the input transistor array while the switches controlled by the digital word S 1 − S n would be used to turn on or off the corresponding transistors M S1 -M Sn in the auxiliary array. In particular, the auxiliary array is applied with same input DC level (V CM ) and contains transistors identical to those in the input transistor array so that the output dc level can remain constant for each gain mode [9].
If K S0 -K Sn represent the W/L ratios of the corresponding transistors M S0 -M Sn , then the effective W/L ratio K n of the input transistor array can be expressed as: The effective transconductance g mn can be expressed as: The gain equals the product of the effective transconductance g mn and the load resistor R L , and can be expressed as follows:
The voltage gain of each B-type gain cell can be varied from 0 to 7 dB in 1-dB steps. When all the gain cells are connected in cascade (as shown in Figure 4), the gain range of 20 dB can be provided. During the simulation, the PGA delivers the voltage gain of 3.92 dB and −16.1 dB for the 5-bit binary programming word of 10,100 and 00,000, respectively.
A buffer (Figure 7) is used to drive the 50-Ω load of the network analyzer during the measurement. Moreover, it can also maintain the required bandwidth and linearity by minimizing the loading effect of the up-conversion mixer in the future. Based on the fT-doubler architecture, the
The voltage gain of each B-type gain cell can be varied from 0 to 7 dB in 1-dB steps. When all the gain cells are connected in cascade (as shown in Figure 4), the gain range of 20 dB can be provided. During the simulation, the PGA delivers the voltage gain of 3.92 dB and −16.1 dB for the 5-bit binary programming word of 10,100 and 00,000, respectively.
A buffer (Figure 7) is used to drive the 50-Ω load of the network analyzer during the measurement. Moreover, it can also maintain the required bandwidth and linearity by minimizing the loading effect of the up-conversion mixer in the future. Based on the fT-doubler architecture, the  The voltage gain of each B-type gain cell can be varied from 0 to 7 dB in 1-dB steps. When all the gain cells are connected in cascade (as shown in Figure 4), the gain range of 20 dB can be provided. During the simulation, the PGA delivers the voltage gain of 3.92 dB and −16.1 dB for the 5-bit binary programming word of 10,100 and 00,000, respectively.
A buffer (Figure 7) is used to drive the 50-Ω load of the network analyzer during the measurement. Moreover, it can also maintain the required bandwidth and linearity by minimizing the loading effect of the up-conversion mixer in the future. Based on the fT-doubler architecture, the The voltage gain of each B-type gain cell can be varied from 0 to 7 dB in 1-dB steps. When all the gain cells are connected in cascade (as shown in Figure 4), the gain range of 20 dB can be provided. During the simulation, the PGA delivers the voltage gain of 3.92 dB and −16.1 dB for the 5-bit binary programming word of 10,100 and 00,000, respectively.
A buffer (Figure 7) is used to drive the 50-Ω load of the network analyzer during the measurement. Moreover, it can also maintain the required bandwidth and linearity by minimizing the loading effect of the up-conversion mixer in the future. Based on the f T -doubler architecture, the buffer delivers a high output current to extend the unit-gain frequency. During the simulation, the loading effect is considered by connecting an up-conversion mixer to the output of the buffer. According to the simulation, the buffer achieves the total harmonic distortion (THD) of −47 dB for the input level of 200 mV pp and the 3-dB bandwidth of 1.7 GHz.  The frequency response of the PGA is observed in different gain modes during the simulation. The PGA exhibits the 3-dB bandwidth above 1.2 GHz in all the gain modes. The power gain S21 is more available for the measurement with frequency range up to 1-2 GHz, while the voltage gain is specified as the requirement for analog baseband circuits, so the simulation is performed to observe both the voltage gain and power gain S21. The simulation results of the voltage gain and gain error deviation in all the gain modes are shown in Figure 8a. The gain step error is within ± 0.11 dB and the maximum gain error deviation is less than 0.23 dB. The simulation results of the S21 and gain error deviations in all the gain modes are shown in Figure 8b. The gain step error is within ± 0.23 dB and the maximum gain error deviation is less than 0.52 dB. According to the simulation results, the circuit delivers the voltage gain of 3.92 dB in the highest gain mode and the corresponding S21 is −16.17 dB. In the lowest gain mode, the circuit delivers the voltage gain of −16.1 dB and the corresponding S21 is −36.99 dB. The frequency response of the PGA is observed in different gain modes during the simulation. The PGA exhibits the 3-dB bandwidth above 1.2 GHz in all the gain modes. The power gain S 21 is more available for the measurement with frequency range up to 1-2 GHz, while the voltage gain is specified as the requirement for analog baseband circuits, so the simulation is performed to observe both the voltage gain and power gain S 21 . The simulation results of the voltage gain and gain error deviation in all the gain modes are shown in Figure 8a. The gain step error is within ± 0.11 dB and the maximum gain error deviation is less than 0.23 dB. The simulation results of the S 21 and gain error deviations in all the gain modes are shown in Figure 8b. The gain step error is within ± 0.23 dB and the maximum gain error deviation is less than 0.52 dB. According to the simulation results, the circuit delivers the voltage gain of 3.92 dB in the highest gain mode and the corresponding S 21 is −16.17 dB. In the lowest gain mode, the circuit delivers the voltage gain of −16.1 dB and the corresponding S 21 is −36.99 dB.  The frequency response of the PGA is observed in different gain modes during the simulation. The PGA exhibits the 3-dB bandwidth above 1.2 GHz in all the gain modes. The power gain S21 is more available for the measurement with frequency range up to 1-2 GHz, while the voltage gain is specified as the requirement for analog baseband circuits, so the simulation is performed to observe both the voltage gain and power gain S21. The simulation results of the voltage gain and gain error deviation in all the gain modes are shown in Figure 8a. The gain step error is within ± 0.11 dB and the maximum gain error deviation is less than 0.23 dB. The simulation results of the S21 and gain error deviations in all the gain modes are shown in Figure 8b. The gain step error is within ± 0.23 dB and the maximum gain error deviation is less than 0.52 dB. According to the simulation results, the circuit delivers the voltage gain of 3.92 dB in the highest gain mode and the corresponding S21 is −16.17 dB. In the lowest gain mode, the circuit delivers the voltage gain of −16.1 dB and the corresponding S21 is −36.99 dB.

Measurement Results
The TX analog baseband consisting of the LPF and PGA is fabricated in TSMC 90-nm CMOS process. The chip photo is shown in Figure 10 and the circuit occupies an active area of 0.24 mm 2 . According to the simulation, the circuit consumes 43 mW when it operates under the 1.2 V supply. However, the circuit consumes the power of 93 mW from the 1.2-V supply during the measurement. Such discrepancy may result from the gate leakage current.

A. LPF Measurement Result
The measured S21 of the first biquadratic filter is shown in Figure 11. With the 2-bit programmable capacitor, the cut-off frequency of the first biquadratic filter can be varied from 0.58 GHz to 1.2 GHz, with the transmission zero correspondingly varied from 2.03 GHz to 3.33 GHz. Figure 12 shows the measured S21 of the fourth-order Elliptic LPF. The cut-off frequency ω0 and transmission zeroes ωZ1 and ωZ2 are listed in Table 1. The cut-off frequencies can be varied from 0.76

Measurement Results
The TX analog baseband consisting of the LPF and PGA is fabricated in TSMC 90-nm CMOS process. The chip photo is shown in Figure 10 and the circuit occupies an active area of 0.24 mm 2 . According to the simulation, the circuit consumes 43 mW when it operates under the 1.2 V supply. However, the circuit consumes the power of 93 mW from the 1.2-V supply during the measurement. Such discrepancy may result from the gate leakage current.

Measurement Results
The TX analog baseband consisting of the LPF and PGA is fabricated in TSMC 90-nm CMOS process. The chip photo is shown in Figure 10 and the circuit occupies an active area of 0.24 mm 2 . According to the simulation, the circuit consumes 43 mW when it operates under the 1.2 V supply. However, the circuit consumes the power of 93 mW from the 1.2-V supply during the measurement. Such discrepancy may result from the gate leakage current.

A. LPF Measurement Result
The measured S21 of the first biquadratic filter is shown in Figure 11. With the 2-bit programmable capacitor, the cut-off frequency of the first biquadratic filter can be varied from 0.58 GHz to 1.2 GHz, with the transmission zero correspondingly varied from 2.03 GHz to 3.33 GHz. Figure 12 shows the measured S21 of the fourth-order Elliptic LPF. The cut-off frequency ω0 and transmission zeroes ωZ1 and ωZ2 are listed in Table 1. The cut-off frequencies can be varied from 0.76 GHz to 1.23 GHz, while the first transmission zero can be varied from 2.03 to 3.33 GHz. The second transmission zero would remain at 4.6 GHz in all the operation modes.

LPF Measurement Result
The measured S 21 of the first biquadratic filter is shown in Figure 11. With the 2-bit programmable capacitor, the cut-off frequency of the first biquadratic filter can be varied from 0.58 GHz to 1.2 GHz, with the transmission zero correspondingly varied from 2.03 GHz to 3.33 GHz. Figure 12 shows the measured S 21 of the fourth-order Elliptic LPF. The cut-off frequency ω 0 and transmission zeroes ω Z1 and ω Z2 are listed in Table 1. The cut-off frequencies can be varied from 0.76 GHz to 1.23 GHz, while the first transmission zero can be varied from 2.03 to 3.33 GHz. The second transmission zero would remain at 4.6 GHz in all the operation modes.    Figure 13a shows the output spectrum of SSF-LPF for an input swing of 0.5 Vpeak-to-peak at 100 MHz, where the level of the fundamental tone is −10.49 dBm and that of the third order harmonic is −51.81 dBm. Considering the cable losses of 0.22 dB and 0.49 dB at 100 MHz and 300 MHz, respectively, the third-order rejection is −41.05 dBc. Figure 13b shows the output spectrum of SSF-LPF for an input swing of 0.5 Vpeak-to-peak at 500 MHz, where the level of the fundamental tone is −13.14 dBm and that of the third order harmonic is −42.12 dBm. Considering the cable losses of 0.62 dB and 1.15 dB at 500 MHz and 1.5 GHz, respectively, the third-order rejection is −28.45 dBc. Figure 13c shows the output spectrum of SSF-LPF for an input swing of 0.5 Vpeak-to-peak at 1 GHz, where the level of the fundamental tone is −18.59 dBm and that of the third order harmonic is −53.68 dBm. Considering the cable losses of 0.89 dB and 1.66 dB at 1 GHz and 3 GHz, respectively, the third-order rejection is −34.32 dBc. Notably, the measurement is performed in a single-ended fashion by probing only one of the pseudo differential outputs, so the second order harmonic can be seen during the measurement. Figure 14 shows the measurement result of 1-dB compression point at 100 MHz, where the input voltage is swept from −40 to −15 dBv. The measured input 1-dB compression point of the 4th Elliptic LPF is −16.5 dBv. Figure 15 shows the measurement result of IIP3 with the two-tone signals at 100 MHz and 110 MHz. The measured IIP3 is −1 dBv.    Figure 13a shows the output spectrum of SSF-LPF for an input swing of 0.5 Vpeak-to-peak at 100 MHz, where the level of the fundamental tone is −10.49 dBm and that of the third order harmonic is −51.81 dBm. Considering the cable losses of 0.22 dB and 0.49 dB at 100 MHz and 300 MHz, respectively, the third-order rejection is −41.05 dBc. Figure 13b shows the output spectrum of SSF-LPF for an input swing of 0.5 Vpeak-to-peak at 500 MHz, where the level of the fundamental tone is −13.14 dBm and that of the third order harmonic is −42.12 dBm. Considering the cable losses of 0.62 dB and 1.15 dB at 500 MHz and 1.5 GHz, respectively, the third-order rejection is −28.45 dBc. Figure 13c shows the output spectrum of SSF-LPF for an input swing of 0.5 Vpeak-to-peak at 1 GHz, where the level of the fundamental tone is −18.59 dBm and that of the third order harmonic is −53.68 dBm. Considering the cable losses of 0.89 dB and 1.66 dB at 1 GHz and 3 GHz, respectively, the third-order rejection is −34.32 dBc. Notably, the measurement is performed in a single-ended fashion by probing only one of the pseudo differential outputs, so the second order harmonic can be seen during the measurement. Figure 14 shows the measurement result of 1-dB compression point at 100 MHz, where the input voltage is swept from −40 to −15 dBv. The measured input 1-dB compression point of the 4th Elliptic LPF is −16.5 dBv. Figure 15 shows the measurement result of IIP3 with the two-tone signals at 100 MHz and 110 MHz. The measured IIP3 is −1 dBv.   Figure 13a shows the output spectrum of SSF-LPF for an input swing of 0.5 V peak-to-peak at 100 MHz, where the level of the fundamental tone is −10.49 dBm and that of the third order harmonic is −51.81 dBm. Considering the cable losses of 0.22 dB and 0.49 dB at 100 MHz and 300 MHz, respectively, the third-order rejection is −41.05 dBc. Figure 13b shows the output spectrum of SSF-LPF for an input swing of 0.5 V peak-to-peak at 500 MHz, where the level of the fundamental tone is −13.14 dBm and that of the third order harmonic is −42.12 dBm. Considering the cable losses of 0.62 dB and 1.15 dB at 500 MHz and 1.5 GHz, respectively, the third-order rejection is −28.45 dBc. Figure 13c shows the output spectrum of SSF-LPF for an input swing of 0.5 V peak-to-peak at 1 GHz, where the level of the fundamental tone is −18.59 dBm and that of the third order harmonic is −53.68 dBm. Considering the cable losses of 0.89 dB and 1.66 dB at 1 GHz and 3 GHz, respectively, the third-order rejection is −34.32 dBc. Notably, the measurement is performed in a single-ended fashion by probing only one of the pseudo differential outputs, so the second order harmonic can be seen during the measurement. Figure 14 shows the measurement result of 1-dB compression point at 100 MHz, where the input voltage is swept from −40 to −15 dBv. The measured input 1-dB compression point of the 4th Elliptic LPF is −16.5 dBv. Figure 15 shows the measurement result of IIP3 with the two-tone signals at 100 MHz and 110 MHz. The measured IIP3 is −1 dBv.

B. TX Analog Baseband
With the PGA operating in different gain modes, the S21 of the TX analog baseband are measured, as shown in Figure 16. The measured S21 is −16.26 dB in the highest gain mode and −39.67 dB in the lowest gain mode, which agrees well with the simulation results. According to the measurement results, the TX analog baseband exhibits the 3-dB bandwidth of 1.03 GHz in the highest gain mode and 1.05 GHz in the lowest gain mode. Figure 17a shows the measured S21 and gain step error. Figure  17b shows the measured S21 and gain error deviation. The achieved power gain range is from -39.67 dB to −16.26 dB, where the gain step error is −0.7 to +0.9 dB and the gain error deviation is −4.4 to +0.4 dB. The voltage gain range of −18.78-3.83 dB can be roughly estimated. The measured THD results versus the gain settings are shown in Figure 18, where the output signal level would be maintained at 200 mVpeak-to-peak during the measurement and the required input levels for different gain modes are calculated according to the measured gain. The measured THD is −10 dB in the lowest gain mode and −33.5 dB in the highest gain mode.

TX Analog Baseband
With the PGA operating in different gain modes, the S 21 of the TX analog baseband are measured, as shown in Figure 16. The measured S 21 is −16.26 dB in the highest gain mode and −39.67 dB in the lowest gain mode, which agrees well with the simulation results. According to the measurement results, the TX analog baseband exhibits the 3-dB bandwidth of 1.03 GHz in the highest gain mode and 1.05 GHz in the lowest gain mode. Figure 17a shows the measured S 21 and gain step error. Figure 17b shows the measured S 21 and gain error deviation. The achieved power gain range is from -39.67 dB to −16.26 dB, where the gain step error is −0.7 to +0.9 dB and the gain error deviation is −4.4 to +0.4 dB. The voltage gain range of −18.78-3.83 dB can be roughly estimated. The measured THD results versus the gain settings are shown in Figure 18, where the output signal level would be maintained at 200 mV peak-to-peak during the measurement and the required input levels for different gain modes are calculated according to the measured gain. The measured THD is −10 dB in the lowest gain mode and −33.5 dB in the highest gain mode.

B. TX Analog Baseband
With the PGA operating in different gain modes, the S21 of the TX analog baseband are measured, as shown in Figure 16. The measured S21 is −16.26 dB in the highest gain mode and −39.67 dB in the lowest gain mode, which agrees well with the simulation results. According to the measurement results, the TX analog baseband exhibits the 3-dB bandwidth of 1.03 GHz in the highest gain mode and 1.05 GHz in the lowest gain mode. Figure 17a shows the measured S21 and gain step error. Figure  17b shows the measured S21 and gain error deviation. The achieved power gain range is from -39.67 dB to −16.26 dB, where the gain step error is −0.7 to +0.9 dB and the gain error deviation is −4.4 to +0.4 dB. The voltage gain range of −18.78-3.83 dB can be roughly estimated. The measured THD results versus the gain settings are shown in Figure 18, where the output signal level would be maintained at 200 mVpeak-to-peak during the measurement and the required input levels for different gain modes are calculated according to the measured gain. The measured THD is −10 dB in the lowest gain mode and −33.5 dB in the highest gain mode.     Figure 19 shows the IIP3 measurement result of the analog baseband. During the measurement, the input voltage is swept from −32 dBv to −4 dBv and the two-tone inputs are at 100 and 110 MHz. The TX analog baseband achieves the IIP3 of −0.2 dBv when the PGA operates in the highest gain mode. Figure 20 shows the measured 1-dB compression point of the TX analog baseband. During the measurement, the input voltage is swept from −40 to 5 dBv and the frequency of the input signal is 100 MHz. The circuit achieves the 1-dB compression point of −10 dBv when its PGA operates in the highest gain mode. The noise figure (NF) measurement results of three chip samples are shown in Figure 21. Again, the PGA operates in the highest gain mode during the measurement. Over the frequency range from 10 MHz to 1.2 GHz, the noise figures of 30.4-40.6 dB, 24.4-32.5 dB, and 27.8-37.0 dB are observed from the three chip samples of the transmitter analog baseband. The performance of the TX analog baseband is listed and compared with those of previous reported analog baseband circuits in Table 2 [10][11][12]. The TX analog baseband in this work achieves the wide bandwidth of 1.03-1.05 GHz and its noise figure and linearity are comparable with those of previous works.   Figure 19 shows the IIP3 measurement result of the analog baseband. During the measurement, the input voltage is swept from −32 dBv to −4 dBv and the two-tone inputs are at 100 and 110 MHz. The TX analog baseband achieves the IIP3 of −0.2 dBv when the PGA operates in the highest gain mode. Figure 20 shows the measured 1-dB compression point of the TX analog baseband. During the measurement, the input voltage is swept from −40 to 5 dBv and the frequency of the input signal is 100 MHz. The circuit achieves the 1-dB compression point of −10 dBv when its PGA operates in the highest gain mode. The noise figure (NF) measurement results of three chip samples are shown in Figure 21. Again, the PGA operates in the highest gain mode during the measurement. Over the frequency range from 10 MHz to 1.2 GHz, the noise figures of 30.4-40.6 dB, 24.4-32.5 dB, and 27.8-37.0 dB are observed from the three chip samples of the transmitter analog baseband. The performance of the TX analog baseband is listed and compared with those of previous reported analog baseband circuits in Table 2 [10][11][12]. The TX analog baseband in this work achieves the wide bandwidth of 1.03-1.05 GHz and its noise figure and linearity are comparable with those of previous works.  Figure 19 shows the IIP3 measurement result of the analog baseband. During the measurement, the input voltage is swept from −32 dBv to −4 dBv and the two-tone inputs are at 100 and 110 MHz. The TX analog baseband achieves the IIP3 of −0.2 dBv when the PGA operates in the highest gain mode. Figure 20 shows the measured 1-dB compression point of the TX analog baseband. During the measurement, the input voltage is swept from −40 to 5 dBv and the frequency of the input signal is 100 MHz. The circuit achieves the 1-dB compression point of −10 dBv when its PGA operates in the highest gain mode. The noise figure (NF) measurement results of three chip samples are shown in Figure 21. Again, the PGA operates in the highest gain mode during the measurement. Over the frequency range from 10 MHz to 1.2 GHz, the noise figures of 30.4-40.6 dB, 24.4-32.5 dB, and 27.8-37.0 dB are observed from the three chip samples of the transmitter analog baseband. The performance of the TX analog baseband is listed and compared with those of previous reported analog baseband circuits in Table 2 [10][11][12]. The TX analog baseband in this work achieves the wide bandwidth of 1.03-1.05 GHz and its noise figure and linearity are comparable with those of previous works.