A 40 nW CMOS-Based Temperature Sensor with Calibration Free Inaccuracy within ±0.6 ∘C

In this study, a temperature equivalent voltage signal was obtained by subtracting output voltages received from two individual temperature sensors. These sensors work in the subthreshold region and generate the output voltage signals that are proportional and complementary to the temperature. Over the temperature range of −40 ∘C to +85 ∘C without using any calibration method, absolute temperature inaccuracy less than ±0.6 ∘C was attained from the measurement of five prototypes of the proposed temperature sensor. The implementation was done in a standard 0.18 μ m CMOS technology with a total area of 0.0018 mm 2. The total power consumption is 40 nW for a supply voltage of 1.2 V measured at room temperature.


Introduction
The growing regime of Internet of Things (IoT) requires devices with low-power and low-cost for the consumer electronics. A wireless sensor node (WSN) is first in the long line of devices since it is the backbone of any IoT-based application [1]. One of the demanding specifications in the design of wireless sensor node is ultra low-power consumption. This is necessary due to the presence of power-hungry transceiver module [2,3]. These sensor nodes are deployed in various applications such as medical, infrastructure and environmental monitoring, where the most common sensing modality is temperature.
In the literature, various low power temperature sensing modules that are either suitable or have been used in WSN are available. These temperature sensing modules sense the temperature either by using BJT (Bipolar Junction transistor)-based or by using MOSFET (Metal Oxide Semiconductor Field-effect transistor)-based circuit arrangements. The BJT-based temperature sensors are widely accepted due to their accurate temperature sensing ability that can be below ±1 • C [4][5][6][7]. For all MOSFET-based implementations, a temperature accuracy less than ±2 • has been achieved [8][9][10][11].
One of the common post-processing methods for either BJT-based or MOSFET-based temperature sensor designs is the calibration, which is required to assure that the measurements are accurate and within the specifications [12][13][14]. In the aforementioned literature, either the single-point or the two-point calibration method is used to adjust the attribute of the temperature sensor. In addition to these conventional calibration approaches, researchers have also proposed methods such as self-calibration [15,16] and/or auto-calibration [17][18][19], to further reduce the complexity of the post fabrication calibration process.
Since the temperature sensor is a highly demanding element, to reduce the production time as well as the maintenance cost, elimination of the calibration process would be advantageous. Especially in the case of practical implementations such as room, automobile or refrigeration temperature monitoring, moderate temperature accuracy in the range of ±1 • C is adequate for controlling and supervision [20]. Some of the solutions to design the calibration-free temperature sensors that are useful for these purposes have been proposed in [21,22].
This work proposes a temperature sensor topology that is an all-MOSFET-based implementation to save Si area, has V th -based temperature sensing for fast response time, consumes power in nano-watts, is free from calibration to save post-processing and has an acceptable temperature accuracy suitable for various general-purpose applications. The block diagram is presented in Figure 1 where a MOSFET-based temperature sensor module has been formed by using two complementary temperature sensors. These sensors generate the output voltage signals that are Proportional-To-Absolute-Temperature (PTAT) and Complementary-To-Absolute-Temperature (CTAT), respectively. These voltage signals are then measured externally and a net PTAT output voltage signal is obtained by subtracting the CTAT-voltage signal from the PTAT-voltage signal. The arrangement is capable of measuring the temperature accurately within the range of ±0.6 • C without using any calibration process. This accuracy has been achieved for the temperature range of −40 • C to +85 • C [23] where the on-chip thermal cores consume power of 40 nW when operating at the supply voltage of 1.2 V. This paper is organized in four sections. Section 2 introduces the design implementation of the proposed temperature sensor cores. Experimental results from the prototype temperature sensors fabricated using 0.18 µm standard CMOS process are presented in Section 3. The concluding remarks are presented in Section 4.

Design Implementaton
The circuit diagram of proposed temperature sensing module is shown in Figure 2 that consists of three sub-blocks, namely resistor-less beta multiplier circuit, CTAT sensor and PTAT sensor. The resistor-less beta multiplier circuit provides reference current to the PTAT and CTAT temperature sensor cores. These cores utilize this current to generate thermal equivalent voltage signals, which are proportional and complementary to the temperature, respectively. The brief description and the first order theoretical modeling of the sub-blocks are in the following subsections.

Resistor-Less Beta Multiplier Circuit
The classical resistor-less beta multiplier (RBM) circuit [24] has been selected to obtain the reference current for the temperature sensing core due to its implementation simplicity. In the circuit (see Figure 2), the NMOSFETs (N-type Metal Oxide Semiconductor Field Effect Transistor) M n1 and M n2 operate in the subthreshold region. The NMOSFET M n3 is deployed as a MOS resistor and the gate controlling voltage to keep it in strong inversion, deep-triode region has been obtained from diode-connected NMOSFET M n4 . Thus, the equations of a linear and the saturation currents flowing in NMOSFET M n3 and M n4 are: (1) where I re f is the reference current which is flowing equally in all the branches of the RBM circuit; µ n , C OX and V thn are the mobility parameter, the gate-oxide capacitance and the threshold voltage of the NMOSFET, respectively; V ds3 and V gs4 are, respectively, the drain-source and gate-source voltages of M n3 ; and V gs4 is the gate-source voltage of M n4 . Finally, S 3 and S 4 are the aspect ratio (W/L) of M n3 and M n4 , respectively. It can be observed in Figure 2 that V gs3 = V gs4 , hence solving Equations (1) and (2) results in: Applying Kirchoff's Voltage Law (KVL) in the voltage loop formed by M n1 , M n2 and M n3 results in: The NMOSFETs M n1 and M n2 are in subthreshold saturation region [25] therefore V gs1 and V gs2 can be derived as ,: where I DO is the saturation diode saturation current, η is the subthreshold slope-factor and V T is the thermal voltage. Using Equations (5) and (6) in Equation (4), and substituting the resultant into Equation (3) gives the expression of I re f as follows: It can be seen from Equation (7) that I re f is supply independent and its magnitude is a function of device geometries. The temperature behavior of I re f is a function of the temperature behavior of parameters µ, V T and η. Referring to the work published in [26], the mobility parameter µ decreases with increasing temperature while the thermal voltage V T and the subthreshold slope η, increases with increasing temperature [25,27]. Thus, it can be concluded that the dominance of the terms η and V T in (7) will will introduce the PTAT temperature dependence in it.
The post layout simulation results of the current reference circuit at typical corner obtained for the temperature ranging from −40 • C to +85 • C in the steps of 12.5 • C are shown in Figure 3 where the PTAT dependence of I re f can be seen though the plot is not exactly linear by nature but increases with increasing temperature. By applying the 2-point calibration at −40 • C and +85 • C, it can be estimated that the current exhibit the PTAT behavior with the temperature coefficient of 1885 ppm/ • C.

Temperature Sensing Core
The temperature sensing core is formed by the two temperature sensors which are labeled as CTAT sensor and PTAT sensor in Figure 2. As the name indicates, CTAT sensor generates a voltage that decreases with increasing temperature. On the contrary, PTAT sensor generates a voltage that increases with increasing temperature.
The CTAT sensor is formed by using NMOSFETs M na to M nd and PMOSFETs (P-type Metal Oxide Semiconductor Field Effect Transistor) M p4 and M p5 have been used to mirror reference current in the core. Similarly, the PTAT sensor is constructed by using PMOSFETs M pa to M pd , and uses M n5 and M n6 as the current mirror. It can be seen in Figure 2 that each sensor consists of two branches, where currents I 1 ,N I 1 (CTAT sensor) and I 2 ,KI 2 (PTAT sensor) have been utilized, respectively. The magnitude (I 1 and I 2 ) and their mirroring ratios (N, K) were determined by framing an optimization problem that was solved using the Matlab ® software where the difference of the output PTAT and CTAT voltages of the sensors will result into the minimum absolute temperature error, was selected as the optimization constraint. The data used in the analysis was the parametric circuit simulation results that were obtained with the Spectre © simulator in the Cadence environment ® .
Let us consider the CTAT sensor, in which NMOSFETs M na to M nd are set to operate in the subthreshold region. Applying KVL in the voltage loops formed by NMOSFETs M na to M nd results in: The equation for subthreshold drain-current (I sub ) is given by [25]: For the diode-connected transistor working in saturation region (V ds > 4V T or ≈100 mV), Equation (12) is rewritten as follows: In the circuit, M nd and M nb are diode-connected and the currents of N I 1 and I 1 , respectively, are flowing through them. Hence, using Equation (13) in Equation (11) results in: where, S nb , S nd are the aspect ratio of M nb and M nd , respectively. Subtracting Equation (9) from Equation (8) results in: As the operating supply voltage is 1.2 V, the drain-source voltage V dsc of the NMOSFET M nc is greater than 100 mV, thus it is working in the subthreshold-saturation region with a total current value of (N + 1)I 1 . Hence, using Equations (13) and (14) in Equation (15) results in: It can be observed from Equation (16) that the output voltage V N is a sum of two parts (Parts (a) and (b)), whose constituents have a well define thermal behavior. The threshold voltage, i.e., Part (a), will exhibit CTAT behavior [26]. The temperature behavior of Part (b) is governed by the combined thermal behavior of the thermal voltage V T (0.085 mV/ • C) [25], the subthreshold slope parameter η [27], the mobility factor µ [26] and I 1 which is mirrored from I re f (see Figure 2). The thermal behavior of Part (b) can be predicted from the schematic-level simulation results, as shown in Figure 4. Here, the thermal slope of V thn is −0.63 mV/ • C while the thermal slope of V N is −2.1 mV/ • C. This, high magnitude of negative thermal slope of V N is feasible only when Part (b) exhibit the CTAT temperature dependence. Overall, Equation (16) will exhibit CTAT behavior which can be verified from the schematic level simulation results shown in Figure 4.  Similarly, by following the aforementioned steps, the output voltage from the PTAT sensor can be derived as: In Equation (17), Term (a1) is the supply voltage, which is a constant and also independent of the temperature, while Terms (b1) and (c1) exhibit the CTAT behavior, as explained above. Thus, when the sum of the Terms (b1) and (c1) is subtracted from the constant term, it results in o the PTAT behavior. However, it causes the PTAT sensor to be highly supply dependent. The schematic level simulation results are shown in Figure 5 where the maximum deviation in output of the CTAT sensor is 4 mV for the change in supply voltage from 0.8 to 2 V. This deviation can further be reduced by changing the circuit design strategy, e.g. using folded cascode biasing. Thus, it is possible to comment that CTAT is supply independent (see Equation (16)) while the output of PTAT sensor is supply dependent (see Equation (17)). The proposed architectures are capable of working from 0.8 to 2 V. In the present implementation, the sensors are operating at supply voltage of 1.2 V, which is one of the system level specifications where the sensor has been deployed. The simulated absolute temperature inaccuracy results at different supply voltage values for both of the sensors are also shown (Figure 5c) where the calculated supply-sensitivity [28] at room temperature of CTAT and PTAT sensors are 0.48 • C/V and 0.15 • C/V, respectively. It should be noted that ideally magnitudes of the supply sensitivity parameter are equal for both sensors; this inequality in the magnitudes is due to the design consideration.

Differential Sensing
The different sensing is obtained by subtracting Equation (16) from Equation (17), and results in: It can be seen in Figure 2 that the currents I 1 and I 2 , which are flowing in the cores, have been derived from the reference current generator, where and i α and β are the scaling factors. Substituting Equation (7) into Equation (19) and then into Equation (18) results in:

Post Layout Simulation Results
The parameters present in Equation (20) can be divided into two parts: first, the technology dependent parameters, which are η, C OX , V thp , V thn , µ n , µ p , and, second, the circuit level design parameters, which are the aspect ratio of transistors and scaling factors. During the design development of the cores, the dataset corresponding to the temperature-dependent characteristics of V di f f for the temperature range of −40 • C to +85 • C in the steps of 12.5 • C were obtained by varying the circuit-level design parameters by using Spectre simulator in the Cadence environment. Later, Matlab ® was used offline to find those circuit-level parameters for which the difference between the thermal characteristics curve and the best fitted line was minimal..
Mathematically it can be represented as: where f (T) is the difference of the best-fit line V ideal corresponding to V di f f over the selected temperature range. It is important to note that these cores can be designed individually; however, in the proposed implementation, they were designed simultaneously to follow the convergence condition in Equation (21). The post layout Monte Carlo simulation results (500 runs) of the fabrication-ready circuit are shown in Figure 6. For these simulations, the technology spread and devices mismatch at the supply voltage of 1.2 V were considered. The presence of a large spread in the sensor output voltage plots is primarily due to the dominant threshold voltage V th (see Equations (16) and (17)) [29]. However, it can be seen in Figure 6b that, irrespective of wide process spread, the calculated temperature inaccuracy is within the limit of ±1 • C for around 98% of the total Monte Carlo runs of the proposed temperature sensor.

Measurement Results
The proposed temperature sensor was fabricated in a standard 0.18 µm CMOS technology and the implemented area including current reference circuit is 0.013 mm 2 (see Figure 7). The measurements were performed on five prototypes at the supply voltage of 1.2 V. The temperature chamber VTM7004 ® was used to perform the temperature characterization. The controlling program was implemented in the LabVIEW ® to perform thermal characterization in the range of −40 • C to +85 • C in the programmed temperature step of 12.5 • C. A calibrated precision Pt-100 thermometer (±0.015 • C) was placed close to the prototype to obtain the true ambient temperature. The detailed block diagram of the measurement setup is shown in Figure 8.   The differential output voltages measured from the five prototypes are shown in Figure 9. The performance of the output voltage signals was off-line evaluated by using MATLAB ® in terms of the absolute temperature error (TE), which is the difference between the temperature equivalent of the measured voltage data and the temperature obtained from the least square best fit line. This line was obtained from the measured data points using the MATLAB program. The measured absolute temperature error obtained for the five prototypes is shown in Figure 10. It can be seen from the plots that the absolute temperature error is within ±0.6 • C. The performance comparison of the proposed architecture with the state-of-the-art temperature sensors available in the literature is presented in Table 1. It can be observed in the table that temperature accuracy without any calibration offered by the proposed temperature sensing module is smaller than or comparable to most of the-state-of-art published literature.

Conclusions
This paper explains the temperature sensor arrangement formed by using two temperature sensors with complementary thermal characteristics. The temperature equivalent voltage is a difference of voltage generated by CTAT and PTAT sensor cores, respectively. As a result, it becomes possible to measure the temperature with inaccuracy of ±0.6 • C, without use of any existing calibration methods. The only limitation of this module is high supply voltage dependence because of the PTAT sensor core. However, this limitation can be overcome by using a voltage regulator but it will increase total power consumption. In the present case, the cores all together consume 40 nW of power from the supply voltage of 1.2 V. The low power consumption and ability to measure temperature within permissible limits without use of any calibration make the proposed temperature sensing module suitable for various temperature measuring applications that are controlled by IoT in the extended industrial temperature range.