A PVT-Robust Super-Regenerative Receiver with Background Frequency Calibration and Concurrent Quenching Waveform

A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center frequency deviations of the SR oscillator (SRO) without interrupting the input data stream. Additionally, a concurrent quenching waveform (CQW) technique is devised to improve the SRO sensitivity and its noise performance. The proposed SRO architecture is controlled by two separate biasing branches to extend the sensitivity accumulation (SA) phase and reduce its noise during the SR phase, compared to the conventional optimal quenching waveform (OQW). The proposed SR receiver is implemented at 2.46 GHz center frequency in 180 nm SMIC CMOS technology and achieves better sensitivity, power consumption, noise performance, and PVT immunity compared with existent SR receiver architectures.


Introduction
The low complexity and low power consumption characteristics make super-regenerative (SR) receivers, mainly composed of a LC-tank super regenerative oscillator (SRO), an envelope detector (ED), and a demodulator, a suitable alternative for short-range wireless communications. Unlike linear receivers which tend to be more robust to PVT variations [1,2], SR receivers are nonlinear and hence are inherently more prone to PVT variations. The in-band SRO gain is simultaneously affected by the frequency deviations between the carrier frequency of the input OOK signal and SRO's center frequency and the design of its quenching waveform as shown in Figure 1a. Any deviation in the center frequency or the shape of its quenching waveform will result in selectivity and sensitivity degradations. To achieve high performance under low power consumption, a frequency calibration circuit is required to adjust the SRO center frequency and an optimal quenching waveform (OQW) [3] is needed to optimize the SRO performance.
Recently, several frequency calibration techniques have been proposed for SR receivers using a phase-locked-loop (PLL) [4,5] or a counter-based frequency-locked-loop (FLL) [6] as shown in Figure 1b. Although these techniques can calibrate the SRO to the expected center frequency, they have to interrupt receiving of the input OOK data stream. For example, the frequency calibration loop in Reference [4] uses a charge-pump based PLL to compensate for the frequency deviations of the SRO at start-up; however, it is not able to continuously track the frequency deviation under PVT variations.
During normal operation while receiving the input data, any frequency deviation with respects to the SRO nominal center frequency f SRO will cause degradation of the SRO performance (as illustrated in Figure 1a). Due to the initial phase error between the reference clock and SRO's feedback clock at the start of each calibration cycle, the conventional PLL or FLL-based methods need a considerable time exceeding the quenching cycle to overcome this initial phase error and that causes error in the frequency calibration (refer to Section 2.1.1). As a result, it is not feasible to use the conventional techniques to calibrate the SRO frequency in background (refer to Figure 2). In contrast, a novel initial phase error reduction is proposed in this paper to shorten the frequency detection time to less than the quenching cycle. That offers the proposed calibration the capability to continuously adjust the SRO center frequency in every quenching cycle to compensate for the SRO selectivity deviation during normal operation. the SRO at start-up; however, it is not able to continuously track the frequency deviation under PVT variations. During normal operation while receiving the input data, any frequency deviation with respects to the SRO nominal center frequency will cause degradation of the SRO performance (as illustrated in Figure 1a). Due to the initial phase error between the reference clock and SRO's feedback clock at the start of each calibration cycle, the conventional PLL or FLL-based methods need a considerable time exceeding the quenching cycle to overcome this initial phase error and that causes error in the frequency calibration (refer to Section 2.1.1). As a result, it is not feasible to use the conventional techniques to calibrate the SRO frequency in background (refer to Figure 2). In contrast, a novel initial phase error reduction is proposed in this paper to shorten the frequency detection time to less than the quenching cycle. That offers the proposed calibration the capability to continuously adjust the SRO center frequency in every quenching cycle to compensate for the SRO selectivity deviation during normal operation.  The sensitivity of the SR receiver is determined mainly by its quenching signal design. An optimal quenching waveform (OQW), shown in Figure 1b, was proposed in Reference [1] to optimize the sensitivity of the SRO. This quenching signal places the SRO into two regions, namely the sensitivity accumulation (SA) region and the super-regenerative (SR) region. In this paper, a concurrent quenching waveform (CQW) technique is presented to extend the SA region over the entire quenching period to allow maximum sensitivity accumulation and alleviate the requirement on the slope shape of the OQW under PVT variations. In addition, the proposed CQW reduces the SRO noise substantially and improves its signal-to-noise ratio (SNR) during the SR region.  the SRO at start-up; however, it is not able to continuously track the frequency deviation under PVT variations. During normal operation while receiving the input data, any frequency deviation with respects to the SRO nominal center frequency will cause degradation of the SRO performance (as illustrated in Figure 1a). Due to the initial phase error between the reference clock and SRO's feedback clock at the start of each calibration cycle, the conventional PLL or FLL-based methods need a considerable time exceeding the quenching cycle to overcome this initial phase error and that causes error in the frequency calibration (refer to Section 2.1.1). As a result, it is not feasible to use the conventional techniques to calibrate the SRO frequency in background (refer to Figure 2). In contrast, a novel initial phase error reduction is proposed in this paper to shorten the frequency detection time to less than the quenching cycle. That offers the proposed calibration the capability to continuously adjust the SRO center frequency in every quenching cycle to compensate for the SRO selectivity deviation during normal operation.  The sensitivity of the SR receiver is determined mainly by its quenching signal design. An optimal quenching waveform (OQW), shown in Figure 1b, was proposed in Reference [1] to optimize the sensitivity of the SRO. This quenching signal places the SRO into two regions, namely the sensitivity accumulation (SA) region and the super-regenerative (SR) region. In this paper, a concurrent quenching waveform (CQW) technique is presented to extend the SA region over the entire quenching period to allow maximum sensitivity accumulation and alleviate the requirement on the slope shape of the OQW under PVT variations. In addition, the proposed CQW reduces the SRO noise substantially and improves its signal-to-noise ratio (SNR) during the SR region. The sensitivity of the SR receiver is determined mainly by its quenching signal design. An optimal quenching waveform (OQW), shown in Figure 1b, was proposed in Reference [1] to optimize the sensitivity of the SRO. This quenching signal places the SRO into two regions, namely the sensitivity accumulation (SA) region and the super-regenerative (SR) region. In this paper, a concurrent quenching waveform (CQW) technique is presented to extend the SA region over the entire quenching period to allow maximum sensitivity accumulation and alleviate the requirement on the slope shape of the OQW under PVT variations. In addition, the proposed CQW reduces the SRO noise substantially and improves its signal-to-noise ratio (SNR) during the SR region.
This paper is organized as follows: Section 2 firstly presents the SRO theoretical background analysis and important design parameters, and then introduces the proposed background frequency calibration and concurrent quenching waveform techniques. Section 3 includes the simulation results. Section 4 concludes this paper.

PLL with Random Initial Phase Error
To improve the SR receiver selectivity, compensation of its center deviation is required. There are several methods currently used to calibrate the oscillating frequency of the SRO using PLL [4,5] and FLL [6]. However, all of them are infeasible to conduct background frequency calibration as the reason described below. Figure 3a illustrates the schematic of the SR receiver with a conventional PLL-based frequency calibration. In contrast with the continuous operation of a normal PLL used for clock synchronization, a PLL used for SRO oscillating frequency calibration operates in intermittent mode. when the input enable signal EN is high, PLL is activated to detect the phase error between the reference clock CLK ref and the feedback clock CLK fb , and converts this phase error into the pulse width on the outputs UP and DW of the phase-frequency detector (PFD), and accordingly drive the charge pump to adjust the varactors' tuning voltage V tune to tune the oscillating frequency of SRO f SRO to be the desired one. When EN is low, the PLL must freeze its operation. Since CLK ref and CLK fb are unsynchronized when EN turns active, there exists a random phase error between CLK ref and CLK fb as shown in Figure 3b.
The phase difference between CLK ref and CLK fb can be expressed as follows: where f re f and f f b are the frequencies corresponding to CLK ref and CLK fb the reference clock and the PLL loop's feedback clock respectively, ∆ϕ i is the initial phase error between these two clocks at the start of the detection, and t PD is the detecting time. As shown in Figure 3b, although the period of the reference clock T ref is smaller than the feedback clock's period T fb , ∆ϕ i will result in incorrect values at the PFD's output signals on UP and DW, which causes increasing T fb by PLL instead of decreasing it. That will increase substantially the PLL's settling time (as indicated by the settling time of V tune in Figure 3c), therefore, it is hard for the conventional PLL-based calibration to adapt SRO's intermittent operation because the quenching cycle is too short for PLL to acquire correct phase error detection. As a consequence, the SR receiver has to interrupt its receiving process and keep SRO oscillating continuously till the finish of frequency calibration. This paper is organized as follows: Section 2 firstly presents the SRO theoretical background analysis and important design parameters, and then introduces the proposed background frequency calibration and concurrent quenching waveform techniques. Section 3 includes the simulation results. Section 4 concludes this paper.

PLL with Random Initial Phase Error
To improve the SR receiver selectivity, compensation of its center deviation is required. There are several methods currently used to calibrate the oscillating frequency of the SRO using PLL [4,5] and FLL [6]. However, all of them are infeasible to conduct background frequency calibration as the reason described below. Figure 3a illustrates the schematic of the SR receiver with a conventional PLL-based frequency calibration. In contrast with the continuous operation of a normal PLL used for clock synchronization, a PLL used for SRO oscillating frequency calibration operates in intermittent mode. when the input enable signal EN is high, PLL is activated to detect the phase error between the reference clock CLK and the feedback clock CLK , and converts this phase error into the pulse width on the outputs UP and DW of the phase-frequency detector (PFD), and accordingly drive the charge pump to adjust the varactors' tuning voltage V to tune the oscillating frequency of SRO to be the desired one. When EN is low, the PLL must freeze its operation. Since CLK and CLK are unsynchronized when EN turns active, there exists a random phase error between CLK and CLK as shown in Figure 3b.
The phase difference between CLK and CLK can be expressed as follows: where and are the frequencies corresponding to CLK and CLK the reference clock and the PLL loopʹs feedback clock respectively, ∆ is the initial phase error between these two clocks at the start of the detection, and is the detecting time. As shown in Figure 3b, although the period of the reference clock T is smaller than the feedback clockʹs period T , ∆φ will result in incorrect values at the PFD's output signals on UP and DW, which causes increasing T by PLL instead of decreasing it. That will increase substantially the PLL's settling time (as indicated by the settling time of V in Figure 3c), therefore, it is hard for the conventional PLL-based calibration to adapt SRO's intermittent operation because the quenching cycle is too short for PLL to acquire correct phase error detection. As a consequence, the SR receiver has to interrupt its receiving process and keep SRO oscillating continuously till the finish of frequency calibration.

Quenching Signal Analysis under PVT Variations
To optimize the sensitivity of the SRO, an optimal quenching waveform (OQW) is proposed in Reference [1] as shown in Figure 4. The OQW offers clearly better performance compares with conventional quenching waveforms such as square wave, sawtooth, and sinusoidal quenching. The OQW signal places the SRO into 2 regions, the sensitivity accumulation (SA) region and the super-regenerative (SR) region, to optimize the SRO sensitivity ( Figure 5).

Quenching Signal Analysis under PVT Variations
To optimize the sensitivity of the SRO, an optimal quenching waveform (OQW) is proposed in Reference [1] as shown in Figure 4. The OQW offers clearly better performance compares with conventional quenching waveforms such as square wave, sawtooth, and sinusoidal quenching. The OQW signal places the SRO into 2 regions, the sensitivity accumulation (SA) region and the super-regenerative (SR) region, to optimize the SRO sensitivity ( Figure 5).

Quenching Signal Analysis under PVT Variations
To optimize the sensitivity of the SRO, an optimal quenching waveform (OQW) is proposed in Reference [1] as shown in Figure 4. The OQW offers clearly better performance compares with conventional quenching waveforms such as square wave, sawtooth, and sinusoidal quenching. The OQW signal places the SRO into 2 regions, the sensitivity accumulation (SA) region and the super-regenerative (SR) region, to optimize the SRO sensitivity ( Figure 5).   According to Reference [1], the expression of the SRO voltage output can be written as: where k ,δ , ω represents the passive gain, quiescent damping factor, center frequency of the SRO respectively. δ t is the dynamic damping factor for the entire system and I t is the first derivative of the input current. The dynamic damping factor is given: where G represents the SRO static loss, G t is the transient value of the negative transconductance. C is the total capacitance of the LC-tank and G t G G t represents the instantaneous transconductance due to the quenching controller. The sensitivity and SR gain functions extracted from Equation (2) are: As it is shown in the timing diagram of the OQW based SRO in Figure 5, the sensitivity reaches its maximum value when the SRO biasing current is equal to a critical current I (equivalently when the instantaneous transconductance G t 0). However, once the oscillation starts to build up in the SR region, the SRO will not respond to the input signal because the sensitivity rapidly decays afterwards in the SR region (refer to Figure 5). Since the maximum sensitivity of the SRO is achieved only when the OQW crosses in the middle of SA region, any change in the OQW's slope due to PVT variations in the SA region will cause sensitivity degradation as shown in Figure 6. At the end of the SA region, the OQW is stepped up to a maximum value _ to place the SRO in the SR region and regenerate the output signal. In the SR region, the SRO regenerative gain is dramatically reduced because the sensitivity decays to 0 (refer to Figure 6b), therefore, the input referred noise will dramatically increase which will degrade the SNR. According to Reference [1], the expression of the SRO voltage output can be written as: where k 0 , δ 0 , ω 0 represents the passive gain, quiescent damping factor, center frequency of the SRO respectively. δ(t) is the dynamic damping factor for the entire system and I in (t) is the first derivative of the input current. The dynamic damping factor is given: where G 0 represents the SRO static loss, −G m (t) is the transient value of the negative transconductance. C is the total capacitance of the LC-tank and G i (t) = G 0 − G m (t) represents the instantaneous transconductance due to the quenching controller. The sensitivity and SR gain functions extracted from Equation (2) are: Sensitivity : As it is shown in the timing diagram of the OQW based SRO in Figure 5, the sensitivity reaches its maximum value when the SRO biasing current is equal to a critical current I critical (equivalently when the instantaneous transconductance G i (t) = 0). However, once the oscillation starts to build up in the SR region, the SRO will not respond to the input signal because the sensitivity rapidly decays afterwards in the SR region (refer to Figure 5). Since the maximum sensitivity of the SRO is achieved only when the OQW crosses I critical in the middle of SA region, any change in the OQW's slope due to PVT variations in the SA region will cause sensitivity degradation as shown in Figure 6. At the end of the SA region, the OQW is stepped up to a maximum value V re f _high to place the SRO in the SR region and regenerate the output signal. In the SR region, the SRO regenerative gain is dramatically reduced because the sensitivity decays to 0 (refer to Figure 6b), therefore, the input referred noise will dramatically increase which will degrade the SNR.

Proposed SR Receiver with Background Frequency Calibration and Concurrent Quenching Waveform
The block diagram of the proposed SR receiver is illustrated in Figure 7. This receiver consists of an SRO quenched by the proposed CQW and a PLL with the initial phase error reduction, built around the SRO for frequency calibration. Beside the components illustrated in Figure 3a, the proposed PLL includes an initial phase error reducing circuit (IPERC), a comparator (COM) used to trigger frequency calibration periodically, a divider (CT1) employed to generate a synchronized reference clock Clk from the input clock Clk , and an analog OTA-based buffer to drive the varactors and hold the charge on the capacitor C . Unlike the above mentioned PLL or FLL techniques in References [4,6] that interrupt the receiving phase to perform frequency calibration, the proposed PLL can perform frequency calibration without disturbing the data receiving. When the envelope detector output V goes high, exceeding a preset threshold voltage V , the output EN of comparator COM in PLL turns high accordingly to enable PLL to detect the frequency difference between the SRO output frequency and the desired one, and tune the SRO center frequency via the voltage V . Meanwhile, the proposed CQW technique is applied to the SRO to achieve noise reduction and sensitivity enhancement robust to PVT variations.

SR Receiver Architecture Overview
The block diagram of the proposed SR receiver is illustrated in Figure 7. This receiver consists of an SRO quenched by the proposed CQW and a PLL with the initial phase error reduction, built around the SRO for frequency calibration. Beside the components illustrated in Figure 3a, the proposed PLL includes an initial phase error reducing circuit (IPERC), a comparator (COM) used to trigger frequency calibration periodically, a divider (CT1) employed to generate a synchronized reference clock Clk ref from the input clock Clk in , and an analog OTA-based buffer to drive the varactors and hold the charge on the capacitor C 1 . Unlike the above mentioned PLL or FLL techniques in References [4,6] that interrupt the receiving phase to perform frequency calibration, the proposed PLL can perform frequency calibration without disturbing the data receiving. When the envelope detector output V ED goes high, exceeding a preset threshold voltage V TH , the output EN of comparator COM in PLL turns high accordingly to enable PLL to detect the frequency difference between the SRO output frequency and the desired one, and tune the SRO center frequency via the voltage V tune . Meanwhile, the proposed CQW technique is applied to the SRO to achieve noise reduction and sensitivity enhancement robust to PVT variations.

Proposed SR Receiver with Background Frequency Calibration and Concurrent Quenching Waveform
The block diagram of the proposed SR receiver is illustrated in Figure 7. This receiver consists of an SRO quenched by the proposed CQW and a PLL with the initial phase error reduction, built around the SRO for frequency calibration. Beside the components illustrated in Figure 3a, the proposed PLL includes an initial phase error reducing circuit (IPERC), a comparator (COM) used to trigger frequency calibration periodically, a divider (CT1) employed to generate a synchronized reference clock Clk from the input clock Clk , and an analog OTA-based buffer to drive the varactors and hold the charge on the capacitor C . Unlike the above mentioned PLL or FLL techniques in References [4,6] that interrupt the receiving phase to perform frequency calibration, the proposed PLL can perform frequency calibration without disturbing the data receiving. When the envelope detector output V goes high, exceeding a preset threshold voltage V , the output EN of comparator COM in PLL turns high accordingly to enable PLL to detect the frequency difference between the SRO output frequency and the desired one, and tune the SRO center frequency via the voltage V . Meanwhile, the proposed CQW technique is applied to the SRO to achieve noise reduction and sensitivity enhancement robust to PVT variations.

Fast Frequency Calibration Using PLL with Initial Phase Reduction
As shown in Figure 7, the proposed PLL is composed mainly of a phase detector, a high-speed analog divider (÷2) combined with a pulse-swallow counter (CT2) for RF signal frequency division, a counter (CT1) for the reference clock generation, an initial phase error reduction circuit (IPERC), and a comparator (COM). IPERC is used to eliminate the initial phase error ∆ϕ i between the reference clock (Clk ref ) and the feedback clock (Clk fb ) stemming from SRO's output. After initial phase error reduction, the actual phase error between Clk ref and Clk fb is detected by the phase detector and converted into the pulse width on the phase detector's output UP and DW. Then, UP and DW drive the charge pump to charge or discharge the capacitor C 1 to adjust its voltage V tune . Finally, the voltage on C 1 is buffered and fed to the varactors to tune SRO's oscillating frequency.
The required frequency calibration time per quenching cycle for the proposed intermittent frequency calibration technique is much shorter than conventional techniques mentioned in Reference [1,2,4] owing to the initial phase error reduction. Equation (6) shows the design parameters which will influence the calibration time. The phase detector output ϕ n represents the frequency detecting accuracy and can be derived as: where ∆ϕ i,n is the initial phase error occurring in the nth cycle, (T n − T n−1 ) represents the phase detecting time, N = 2 * N PSC is the overall division ratio including the ratio of the analog divider (÷2) and N PSC from CT2 respectively; f re f and f f b are the frequency of Clk ref and Clk fb respectively, and Clk ref is the result of dividing Clk in by N CT1 the division ratio of CT1. f re f − f SRO /N is defined as the calibration resolution which represents the difference between the desired SRO oscillating frequency and the current SRO oscillating frequency. As indicated, the ultimate phase error ϕ n includes the unpredictable ∆ϕ i,n and the actual phase error between ClK ref and ClK fb . Compared with the conventional counterparts in the sate-of-art design, IPERC is the essential of the proposed PLL. Figure 8 shows the schematic of the IPER and its signal propagation delay diagram, while Figure 9a illustrates its timing diagram. As shown in Figure 7, the proposed PLL is composed mainly of a phase detector, a high-speed analog divider (2) combined with a pulse-swallow counter (CT2) for RF signal frequency division, a counter (CT1) for the reference clock generation, an initial phase error reduction circuit (IPERC), and a comparator (COM). IPERC is used to eliminate the initial phase error ∆φ between the reference clock (Clk ) and the feedback clock (Clk ) stemming from SRO's output. After initial phase error reduction, the actual phase error between Clk and Clk is detected by the phase detector and converted into the pulse width on the phase detector's output UP and DW. Then, UP and DW drive the charge pump to charge or discharge the capacitor C to adjust its voltage V . Finally, the voltage on C is buffered and fed to the varactors to tune SRO's oscillating frequency.
The required frequency calibration time per quenching cycle for the proposed intermittent frequency calibration technique is much shorter than conventional techniques mentioned in Reference [1][2]4] owing to the initial phase error reduction. Equation (6) shows the design parameters which will influence the calibration time. The phase detector output φ represents the frequency detecting accuracy and can be derived as: where ∆ , is the initial phase error occurring in the nth cycle, represents the phase detecting time, 2 * is the overall division ratio including the ratio of the analog divider (2) and from CT2 respectively; and are the frequency of Clk and Clk respectively, and Clk is the result of dividing Clk by the division ratio of CT1. ⁄ is defined as the calibration resolution which represents the difference between the desired SRO oscillating frequency and the current SRO oscillating frequency. As indicated, the ultimate phase error includes the unpredictable ∆ , and the actual phase error between ClK and ClK . Compared with the conventional counterparts in the sate-of-art design, IPERC is the essential of the proposed PLL. Figure 8 shows the schematic of the IPER and its signal propagation delay diagram, while Figure 9a illustrates its timing diagram. In conjunction with those figures, the working principle of IPERC is explained as follows. This circuit includes two identical DFF-type latches, U1 and U2, with a set (S) and a reset (R) inputs. The latch U1 along with a buffer chain (U3), a delay cell (U4), two AND2 gats and two inverters are used to generate Clk _ which is a delayed version of the input Clk . The input EN is delayed by through the delay cell U5 to generate the signal EN1 which is sampled in U2 by Clk to generate the output EN2 . As shown in Figure 8b, the rising edges of Clk _ will lag behind the corresponding rising edges of Clk by a delay of calculated by: , , , In conjunction with those figures, the working principle of IPERC is explained as follows. This circuit includes two identical DFF-type latches, U1 and U2, with a set (S) and a reset (R) inputs. The latch U1 along with a buffer chain (U3), a delay cell (U4), two AND2 gats and two inverters are used to generate Clk in_delay which is a delayed version of the input Clk in . The input EN is delayed by t d1 through the delay cell U5 to generate the signal EN1 which is sampled in U2 by Clk in to generate the output EN2. As shown in Figure 8b, the rising edges of Clk in_delay will lag behind the corresponding rising edges of Clk in by a delay of t d2 calculated by: where t d,G is the AND gate's propagation delay, t d,B is the buffer chain's delay, and t d,D1 is the latch's propagation delay from its input S to its output Q. Simultaneously, the rising edge of EN2 will lag behind the rising edges of Clk in by a delay of t d,D2 , the latch U2's propagation delay from its clock input CK to its output Q. The delay of t d1 on EN2 is aimed at preventing the division ratio N from the instability of the analog divider during the initial start-up phase as shown in Figure 9a. To avoid the degradation of detecting accuracy caused by the instability, the value of t d1 must be set greater than the settling time of the analog divider. The duration of the instability varies with PVT variation, and its worst-case scenario is about 5 ns in the proposed design, hence t d1 is set to 10 ns in this design. where , is the AND gate's propagation delay, , is the buffer chain's delay, and , is the latch's propagation delay from its input S to its output Q. Simultaneously, the rising edge of EN2 will lag behind the rising edges of Clk by a delay of , , the latch U2's propagation delay from its clock input CK to its output Q. The delay of on EN2 is aimed at preventing the division ratio from the instability of the analog divider during the initial start-up phase as shown in Figure 9a. To avoid the degradation of detecting accuracy caused by the instability, the value of must be set greater than the settling time of the analog divider. The duration of the instability varies with PVT variation, and its worst-case scenario is about 5 ns in the proposed design, hence is set to 10 ns in this design. As shown in Figure 7, EN2 is used to enable the dividers CT1 and CT2 at the same time to synchronize the generation of ClK and ClK , and consequently eliminate their initial phase error ∆ . According to Equation (7), the rising edge of EN2 will always lead the rising edge of Clk _ by a value of , . That prevents CT1 from missing the first rising edge of Clk _ when EN2 turns high. Since , approximately equals , , , can be set by the buffer chain U3 to provide synchronization between ClK with ClK . As a result, ∆ can be reduced from tens nanoseconds to less than 1 ns despite PVT variations. Figure 9b presents the timing diagram of the main signals in the proposed PLL. The PLL operates on cycle by cycle basis by detecting the frequency error betweenClk and Clk , and adjusting the tuning voltage V and consequently the oscillating frequency of SRO in each cycle. As shown in Figure 7, EN2 is used to enable the dividers CT1 and CT2 at the same time to synchronize the generation of ClK ref and ClK fb , and consequently eliminate their initial phase error ∆ϕ i . According to Equation (7), the rising edge of EN2 will always lead the rising edge of Clk in_delay by a value of (t d2 − t d,D2 ). That prevents CT1 from missing the first rising edge of Clk in_delay when EN2 turns high. Since t d,D1 approximately equals t d,D2 , (t d2 − t d,D2 ) can be set by the buffer chain U3 to provide synchronization between ClK ref with ClK fb . As a result, ∆ϕ i can be reduced from tens nanoseconds to less than 1 ns despite PVT variations. Figure 9b presents the timing diagram of the main signals in the proposed PLL. The PLL operates on cycle by cycle basis by detecting the frequency error between Clk ref and Clk fb , and adjusting the tuning voltage V tune and consequently the oscillating frequency of SRO in each cycle. To systematically analyze its performance, the following hypotheses are considered: (1) the PLL operated in a quasi-periodic steady state mode; (2) The transient charging or discharging behavior of the charge pump is neglected. After calibration, the negative pulse width T f b of Clk fb approximately equals T re f , the counterpart of Clk ref ; while the tuning voltage V tune will approach the desired level V t . Therefore, the following equations can be found: where ∆ϕ i (n) is the initial phase error in the cycle n, ∆τ UP,DW (n) is the pulse width of PFD's outputs; I CP is the current of the charge pump; C 1 is the capacitance of C1; and k is the voltage-to-frequency gain of SRO (assumed to have a negative value), f SRO is the oscillating frequency of SRO while f o is its initial value. Those equations can be combined as: It is notable that ( f o − kV t ) equals the target frequency f TF which is expected to be N/T re f . Additionally, ∆V tune (n)∆T fb (n) is sufficiently small compared to other terms in Equation (9), and can be neglected. The Equation (9) can be rewritten as: Substituting Equation (10) into Equation (8) yields: By applying Z-domain analysis to Equation (11), the transfer function of the PLL can be written as: As implied by Equation (12), the necessary and sufficient condition for the stability of the proposed PLL is: The step response of the system can be written as: From the above equation, it can be observed that a larger β can lead to a faster system's convergence but results in a larger ripple on ∆T f b . In this design, β is set to 0.27 to guarantee accurate frequency calibration as it is discussed in Section 3.

SRO with Concurrent Quenching Waveform
The proposed SRO architecture and its timing diagram are shown in Figures 10 and 11 respectively. In contrast to conventional SRO architectures, the SA and SR regions in the proposed one are separately controlled by M5 and M6 which perform the proposed CQW operation. M5 is controlled by V 1 and is on for the entire quenching period (case when V 1 = V 1a in Figure 11). M6 is controlled by V 2 and is on only during the SR region. When M5 is on, the SRO is always operating in the vicinity of I critical and accumulates sensitivity during the entire quenching phase. When M6 is on, the SRO performs super-regeneration and sensitivity accumulation simultaneously, while the conventional SRO architecture with OQW loses sensitivity accumulation during SR region. When the transistors M5-6 are both on, the SRO is in SR region and concurrently regenerates the SRO output and samples the input signal for the entire quenching cycle. in the vicinity of I and accumulates sensitivity during the entire quenching phase. When M6 is on, the SRO performs super-regeneration and sensitivity accumulation simultaneously, while the conventional SRO architecture with OQW loses sensitivity accumulation during SR region. When the transistors M5-6 are both on, the SRO is in SR region and concurrently regenerates the SRO output and samples the input signal for the entire quenching cycle.  Splitting the quenching signal into V and V allows optimizing the noise performance in addition to improving the accumulated sensitivity compared to OQW as will be explained later. Figure 12c shows the SRO output noise with different V waveforms, V and V , along with OQW scheme. For V V , M5 is on for the entire quenching period to improve sensitivity and noise compared to OQW. For V V M5 is turned off to improve more the noise performance compared to the case of V V while achieving same sensitivity as OQW. in the vicinity of I and accumulates sensitivity during the entire quenching phase. When M6 is on, the SRO performs super-regeneration and sensitivity accumulation simultaneously, while the conventional SRO architecture with OQW loses sensitivity accumulation during SR region. When the transistors M5-6 are both on, the SRO is in SR region and concurrently regenerates the SRO output and samples the input signal for the entire quenching cycle.  Splitting the quenching signal into V and V allows optimizing the noise performance in addition to improving the accumulated sensitivity compared to OQW as will be explained later. Figure 12c shows the SRO output noise with different V waveforms, V and V , along with OQW scheme. For V V , M5 is on for the entire quenching period to improve sensitivity and noise compared to OQW. For V V M5 is turned off to improve more the noise performance compared to the case of V V while achieving same sensitivity as OQW.
To understand how to optimize the noise of the SRO it is instructive to compare the noise Figure 11. Comparison between the conventional OQW and the proposed CQW techniques.
Splitting the quenching signal into V 1 and V 2 allows optimizing the noise performance in addition to improving the accumulated sensitivity compared to OQW as will be explained later. Figure 12c shows the SRO output noise with different V 1 waveforms, V 1a and V 1b , along with OQW scheme. For V 1 = V 1a , M5 is on for the entire quenching period to improve sensitivity and noise compared to OQW. For V 1 = V 1b M5 is turned off to improve more the noise performance compared to the case of V 1 = V 1a while achieving same sensitivity as OQW.
To understand how to optimize the noise of the SRO it is instructive to compare the noise performance of an OTA and an SRO as shown in Figure 12a,b. The small signal model of an OTA and SRO are different by the type of load. Additionally, the OTA is biasing using constant current while an SRO is biased using its customized quenching waveform. The output referred noise of an OTA can be analyzed as follows: where V 2 n,in and V 2 n,out are the input and output referred noise respectively. Gain of an OTA, A v simply equals G m R out . Since the biasing current is a constant value which means that the G m maintains a constant value. In conventional linear receivers with OTA placed as the front-end signal detector, increasing the biasing current will cause input referred noise to decrease because the current thermal noise of an MOS transistor is proportional to G m while the input referred noise is inversely proportional to A 2 v . while an SRO is biased using its customized quenching waveform. The output referred noise of an OTA can be analyzed as follows: , , where V , and V , are the input and output referred noise respectively. Gain of an OTA, A simply equals G R . Since the biasing current is a constant value which means that the G maintains a constant value. In conventional linear receivers with OTA placed as the front-end signal detector, increasing the biasing current will cause input referred noise to decrease because the current thermal noise of an MOS transistor is proportional to G while the input referred noise is inversely proportional to A . Similarly, the input referred noise of the SRO can be intuitively analyzed also by starting from the SRO gain A [7,8] as the following: where k is the SRO regenerative gain and u t is the SR gain as given in Equation (5). Similarly, the input referred noise of the SRO can be intuitively analyzed also by starting from the SRO gain A v [7,8] as the following: where k r is the SRO regenerative gain and u(t) is the SR gain as given in Equation (5).
The gain A 2 v can also be written as the following: where ∆f ENB is the the equivalent noise bandwidth (ENB) of the SRO frequency response. G meff and G 0 refer to the effective transconductance of M3-4 in Figure 10 and static loss of the SRO. For practical design purposes, in Equations (16)-(19) the SRO regenerative gain k r is much greater than the SR gain u(t) for the SRO to achieve good sensitivity. The noise bandwidth in Equation (18) is determined by the selectivity of the SRO. As we can notice, the major difference for the noise analysis between conventional OTA-based receivers and SR receiver is that the gain A v of an SRO is consists of 3 different components, namely static loss, regenerative gain, and super-regenerative gain corresponding to k 0 , k r , u(t) respectively. For the proposed CQW scheme applied as quenching signal for the SRO under V 1a , the sensitivity region has been extended over the entire quenching cycle and the SRO is always responding to the input OOK signal for both SA and SR regions. Therefore, the major contribution of the SRO gain k r is not degrading through the entire quenching cycle and hence reducing the input referred noise and improving the SNR. In contrast, for the SRO under OQW quenching, the SR region is only responsible for generating the oscillation envelope, in response to the SA region, while k r is dramatically reduced because the sensitivity decays to 0 (refer to Figure 11). Therefore, the input referred noise will dramatically increase and hence degrade the SNR. It is straightforward to find that the SRO frequency response has narrower noise bandwidth for the proposed CQW technique compared with the conventional OQW quenching because the proposed CQW technique extends the sensitivity for the SRO in time domain and therefore, it automatically reduces the ∆f ENB to reduce the noise.
The dominant noise source of the SRO circuits is stemmed from the input transistors (M3-4 in Figure 10); when V 1 = V 1b the transistors M3-M4 are turned off in SO region to reduce the noise as highlighted in red in Figure 12c. That will maintain the same SA region compared with the OQW while reducing the biasing current completely in the SR region for the input transistors M3-4 to maximize the SNR for the SRO under the trade-off of lower sensitivity accumulation compared to the case of V 1 = V 1a .

Simulation Results and Discussion
The proposed SR receiver with PLL frequency calibration and CQW technique is implemented in at transistor level using 180 nm SMIC CMOS technology. An inductor of 3 nH with a quality factor (Q) of 30 and a pair of varactors with a nominal capacitance of 0.5 pF (at V tune = 0.5V) are used to set the SRO resonance frequency around 2.46 GHz. A Gm-boosted crossing-coupled PMOS pair with an aspect ratio of 450/0.18 is used to provide sufficient negative transconductance under a supply voltage of 1 V. The aspect ratio of input pair (M3/M4/M7/M8) in Figure 10 is 150/0.18. Figure 13 is the simulation results to illustrate the operating principle of the proposed SRO with CQW technique. The CQW extends the SA region during the control voltage V 1 , while V 2 is only used to generate fast start-up oscillation. As a result, the effect of the process variation on slope changes can be reduced. As shown, the process variations does not degrade the sensitivity accumulation because the SA region has been extended over the entire quenching cycle and the SRO is able to detect the input signal correctly with different slopes of the voltage V 1 .
In contrast to Figure 13, Figure 14 show how the conventional OQW suffers under process variations which dramatically reduce the sensitivity of the SRO. That is indicated from the oscillation at the SRO output during the absence of input OOK signal. Figures 15 and 16 show the immunity of the proposed the proposed CQW architecture against voltage and temperature variations respectively. Figure 17 shows how the proposed CQW architecture can reduce the oscillation at the SRO output during the absence of input signal with the presence of noise compared with OQW. That is indicated by reducing the oscillation at the SRO output during the absence of input OOK signal.

Figure 14.
The simulation results illustrating the SRR's immunity against process variations when the conventional optimal quenching waveform is applied. From top to bottom: input OOK signal, the combined CQW waveform, and the SRO output signals under process variation (the red line for the fastest-speed process corner (FF), the black is for the typical (TT), and the blue is for the slowest one (SS)).  The simulation results illustrating the SRR's immunity against process variations when the conventional optimal quenching waveform is applied. From top to bottom: input OOK signal, the combined CQW waveform, and the SRO output signals under process variation (the red line for the fastest-speed process corner (FF), the black is for the typical (TT), and the blue is for the slowest one (SS)).        Figure 18 shows the proposed PLL with initial phase error reduction. Clk is set to 50 MHz and the division ratio of and are 5 and 123 respectively to expect a final of 2.46 GHz. As Figure 16 indicates, due to the random initial phase ∆ between EN and Clk , the time shift can be up to 18 ns. However, by applying the proposed initial phase error reduction, the actual phase error can be shortened to be around 0.12 ns. Therefore, the proposed PLL can differentiate the small frequency deviation between Clk and Clk and then adjust the voltage V in each calibration cycle. Figure 19 illustrates the proposed frequency calibration process during SR receiverʹs receiving. In simulations, each quenching cycle lasts 1.25 μS to match a data rate of 800 kbps wherein the SR phase only occupies a length of 300 ns. Despite the short SR phase, the proposed PLL is still able to adjust the oscillating frequency from 2.55 GHz to 2.46 GHz with a frequency error of less than 10 MHz as shown. In contrast, when the initial phase error reduction is disabled, the PLL fails to obtain sufficiently precise frequency error detection, and the initial phase error misleads the adjustment of V tune . As a result, the PLL finally settles down to a wrong as shown in Figure 20.   Figure 18 shows the proposed PLL with initial phase error reduction. Clk in is set to 50 MHz and the division ratio of N CT1 and N PSC are 5 and 123 respectively to expect a final f SRO of 2.46 GHz. As Figure 16 indicates, due to the random initial phase ∆ϕ i between EN and Clk in , the time shift can be up to 18 ns. However, by applying the proposed initial phase error reduction, the actual phase error can be shortened to be around 0.12 ns. Therefore, the proposed PLL can differentiate the small frequency deviation between Clk ref and Clk fb and then adjust the voltage V tune in each calibration cycle. Figure 19 illustrates the proposed frequency calibration process during SR receiver's receiving. In simulations, each quenching cycle lasts 1.25 µS to match a data rate of 800 kbps wherein the SR phase only occupies a length of 300 ns. Despite the short SR phase, the proposed PLL is still able to adjust the oscillating frequency from 2.55 GHz to 2.46 GHz with a frequency error of less than 10 MHz as shown. In contrast, when the initial phase error reduction is disabled, the PLL fails to obtain sufficiently precise frequency error detection, and the initial phase error misleads the adjustment of V tune . As a result, the PLL finally settles down to a wrong f SRO as shown in Figure 20.  Figure 18 shows the proposed PLL with initial phase error reduction. Clk is set to 50 MHz and the division ratio of and are 5 and 123 respectively to expect a final of 2.46 GHz. As Figure 16 indicates, due to the random initial phase ∆ between EN and Clk , the time shift can be up to 18 ns. However, by applying the proposed initial phase error reduction, the actual phase error can be shortened to be around 0.12 ns. Therefore, the proposed PLL can differentiate the small frequency deviation between Clk and Clk and then adjust the voltage V in each calibration cycle. Figure 19 illustrates the proposed frequency calibration process during SR receiverʹs receiving. In simulations, each quenching cycle lasts 1.25 μS to match a data rate of 800 kbps wherein the SR phase only occupies a length of 300 ns. Despite the short SR phase, the proposed PLL is still able to adjust the oscillating frequency from 2.55 GHz to 2.46 GHz with a frequency error of less than 10 MHz as shown. In contrast, when the initial phase error reduction is disabled, the PLL fails to obtain sufficiently precise frequency error detection, and the initial phase error misleads the adjustment of V tune . As a result, the PLL finally settles down to a wrong as shown in Figure 20.    In the following simulation the immunity of the proposed PLL is evaluated under technology process variations. The SRO's frequency versus voltage curves are tested with corners variation as shown in Figure 21. The frequency variation can be up to 50 MHz with a fixed due to the process variation while the voltage-to-frequency gain is about −267 MHz/V at 2.46 GHz under the TT process corner. Figure 22a shows the settling behavior of PLL is with different values of changed by selecting different according to Equation (13). As shown in Figure 22a, when β is less than 2, all waveforms of V gradually converge but with ripple due to the random ∆ in each cycle. A larger leads to a faster convergence, but more ripples. To achieve a precise frequency calibration, is set to 0.27. In this case, the settling time of PLL is about 35 μs, and the ripple of is limited to less than 25 mV which corresponds to a frequency variation of 6.7 MHz. Figure 22b shows the settling behavior under various process corners with 0.27. It can be seen that the waveforms can converge regardless of the process variation with a maximum voltage ripple less than 25 mV.  In the following simulation the immunity of the proposed PLL is evaluated under technology process variations. The SRO's frequency versus voltage curves are tested with corners variation as shown in Figure 21. The frequency variation can be up to 50 MHz with a fixed due to the process variation while the voltage-to-frequency gain is about −267 MHz/V at 2.46 GHz under the TT process corner. Figure 22a shows the settling behavior of PLL is with different values of changed by selecting different according to Equation (13). As shown in Figure 22a, when β is less than 2, all waveforms of V gradually converge but with ripple due to the random ∆ in each cycle. A larger leads to a faster convergence, but more ripples. To achieve a precise frequency calibration, is set to 0.27. In this case, the settling time of PLL is about 35 μs, and the ripple of is limited to less than 25 mV which corresponds to a frequency variation of 6.7 MHz. Figure 22b shows the settling behavior under various process corners with 0.27. It can be seen that the waveforms can converge regardless of the process variation with a maximum voltage ripple less than 25 mV. In the following simulation the immunity of the proposed PLL is evaluated under technology process variations. The SRO's frequency versus voltage curves are tested with corners variation as shown in Figure 21. The frequency variation can be up to 50 MHz with a fixed V tune due to the process variation while the voltage-to-frequency gain is about −267 MHz/V at f SRO = 2.46 GHz under the TT process corner. Figure 22a shows the settling behavior of PLL is with different values of β changed by selecting different I CP according to Equation (13). As shown in Figure 22a, when β is less than 2, all waveforms of V tune gradually converge but with ripple due to the random ∆ϕ i in each cycle. A larger β leads to a faster convergence, but more ripples. To achieve a precise frequency calibration, β is set to 0.27. In this case, the settling time of PLL is about 35 µs, and the ripple of V tune is limited to less than 25 mV which corresponds to a frequency variation of 6.7 MHz. Figure 22b shows the settling behavior under various process corners with β = 0.27. It can be seen that the waveforms can converge regardless of the process variation with a maximum voltage ripple less than 25 mV.  Figure 23 shows the breakdown power consumption of the proposed SR receiver. The total power consumption of the receiver is about 802 μW, including the main blocks of the receiver: the SRO, the envelop detector (ED), and the demodulator (Dem.), contributes a power consumption of about 395 μW; while the PLL consumes a power of 407 μW in average. Table 1 summarizes the performance of this work in comparison with the state-of-arts. The main features of the proposed design are the ability to achieve background frequency calibration with a good sensitivity and less power consumption compared to the counterparts.  Figure 23 shows the breakdown power consumption of the proposed SR receiver. The total power consumption of the receiver is about 802 μW, including the main blocks of the receiver: the SRO, the envelop detector (ED), and the demodulator (Dem.), contributes a power consumption of about 395 μW; while the PLL consumes a power of 407 μW in average. Table 1 summarizes the performance of this work in comparison with the state-of-arts. The main features of the proposed design are the ability to achieve background frequency calibration with a good sensitivity and less power consumption compared to the counterparts.  Figure 23 shows the breakdown power consumption of the proposed SR receiver. The total power consumption of the receiver is about 802 µW, including the main blocks of the receiver: the SRO, the envelop detector (ED), and the demodulator (Dem.), contributes a power consumption of about 395 µW; while the PLL consumes a power of 407 µW in average. Table 1 summarizes the performance of this work in comparison with the state-of-arts. The main features of the proposed design are the ability to achieve background frequency calibration with a good sensitivity and less power consumption compared to the counterparts.  Figure 23 shows the breakdown power consumption of the proposed SR receiver. The total power consumption of the receiver is about 802 μW, including the main blocks of the receiver: the SRO, the envelop detector (ED), and the demodulator (Dem.), contributes a power consumption of about 395 μW; while the PLL consumes a power of 407 μW in average. Table 1 summarizes the performance of this work in comparison with the state-of-arts. The main features of the proposed design are the ability to achieve background frequency calibration with a good sensitivity and less power consumption compared to the counterparts.

Conclusions
This paper proposed a new background frequency calibration and quenching techniques to improve the sensitivity and selectivity of SR receiver. In this work, the importance of cancelling of the initial phase error is discussed and frequency calibration using a PLL with the initial phase error reduction has been proposed to calibrate the SRO center frequency without interrupting the incoming data stream and simultaneously improving the selectivity of the SR receiver. The proposed architecture achieves much shorter phase detecting time to support discrete frequency calibration compared with conventional techniques. Moreover, the proposed CQW quenching technique allows the sensitivity accumulation region to be enlarged through the entire quenching cycle which improves the SRO sensitivity, noise performance, and reduce the power consumption compared with conventional SRO architecture. Meanwhile, immunity to PVT variations has also been improved due to the SA region extension.